From c07b9d1722cc320e65c9f4e091908d369b9a86c2 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 18 Apr 2022 01:30:03 +0000
Subject: [PATCH] Renamed FinalAMOWriteDataM to AMOWriteDataM

---
 pipelined/src/lsu/atomic.sv       |  4 ++--
 pipelined/src/lsu/lsu.sv          |  8 ++++----
 pipelined/src/lsu/subwordwrite.sv | 18 +++++++++---------
 3 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv
index d2054a78..a5dd06ac 100644
--- a/pipelined/src/lsu/atomic.sv
+++ b/pipelined/src/lsu/atomic.sv
@@ -41,7 +41,7 @@ module atomic (
   input logic [1:0]          LSUAtomicM,
   input logic [1:0]          PreLSURWM,
   input logic                IgnoreRequest,
-  output logic [`XLEN-1:0]   FinalAMOWriteDataM,
+  output logic [`XLEN-1:0]   AMOWriteDataM,
   output logic               SquashSCW,
   output logic [1:0]         LSURWM);
 
@@ -50,7 +50,7 @@ module atomic (
 
   amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), 
                 .result(AMOResult));
-  mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
+  mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM);
   assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
   lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
     .SquashSCW, .LSURWM);
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 1e732516..a4403c28 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -181,7 +181,7 @@ module lsu (
   //  Memory System
   //  Either Data Cache or Data Tightly Integrated Memory or just bus interface
   /////////////////////////////////////////////////////////////////////////////////////////////
-  logic [`XLEN-1:0]    FinalAMOWriteDataM, FinalWriteDataM;
+  logic [`XLEN-1:0]    AMOWriteDataM, FinalWriteDataM;
   logic [`XLEN-1:0]    ReadDataWordM;
   logic [`XLEN-1:0]    ReadDataWordMuxM;
   logic                IgnoreRequest;
@@ -255,13 +255,13 @@ module lsu (
   if (`A_SUPPORTED) begin:atomic
     atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, 
       .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, 
-      .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
+      .AMOWriteDataM, .SquashSCW, .LSURWM);
   end else begin:lrsc
-    assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
+    assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign AMOWriteDataM = LSUWriteDataM;
   end
 
   subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
-    .LSUFunct3M, .FinalAMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
+    .LSUFunct3M, .AMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
 
   
 endmodule
diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv
index 5244aded..6a599ab5 100644
--- a/pipelined/src/lsu/subwordwrite.sv
+++ b/pipelined/src/lsu/subwordwrite.sv
@@ -33,7 +33,7 @@
 module subwordwrite (
   input logic [2:0]          LSUPAdrM,
   input logic [2:0]          LSUFunct3M,
-  input logic [`XLEN-1:0]    FinalAMOWriteDataM,
+  input logic [`XLEN-1:0]    AMOWriteDataM,
   output logic [`XLEN-1:0]   FinalWriteDataM,
   output logic [`XLEN/8-1:0] ByteMaskM
 );
@@ -46,18 +46,18 @@ module subwordwrite (
   if (`XLEN == 64) begin:sww
     always_comb 
       case(LSUFunct3M[1:0])
-        2'b00:  FinalWriteDataM = {8{FinalAMOWriteDataM[7:0]}};  // sb
-        2'b01:  FinalWriteDataM = {4{FinalAMOWriteDataM[15:0]}}; // sh
-        2'b10:  FinalWriteDataM = {2{FinalAMOWriteDataM[31:0]}}; // sw
-        2'b11:  FinalWriteDataM = FinalAMOWriteDataM;            // sw
+        2'b00:  FinalWriteDataM = {8{AMOWriteDataM[7:0]}};  // sb
+        2'b01:  FinalWriteDataM = {4{AMOWriteDataM[15:0]}}; // sh
+        2'b10:  FinalWriteDataM = {2{AMOWriteDataM[31:0]}}; // sw
+        2'b11:  FinalWriteDataM = AMOWriteDataM;            // sw
       endcase
   end else begin:sww // 32-bit
     always_comb 
       case(LSUFunct3M[1:0])
-        2'b00:  FinalWriteDataM = {4{FinalAMOWriteDataM[7:0]}};  // sb
-        2'b01:  FinalWriteDataM = {2{FinalAMOWriteDataM[15:0]}}; // sh
-        2'b10:  FinalWriteDataM = FinalAMOWriteDataM;            // sw
-        default: FinalWriteDataM = FinalAMOWriteDataM; // shouldn't happen
+        2'b00:  FinalWriteDataM = {4{AMOWriteDataM[7:0]}};  // sb
+        2'b01:  FinalWriteDataM = {2{AMOWriteDataM[15:0]}}; // sh
+        2'b10:  FinalWriteDataM = AMOWriteDataM;            // sw
+        default: FinalWriteDataM = AMOWriteDataM; // shouldn't happen
       endcase
   end
 endmodule