diff --git a/.gitignore b/.gitignore index e8ff572f..38d466cd 100644 --- a/.gitignore +++ b/.gitignore @@ -111,3 +111,4 @@ sim/imperas.log sim/results-error/ sim/test1.rep sim/vsim.log +tests/coverage/*.S diff --git a/sim/Makefile b/sim/Makefile index 6a917bcd..1c31e1f2 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,3 +1,26 @@ +coverage: + #make -C ../tests/coverage --jobs + #iter-elf.bash --cover --search ../tests/coverage + vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb riscv.ucdb -logfile cov/log + vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt + vcover report cov/cov.ucdb -details -instance=/core/ebu. > cov/rv64gc_coverage_ebu.rpt + vcover report cov/cov.ucdb -details -instance=/core/priv. > cov/rv64gc_coverage_priv.rpt + vcover report cov/cov.ucdb -details -instance=/core/ifu. > cov/rv64gc_coverage_ifu.rpt + vcover report cov/cov.ucdb -details -instance=/core/lsu. > cov/rv64gc_coverage_lsu.rpt + vcover report cov/cov.ucdb -details -instance=/core/fpu. > cov/rv64gc_coverage_fpu.rpt + vcover report cov/cov.ucdb -details -instance=/core/ieu. > cov/rv64gc_coverage_ieu.rpt + vcover report cov/cov.ucdb -below 100 -details -instance=/core/ebu. > cov/rv64gc_uncovered_ebu.rpt + vcover report cov/cov.ucdb -below 100 -details -instance=/core/priv. > cov/rv64gc_uncovered_priv.rpt + vcover report cov/cov.ucdb -below 100 -details -instance=/core/ifu. > cov/rv64gc_uncovered_ifu.rpt + vcover report cov/cov.ucdb -below 100 -details -instance=/core/lsu. > cov/rv64gc_uncovered_lsu.rpt + vcover report cov/cov.ucdb -below 100 -details -instance=/core/fpu. > cov/rv64gc_uncovered_fpu.rpt + vcover report cov/cov.ucdb -below 100 -details -instance=/core/ieu. > cov/rv64gc_uncovered_ieu.rpt + vcover report -hierarchical cov/cov.ucdb > cov/rv64gc_coverage_hierarchical.rpt + vcover report -below 100 -hierarchical cov/cov.ucdb > cov/rv64gc_uncovered_hierarchical.rpt +# vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt +# vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt + vcover report -details -threshH 100 -html cov/cov.ucdb + all: riscoftests memfiles # *** Build old tests/imperas-riscv-tests for now; # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test diff --git a/sim/regression-wally b/sim/regression-wally index 3b0032f7..f323dba6 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -129,6 +129,8 @@ for test in ahbTests: tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] + tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] +# tests64gc.append(["imperas64f", "imperas64d", "imperas64c", "imperas64i"]) coverStr = '-coverage' else: coverStr = '' @@ -215,12 +217,13 @@ def main(): # Coverage report if coverage: - print('Generating coverage report') - os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log') - os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt') - os.system('vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt') - os.system('vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt') - os.system('vcover report -details -threshH 100 -html cov/cov.ucdb') + os.system('make coverage') + #print('Generating coverage report') + #os.system('vcover merge -out cov/cov.ucdb cov/rv64gc_arch64i.ucdb cov/rv64gc*.ucdb -logfile cov/log') + #os.system('vcover report -details cov/cov.ucdb > cov/rv64gc_coverage_details.rpt') + #os.system('vcover report -below 100 cov/cov.ucdb > cov/rv64gc_coverage.rpt') + #os.system('vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt') + #os.system('vcover report -details -threshH 100 -html cov/cov.ucdb') # Count the number of failures if num_fail: print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail) diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index 190ff77f..0ab0e706 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -32,7 +32,7 @@ `include "wally-config.vh" module decompress ( - input logic [31:0] InstrRawD, // 32-bit instruction or raw un decompress instruction + input logic [31:0] InstrRawD, // 32-bit instruction or raw compressed 16-bit instruction in bottom half output logic [31:0] InstrD, // Decompressed instruction output logic IllegalCompInstrD // Invalid decompressed instruction ); diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index d8d48cbf..afca0841 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -62,6 +62,7 @@ module ifu ( output logic [`XLEN-1:0] PC2NextF, // Selected PC between branch prediction and next valid PC if CSRWriteFence output logic [31:0] InstrD, // The decoded instruction in Decode stage output logic [31:0] InstrM, // The decoded instruction in Memory stage + output logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL output logic [`XLEN-1:0] PCM, // Memory stage instruction address // branch predictor output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br @@ -90,7 +91,7 @@ module ifu ( output logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk output logic InstrUpdateDAF, // ITLB hit needs to update dirty or access bits input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP address from privileged unit + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP address from privileged unit output logic InstrAccessFaultF, // Instruction access fault output logic ICacheAccess, // Report I$ read to performance counters output logic ICacheMiss // Report I$ miss to performance counters @@ -116,6 +117,7 @@ module ifu ( logic CompressedF; // The fetched instruction is compressed logic CompressedD; // The decoded instruction is compressed logic CompressedE; // The execution instruction is compressed + logic CompressedM; // The execution instruction is compressed logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage logic IllegalIEUInstrD; // IEU Instruction (regular or compressed) is not good @@ -135,6 +137,7 @@ module ifu ( logic BusCommittedF; // Bus memory operation in flight, delay interrupts logic CacheCommittedF; // I$ memory operation started, delay interrupts logic SelIROM; // PMA indicates instruction address is in the IROM + logic [15:0] InstrRawE, InstrRawM; assign PCFExt = {2'b00, PCSpillF}; @@ -385,5 +388,10 @@ module ifu ( flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD); flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE); assign PCLinkE = PCE + (CompressedE ? 2 : 4); - + + // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception + flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE); + flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM); + flopenrc #(1) CompressedMReg(clk, reset, FlushM, ~StallM, CompressedE, CompressedM); + mux2 #(32) InstrOrigMux(InstrM, {16'b0, InstrRawM}, CompressedM, InstrOrigM); endmodule diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 628c85bb..edb3a93d 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -88,7 +88,7 @@ module lsu ( output logic ITLBWriteF, // Write PTE to ITLB output logic SelHPTW, // During a HPTW walk the effective privilege mode becomes S_MODE input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration from privileged unit - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP address from privileged unit ); logic [`XLEN+1:0] IEUAdrExtM; // Memory stage address zero-extended to PA_BITS or XLEN whichever is longer diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index e3cd8031..4accf0cb 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -56,7 +56,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( // PMA checker signals input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses ); logic [`PA_BITS-1:0] TLBPAdr; // physical address for TLB diff --git a/src/mmu/pmpadrdec.sv b/src/mmu/pmpadrdec.sv index 5f666eea..5e63e7c6 100644 --- a/src/mmu/pmpadrdec.sv +++ b/src/mmu/pmpadrdec.sv @@ -35,7 +35,7 @@ module pmpadrdec ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic [7:0] PMPCfg, - input logic [`XLEN-1:0] PMPAdr, + input logic [`PA_BITS-3:0] PMPAdr, input logic PAgePMPAdrIn, output logic PAgePMPAdrOut, output logic Match, Active, @@ -60,7 +60,7 @@ module pmpadrdec ( // Top-of-range (TOR) // Append two implicit trailing 0's to PMPAdr value - assign CurrentAdrFull = {PMPAdr[`PA_BITS-3:0], 2'b00}; + assign CurrentAdrFull = {PMPAdr, 2'b00}; assign PAltPMPAdr = {1'b0, PhysicalAddress} < {1'b0, CurrentAdrFull}; // unsigned comparison assign PAgePMPAdrOut = ~PAltPMPAdr; assign TORMatch = PAgePMPAdrIn & PAltPMPAdr; @@ -69,10 +69,10 @@ module pmpadrdec ( logic [`PA_BITS-1:0] NAMask, NABase; assign NAMask[1:0] = {2'b11}; - assign NAMask[`PA_BITS-1:2] = (PMPAdr[`PA_BITS-3:0] + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr[`PA_BITS-3:0]; + assign NAMask[`PA_BITS-1:2] = (PMPAdr + {{(`PA_BITS-3){1'b0}}, (AdrMode == NAPOT)}) ^ PMPAdr; // form a mask where the bottom k bits are 1, corresponding to a size of 2^k bytes for this memory region. // This assumes we're using at least an NA4 region, but works for any size NAPOT region. - assign NABase = {(PMPAdr[`PA_BITS-3:0] & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. + assign NABase = {(PMPAdr & ~NAMask[`PA_BITS-1:2]), 2'b00}; // base physical address of the pmp. assign NAMatch = &((NABase ~^ PhysicalAddress) | NAMask); // check if upper bits of base address match, ignore lower bits correspoonding to inside the memory range diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index 828747e2..b7582425 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -42,7 +42,7 @@ module pmpchecker ( // keyword, the compiler warns us that it's interpreting the signal as a var, // which we might not intend. input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], input logic ExecuteAccessF, WriteAccessM, ReadAccessM, output logic PMPInstrAccessFaultF, output logic PMPLoadAccessFaultM, diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index 06762e6d..050cf363 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -37,6 +37,7 @@ module csr #(parameter input logic FlushM, FlushW, input logic StallE, StallM, StallW, input logic [31:0] InstrM, // current instruction + input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL input logic [`XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return logic input logic [`XLEN-1:0] SrcAM, IEUAdrM, // SrcA and memory address from IEU input logic CSRReadM, CSRWriteM, // read or write CSR @@ -85,7 +86,7 @@ module csr #(parameter output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, STATUS_TW, output logic [1:0] STATUS_FS, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], + output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0], output logic [2:0] FRM_REGW, // output logic [`XLEN-1:0] CSRReadValW, // value read from CSR @@ -133,7 +134,7 @@ module csr #(parameter if (InterruptM) NextFaultMtvalM = 0; else case (CauseM) 12, 1, 3: NextFaultMtvalM = PCM; // Instruction page/access faults, breakpoint - 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM}; // Illegal instruction fault // *** this should probably set to the uncompressed instruction + 2: NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrOrigM}; // Illegal instruction fault 0, 4, 6, 13, 15, 5, 7: NextFaultMtvalM = IEUAdrM; // Instruction misaligned, Load/Store Misaligned/page/access faults default: NextFaultMtvalM = 0; // Ecall, interrupts endcase diff --git a/src/privileged/csrm.sv b/src/privileged/csrm.sv index cbeab5fd..9fd46b2e 100644 --- a/src/privileged/csrm.sv +++ b/src/privileged/csrm.sv @@ -85,7 +85,7 @@ module csrm #(parameter output logic [`XLEN-1:0] MEDELEG_REGW, output logic [11:0] MIDELEG_REGW, output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], + output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], output logic WriteMSTATUSM, WriteMSTATUSHM, output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM ); @@ -113,7 +113,7 @@ module csrm #(parameter assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01); assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & InstrValidNotFlushedM & ~ADDRLocked[i]; - flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]); + flopenr #(`PA_BITS-2) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM[`PA_BITS-3:0], PMPADDR_ARRAY_REGW[i]); if (`XLEN==64) begin assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & InstrValidNotFlushedM & ~CFGLocked[i]; flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]); @@ -171,7 +171,7 @@ module csrm #(parameter entry = '0; IllegalCSRMAccessM = !(`S_SUPPORTED) & (CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry - CSRMReadValM = PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]; + CSRMReadValM = {{(`XLEN-(`PA_BITS-2)){1'b0}}, PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0]}; else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin if (`XLEN==64) begin entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64 diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 1795f72c..1a590665 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -99,7 +99,7 @@ module csrs #(parameter flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW); else assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported - flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); + flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); if (`SSTC_SUPPORTED) begin if (`XLEN == 64) flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW); diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 293fc4b3..6d97fe8b 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -37,6 +37,7 @@ module privileged ( input logic CSRReadM, CSRWriteM, // Read or write CSRs input logic [`XLEN-1:0] SrcAM, // GPR register to write input logic [31:0] InstrM, // Instruction + input logic [31:0] InstrOrigM, // Original compressed or uncompressed instruction in Memory stage for Illegal Instruction MTVAL input logic [`XLEN-1:0] IEUAdrM, // address from IEU input logic [`XLEN-1:0] PCM, PC2NextF, // program counter, next PC going to trap/return PC logic // control signals @@ -81,7 +82,7 @@ module privileged ( output logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // status register bits output logic [1:0] STATUS_MPP, STATUS_FS, // status register bits output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration entries to MMU - output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // PMP address entries to MMU + output var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // PMP address entries to MMU output logic [2:0] FRM_REGW, // FPU rounding mode // PC logic output in privileged unit output logic [`XLEN-1:0] UnalignedPCNextF, // Next PC from trap/return PC logic @@ -126,7 +127,7 @@ module privileged ( // Control and Status Registers csr csr(.clk, .reset, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF, + .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .PC2NextF, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 60166862..8f7314ba 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -62,7 +62,7 @@ module wallypipelinedcore ( logic [`XLEN-1:0] SrcAM; logic [2:0] Funct3E; logic [31:0] InstrD; - logic [31:0] InstrM; + logic [31:0] InstrM, InstrOrigM; logic [`XLEN-1:0] PCSpillF, PCE, PCLinkE; logic [`XLEN-1:0] PCM; logic [`XLEN-1:0] CSRReadValW, MDUResultW; @@ -110,7 +110,7 @@ module wallypipelinedcore ( logic SelHPTW; // PMA checker signals - var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]; + var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0]; var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0]; // IMem stalls @@ -176,7 +176,7 @@ module wallypipelinedcore ( .PCLinkE, .PCSrcE, .IEUAdrE, .IEUAdrM, .PCE, .BPWrongE, .BPWrongM, // Mem .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, - .InstrD, .InstrM, .PCM, .InstrClassM, .BPDirPredWrongM, + .InstrD, .InstrM, .InstrOrigM, .PCM, .InstrClassM, .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, // Faults out .IllegalBaseInstrD, .IllegalFPUInstrD, .InstrPageFaultF, .IllegalIEUFPUInstrD, .InstrMisalignedFaultM, @@ -286,7 +286,7 @@ module wallypipelinedcore ( .clk, .reset, .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PC2NextF, - .InstrM, .CSRReadValW, .UnalignedPCNextF, + .InstrM, .InstrOrigM, .CSRReadValW, .UnalignedPCNextF, .RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF, .InstrValidM, .CommittedM, .CommittedF, .FRegWriteM, .LoadStallD, .StoreStallD, diff --git a/testbench/tests.vh b/testbench/tests.vh index 6355b2d1..10633276 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -34,7 +34,7 @@ // *** remove MYIMPERASTEST cases when ported string tvpaths[] = '{ - "../addins/imperas-riscv-tests/work/", + "$RISCV/imperas-riscv-tests/work/", "../tests/riscof/work/riscv-arch-test/", "../tests/riscof/work/wally-riscv-arch-test/", "../tests/imperas-riscv-tests/work/", diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 7773e7c1..e026fa41 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -1,19 +1,21 @@ -TARGET = badinstr +SRCS = $(wildcard *.S) +PROGS = $(patsubst %.S,%,$(SRCS)) -$(TARGET).objdump: $(TARGET) - riscv64-unknown-elf-objdump -D $(TARGET) > $(TARGET).objdump +all: $(PROGS) + +%: %.S WALLY-init-lib.h Makefile + echo $@ + riscv64-unknown-elf-gcc -g -o $@.elf -march=rv64gc -mabi=lp64 -mcmodel=medany \ + -nostartfiles -T../../examples/link/link.ld $@.S + riscv64-unknown-elf-objdump -D $@.elf > $@.objdump -$(TARGET): $(TARGET).S WALLY-init-lib.S Makefile - riscv64-unknown-elf-gcc -g -o $(TARGET) -march=rv64gc -mabi=lp64 -mcmodel=medany \ - -nostartfiles -T../../examples/link/link.ld $(TARGET).S - -sim: - spike +signature=$(TARGET).signature.output +signature-granularity=8 $(TARGET) - diff --ignore-case $(TARGET).signature.output $(TARGET).reference_output || exit +sim: %.elf + spike +signature=%.signature.output +signature-granularity=8 %.elf + diff --ignore-case %.signature.output %.reference_output || exit echo "Signature matches! Success!" clean: - rm -f $(TARGET) $(TARGET).objdump $(TARGET).signature.output + rm -f *.elf *.objdump *.signature.output diff --git a/tests/coverage/WALLY-init-lib.S b/tests/coverage/WALLY-init-lib.h similarity index 99% rename from tests/coverage/WALLY-init-lib.S rename to tests/coverage/WALLY-init-lib.h index 2d30aba2..4de5e768 100644 --- a/tests/coverage/WALLY-init-lib.S +++ b/tests/coverage/WALLY-init-lib.h @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// WALLY-init-lib.S +// WALLY-init-lib.h // // Written: David_Harris@hmc.edu 21 March 2023 // diff --git a/tests/coverage/badinstr.S b/tests/coverage/badinstr.S index 9ec6844d..e77f5c98 100644 --- a/tests/coverage/badinstr.S +++ b/tests/coverage/badinstr.S @@ -24,11 +24,12 @@ //////////////////////////////////////////////////////////////////////////////////////////////// // load code to initalize stack, handle interrupts, terminate -#include "WALLY-init-lib.S" +#include "WALLY-init-lib.h" main: - .word 0x00000033 // legal instruction - .word 0x80000033 // illegal instruction + .word 0x00000033 // legal R-type instruction + .word 0x80000033 // illegal R-type instruction + .word 0x00007003 // illegal Load instruction .word 0x00000000 // illegal instruction j done