From bfa69ea2b3f496850efa6c43b98af7596278a5ce Mon Sep 17 00:00:00 2001
From: James Stine <James Stine>
Date: Thu, 2 Feb 2023 13:54:25 -0600
Subject: [PATCH] Forgot 1p ram for rv32gc : cache data 64x128 and cache tags
 64x22

---
 pipelined/src/generic/mem/ram1p1rwbe.sv       | 20 ++++++++++
 pipelined/src/generic/mem/ram1p1rwbe_64x22.sv | 40 +++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100755 pipelined/src/generic/mem/ram1p1rwbe_64x22.sv

diff --git a/pipelined/src/generic/mem/ram1p1rwbe.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv
index 028f928c..e33e708a 100644
--- a/pipelined/src/generic/mem/ram1p1rwbe.sv
+++ b/pipelined/src/generic/mem/ram1p1rwbe.sv
@@ -68,6 +68,26 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
      ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
 			      .A(addr), .D(din), 
 			      .BWEB(~BitWriteMask), .Q(dout));
+
+  end if (`USE_SRAM == 1 && WIDTH == 128 && DEPTH == 32) begin
+     genvar index;
+     // 64 x 128-bit SRAM
+     logic [WIDTH-1:0] BitWriteMask;
+     for (index=0; index < WIDTH; index++) 
+       assign BitWriteMask[index] = bwe[index/8];
+    TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
+			      .A(addr), .D(din), 
+			      .BWEB(~BitWriteMask), .Q(dout));
+     
+  end else if (`USE_SRAM == 1 && WIDTH == 22  && DEPTH == 32) begin
+     genvar index;
+     // 64 x 22-bit SRAM
+     logic [WIDTH-1:0] BitWriteMask;
+     for (index=0; index < WIDTH; index++) 
+       assign BitWriteMask[index] = bwe[index/8];
+     ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
+			      .A(addr), .D(din), 
+			      .BWEB(~BitWriteMask), .Q(dout));     
     
   // ***************************************************************************
   // READ first SRAM model
diff --git a/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv b/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv
new file mode 100755
index 00000000..84c8d1b7
--- /dev/null
+++ b/pipelined/src/generic/mem/ram1p1rwbe_64x22.sv
@@ -0,0 +1,40 @@
+///////////////////////////////////////////
+// ram1p1rwbe_64x22.sv
+//
+// Written: james.stine@okstate.edu 2 Feburary 2023
+// Modified: 
+//
+// Purpose: RAM wrapper for instantiating RAM IP
+// 
+// A component of the CORE-V-WALLY configurable RISC-V project.
+// 
+// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+module ram1p1rwbe_64x22( 
+  input  logic          CLK, 
+  input  logic 	        CEB, 
+  input  logic          WEB,
+  input  logic [5:0]    A, 
+  input  logic [127:0]  D,
+  input  logic [127:0]  BWEB, 
+  output logic [127:0]  Q
+);
+
+   // replace "generic64x22RAM" with "TS1N..64X22.." module from your memory vendor
+   generic64x22RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
+
+endmodule