From bd87af478ac52066bf0decd2f0f53fcd73876c0a Mon Sep 17 00:00:00 2001
From: Kip Macsai-Goren <kipmacsaigoren@gmail.com>
Date: Fri, 22 Apr 2022 22:45:23 +0000
Subject: [PATCH] Changed mtval for instruction misaligned fault to get address
 from ieuAdrM (Jal/branch target address)

---
 pipelined/src/ifu/ifu.sv                  | 2 --
 pipelined/src/privileged/privileged.sv    | 4 ++--
 pipelined/src/privileged/trap.sv          | 4 ++--
 pipelined/src/wally/wallypipelinedcore.sv | 4 +---
 4 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index 5b42b411..f7b23ccf 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -65,7 +65,6 @@ module ifu (
 	output logic 				InstrPageFaultF,
 	output logic 				IllegalIEUInstrFaultD,
 	output logic 				InstrMisalignedFaultM,
-	output logic [`XLEN-1:0] 	InstrMisalignedAdrM,
 	input logic 				ExceptionM,
 	// mmu management
 	input logic [1:0] 			PrivilegeModeW,
@@ -330,7 +329,6 @@ module ifu (
   // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
   assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE;
   flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
-  flopenr #(`XLEN) InstrMisalignedAdrReg(clk, reset, ~StallM, PCNextF, InstrMisalignedAdrM);
 
   // Instruction and PC/PCLink pipeline registers
   mux2    #(32)    FlushInstrEMux(InstrD, nop, FlushE, NextInstrD);
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index b429a14c..4aa9bf7c 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -57,7 +57,7 @@ module privileged (
   input  logic             StoreAmoMisalignedFaultM,
   input  logic             TimerIntM, MExtIntM, SExtIntM, SwIntM,
   input  logic [63:0]      MTIME_CLINT, 
-  input  logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
+  input  logic [`XLEN-1:0] IEUAdrM,
   input  logic [4:0]       SetFflagsM,
 
   // Trap signals from pmp/pma in mmu
@@ -222,7 +222,7 @@ module privileged (
             .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW, .MIDELEG_REGW,
             .STATUS_MIE, .STATUS_SIE,
             .PCM,
-            .InstrMisalignedAdrM, .IEUAdrM, 
+            .IEUAdrM, 
             .InstrM,
             .InstrValidM, .CommittedM, .DivE, 
             .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index 1cc21579..5a362afb 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -44,7 +44,7 @@ module trap (
   (* mark_debug = "true" *) input logic [11:0] 	   MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW, MIDELEG_REGW,
   input logic 		   STATUS_MIE, STATUS_SIE,
   input logic [`XLEN-1:0]  PCM,
-  input logic [`XLEN-1:0]  InstrMisalignedAdrM, IEUAdrM, 
+  input logic [`XLEN-1:0]  IEUAdrM, 
   input logic [31:0] 	   InstrM,
   input logic 		   InstrValidM, CommittedM, DivE, 
   output logic 		   TrapM, MTrapM, STrapM, UTrapM, RetM,
@@ -152,7 +152,7 @@ module trap (
     // Technically 
   
   always_comb 
-    if      (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
+    if      (InstrMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
     else if (LoadMisalignedFaultM)  NextFaultMtvalM = IEUAdrM;
     else if (StoreAmoMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
     else if (BreakpointFaultM)      NextFaultMtvalM = PCM;
diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv
index 1e835504..5f1fc71b 100644
--- a/pipelined/src/wally/wallypipelinedcore.sv
+++ b/pipelined/src/wally/wallypipelinedcore.sv
@@ -82,7 +82,6 @@ module wallypipelinedcore (
   logic             InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM;
   logic             LoadMisalignedFaultM, LoadAccessFaultM;
   logic             StoreAmoMisalignedFaultM, StoreAmoAccessFaultM;
-  logic [`XLEN-1:0]         InstrMisalignedAdrM;
   logic       InvalidateICacheM, FlushDCacheM;
   logic             PCSrcE;
   logic             CSRWritePendingDEM;
@@ -190,7 +189,6 @@ module wallypipelinedcore (
     // Faults
     .IllegalBaseInstrFaultD, .InstrPageFaultF,
     .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
-    .InstrMisalignedAdrM,
 
     // mmu management
     .PrivilegeModeW, .PTE, .PageType, .SATP_REGW,
@@ -332,7 +330,7 @@ module wallypipelinedcore (
          .LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
          .TimerIntM, .MExtIntM, .SExtIntM, .SwIntM,
          .MTIME_CLINT, 
-         .InstrMisalignedAdrM, .IEUAdrM,
+         .IEUAdrM,
          .SetFflagsM,
          // Trap signals from pmp/pma in mmu
          // *** do these need to be split up into one for dmem and one for ifu?