diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
index 2c7a7947..e3368850 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv
@@ -61,8 +61,8 @@ module fdivsqrtfsm(
   // *** start logic is presently in fctl.  Make it look more like integer division start logic
   // DivStartE comes from fctrl, reflecitng the start of floating-point and possibly integer division
   assign DivStartE = (FDivStartE | IDivStartE) & (state == IDLE) & ~StallM;
-  assign DivDone = (state == DONE) | (WZero & (state == BUSY));
-  assign FDivBusyE = (state == BUSY & ~DivDone);
+  assign DivDone = (state == DONE) | (WZero & (state == BUSY)); // *** used in postprocess.sv and round.sv.  This doesn't seem proper.  They break when removed.
+  assign FDivBusyE = (state == BUSY & ~DivDone); // *** want to add | DivStartE but it creates comb loop
 
     // Divider control signals from MDU
   //assign DivBusyE = (state == BUSY) | DivStartE;
diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv
index ee18c4bc..24365cf9 100644
--- a/pipelined/src/fpu/postproc/postprocess.sv
+++ b/pipelined/src/fpu/postproc/postprocess.sv
@@ -129,7 +129,7 @@ module postprocess (
     assign Mult = OpCtrl[2]&~OpCtrl[1]&~OpCtrl[0];
     assign CvtOp = (PostProcSel == 2'b00);
     assign FmaOp = (PostProcSel == 2'b10);
-    assign DivOp = (PostProcSel == 2'b01)&DivDone;
+    assign DivOp = (PostProcSel == 2'b01) & DivDone;
     assign Sqrt =  OpCtrl[0];
 
     // is there an input of infinity or NaN being used