From 8a6eaa23cc3fbb1db56a5df3f8ca73a98dba1d13 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 31 Jan 2023 22:03:51 -0600 Subject: [PATCH 1/5] Minor optimization to btb. --- pipelined/src/ifu/bpred/bpred.sv | 1 + pipelined/src/ifu/bpred/btb.sv | 7 ++++--- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 048aa112..9889607a 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -149,6 +149,7 @@ module bpred ( .PredValidF, .PredictionInstrClassWrongE, .IEUAdrE, + .InstrClassD, .InstrClassE); // the branch predictor needs a compact decoding of the instruction class. diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index 02c77fab..dc32d914 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -41,6 +41,7 @@ module btb #(parameter int Depth = 10 ) ( // update input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassD, // Instruction class to insert into btb input logic [3:0] InstrClassE // Instruction class to insert into btb ); @@ -71,7 +72,7 @@ module btb #(parameter int Depth = 10 ) ( assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - assign MatchF = PCNextFIndex == PCFIndex; + assign MatchF = PCNextFIndex == PCFIndex & PredValidF; assign MatchD = PCNextFIndex == PCDIndex; assign MatchE = PCNextFIndex == PCEIndex; assign MatchNextX = MatchF | MatchD | MatchE; @@ -79,7 +80,7 @@ module btb #(parameter int Depth = 10 ) ( flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {PredInstrClassD, PredPCD} : + MatchD ? {InstrClassD, PredPCD} : {InstrClassE, IEUAdrE} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); @@ -104,6 +105,6 @@ module btb #(parameter int Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD}); + flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); endmodule From c3e3afe39885adb8c0572943ebda09e8af7ffbda Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 00:24:54 -0600 Subject: [PATCH 2/5] Minor change to btb. --- pipelined/src/ifu/bpred/btb.sv | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ifu/bpred/btb.sv b/pipelined/src/ifu/bpred/btb.sv index dc32d914..7cf9ed99 100644 --- a/pipelined/src/ifu/bpred/btb.sv +++ b/pipelined/src/ifu/bpred/btb.sv @@ -50,12 +50,12 @@ module btb #(parameter int Depth = 10 ) ( logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex; logic [`XLEN-1:0] ResetPC; logic MatchF, MatchD, MatchE, MatchNextX, MatchXF; - logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; + logic [`XLEN+4:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; logic [`XLEN-1:0] PredPCD; logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; - logic TablePredValidF; + logic TablePredValidF, PredValidD; // hashing function for indexing the PC // We have Depth bits to index, but XLEN bits as the input. @@ -72,20 +72,20 @@ module btb #(parameter int Depth = 10 ) ( assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; - assign MatchF = PCNextFIndex == PCFIndex & PredValidF; + assign MatchF = PCNextFIndex == PCFIndex; assign MatchD = PCNextFIndex == PCDIndex; assign MatchE = PCNextFIndex == PCEIndex; assign MatchNextX = MatchF | MatchD | MatchE; flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {InstrClassD, PredPCD} : - {InstrClassE, IEUAdrE} ; + assign ForwardBTBPrediction = MatchF ? {PredValidF, BTBPredInstrClassF, PredPCF} : + MatchD ? {PredValidD, InstrClassD, PredPCD} : + {1'b1, InstrClassE, IEUAdrE} ; - flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); + flopenr #(`XLEN+5) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF; + assign {PredValidF, BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TablePredValidF, TableBTBPredictionF}; always_ff @ (posedge clk) begin if (reset) begin @@ -96,7 +96,7 @@ module btb #(parameter int Depth = 10 ) ( if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex]; end - assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; + //assign PredValidF = MatchXF ? 1'b1 : TablePredValidF; assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE; @@ -105,6 +105,6 @@ module btb #(parameter int Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); + flopenrc #(`XLEN+1) BTBD(clk, reset, FlushD, ~StallD, {PredValidF, PredPCF}, {PredValidD, PredPCD}); endmodule From 2a5b6408f26504f4d23cf8548e8f6f617ec3eca9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 10:27:58 -0600 Subject: [PATCH 3/5] Removed unused signal. --- pipelined/src/ifu/bpred/bpred.sv | 2 +- pipelined/src/ifu/bpred/speculativegshare.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index 9889607a..c72e9014 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -116,7 +116,7 @@ module bpred ( end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, + .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor diff --git a/pipelined/src/ifu/bpred/speculativegshare.sv b/pipelined/src/ifu/bpred/speculativegshare.sv index 23a49eac..1eb888a9 100644 --- a/pipelined/src/ifu/bpred/speculativegshare.sv +++ b/pipelined/src/ifu/bpred/speculativegshare.sv @@ -36,7 +36,7 @@ module speculativegshare #(parameter int k = 10 ) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, input logic [3:0] PredInstrClassF, InstrClassD, InstrClassE, input logic [3:0] WrongPredInstrClassD, input logic PCSrcE From 0035579553e182de25a51bdbf195ce58f5f5e105 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 1 Feb 2023 10:59:38 -0600 Subject: [PATCH 4/5] Minor branch predictor bug fix. --- pipelined/src/ifu/bpred/bpred.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/bpred/bpred.sv b/pipelined/src/ifu/bpred/bpred.sv index c72e9014..66414965 100644 --- a/pipelined/src/ifu/bpred/bpred.sv +++ b/pipelined/src/ifu/bpred/bpred.sv @@ -180,12 +180,14 @@ module bpred ( assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | PredInstrClassF[2] | - (PredInstrClassF[1]) ; + PredInstrClassF[1] | + PredInstrClassF[3]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) | PredInstrClassF[2] | - (PredInstrClassF[1] & PredValidF) ; + (PredInstrClassF[1] & PredValidF) | + (PredInstrClassF[3] & PredValidF); end // Part 3 RAS From 230888db8be70349eeb6c655e6fc84acc1235141 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 2 Feb 2023 08:52:06 -0600 Subject: [PATCH 5/5] Fixed bug #47 discovered by Lee Moore. ECALL and EBREAK do not commit their results. --- pipelined/src/hazard/hazard.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 9dd3c0e4..650e8367 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -68,7 +68,7 @@ module hazard ( assign FlushDCause = TrapM | RetM | CSRWriteFenceM | BPPredWrongE; assign FlushECause = TrapM | RetM | CSRWriteFenceM |(BPPredWrongE & ~(DivBusyE | FDivBusyE)); assign FlushMCause = TrapM | RetM | CSRWriteFenceM; - assign FlushWCause = TrapM & ~(BreakpointFaultM | EcallFaultM); + assign FlushWCause = TrapM; // Stall causes // Most data depenency stalls are identified in the decode stage