diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index b104de4e..96bea67c 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -137,9 +137,16 @@ module icachefsm
       STATE_READY: begin
         SelAdr = 2'b00;
         ICacheReadEn = 1'b1;
+/* -----\/----- EXCLUDED -----\/-----
         if (ITLBMissF & ~(ExceptionM | PendingInterruptM)) begin
           NextState = STATE_TLB_MISS;
-        end else if (hit & ~spill) begin
+        end else 
+ -----/\----- EXCLUDED -----/\----- */
+		if(ITLBMissF) begin
+		  NextState = STATE_READY;
+		  ICacheStallF = 1'b0;
+		end
+		else if (hit & ~spill) begin
           ICacheStallF = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  if(StallF) begin
@@ -325,6 +332,7 @@ module icachefsm
           NextState = STATE_READY;
 		end
       end
+/* -----\/----- EXCLUDED -----\/-----
       STATE_TLB_MISS: begin
         if (WalkerInstrPageFaultF) begin
           NextState = STATE_READY;
@@ -341,11 +349,15 @@ module icachefsm
 		SelAdr = 2'b01;
         NextState = STATE_READY;
       end
+ -----/\----- EXCLUDED -----/\----- */
       STATE_CPU_BUSY: begin
 		ICacheStallF = 1'b0;
+/* -----\/----- EXCLUDED -----\/-----
 		if (ITLBMissF) begin
           NextState = STATE_TLB_MISS;
-		end else if(StallF) begin
+		end else
+ -----/\----- EXCLUDED -----/\----- */
+        if(StallF) begin
 		  NextState = STATE_CPU_BUSY;
 		  SelAdr = 2'b01;
 		end
@@ -356,9 +368,12 @@ module icachefsm
       STATE_CPU_BUSY_SPILL: begin
 		ICacheStallF = 1'b0;
 		ICacheReadEn = 1'b1;
+/* -----\/----- EXCLUDED -----\/-----
 		if (ITLBMissF) begin
           NextState = STATE_TLB_MISS;
-		end else if(StallF) begin
+		end else 
+ -----/\----- EXCLUDED -----/\----- */
+		if(StallF) begin
 		  NextState = STATE_CPU_BUSY_SPILL;
 		  SelAdr = 2'b10;
 		end
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 3f25a689..cb2abd4d 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -144,16 +144,18 @@ module lsu
 	    .ITLBWriteF(ITLBWriteF),
 	    .DTLBWriteM(DTLBWriteM),
 	    .HPTWReadPTE(ReadDataM),
-	    .HPTWStall(HPTWStall),
-            .TranslationPAdr,			  
+	    .DCacheStall(DCacheStall),
+        .TranslationPAdr,			  
 	    .HPTWRead(HPTWRead),
 	    .SelPTW(SelPTW),
+		.HPTWStall,
 	    .AnyCPUReqM,
 	    .MemAfterIWalkDone,
 	    .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
 	    .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
 	    .WalkerStorePageFaultM(WalkerStorePageFaultM));
 
+  assign LSUStall = DCacheStall | HPTWStall;
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
@@ -163,7 +165,6 @@ module lsu
 		 .SelPTW(SelPTW),
 		 .HPTWRead(HPTWRead),
 		 .TranslationPAdrE(TranslationPAdr),
-		 .HPTWStall(HPTWStall),		 
 		 // CPU connection
 		 .MemRWM(MemRWM),
 		 .Funct3M(Funct3M),
@@ -174,7 +175,6 @@ module lsu
 		 .PendingInterruptM(PendingInterruptM),		
 		 .StallW(StallW),
 		 .DataMisalignedM(DataMisalignedM),
-		 .LSUStall(LSUStall),
 		 // DCACHE
 		 .DisableTranslation(DisableTranslation),
 		 .MemRWMtoLRSC(MemRWMtoLRSC),
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index c0647c2b..05cdf0ad 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -33,7 +33,6 @@ module lsuArb
    input logic 		       SelPTW,
    input logic 		       HPTWRead,
    input logic [`PA_BITS-1:0]  TranslationPAdrE,
-   output logic 	       HPTWStall, 
 
    // from CPU
    input logic [1:0] 	       MemRWM,
@@ -46,7 +45,7 @@ module lsuArb
    // to CPU
    output logic 	       DataMisalignedM,
    output logic 	       CommittedM,
-   output logic 	       LSUStall, 
+   //output logic 	       LSUStall, 
   
    // to D Cache
    output logic 	       DisableTranslation, 
@@ -98,10 +97,9 @@ module lsuArb
   // not clear at all.  I think it should be LSUStall from the LSU,
   // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
   //assign HPTWStall = SelPTW ? DCacheStall : 1'b1;  
-  assign HPTWStall = DCacheStall;  
 
   assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
 
-  assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
+  //assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
   
 endmodule
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index 95c8989d..78ee46f4 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -38,13 +38,14 @@ module hptw
    (* mark_debug = "true" *) input logic 		       ITLBMissF, DTLBMissM, // TLB Miss
    input logic [1:0] 	       MemRWM, // 10 = read, 01 = write
    input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU
-   input logic 		       HPTWStall, // stall from LSU
+   input logic 		       DCacheStall, // stall from LSU
    input logic 		       MemAfterIWalkDone,
    input logic 		       AnyCPUReqM,
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0] 	       PageType, // page type to TLBs
    (* mark_debug = "true" *) output logic 	       ITLBWriteF, DTLBWriteM, // write TLB with new entry
    output logic 	       SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU
+   output logic            HPTWStall,
    output logic [`PA_BITS-1:0] TranslationPAdr,
    output logic 	       HPTWRead, // HPTW requesting to read memory
    output logic 	       WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
@@ -54,7 +55,7 @@ module hptw
 				     L1_ADR, L1_RD, 
 				     L2_ADR, L2_RD, 
 				     L3_ADR, L3_RD, 
-				     LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
+				     LEAF, LEAF_DELAY, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
 
   generate
     if (`MEM_VIRTMEM) begin
@@ -86,7 +87,7 @@ module hptw
 
 	  // State flops
  	  flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
-	  assign PRegEn = HPTWRead & ~HPTWStall;
+	  assign PRegEn = HPTWRead & ~DCacheStall;
   	  flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
 	
       // Assign PTE descriptors common across all XLEN values
@@ -100,7 +101,8 @@ module hptw
 	  // Enable and select signals based on states
       assign StartWalk = (WalkerState == IDLE) & TLBMiss;
 	  assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
-	  assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT) & (WalkerState != LEAF);
+	  assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT) & (WalkerState != LEAF) & (WalkerState != LEAF_DELAY);
+	  assign HPTWStall = (WalkerState != IDLE) & (WalkerState != FAULT);
 	  assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
 	  assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
 
@@ -168,7 +170,7 @@ module hptw
 	    IDLE: if (TLBMiss)	 		NextWalkerState = InitialWalkerState;
 		      else 					NextWalkerState = IDLE;
 	    L3_ADR: 			NextWalkerState = L3_RD; // first access in SV48
-	    L3_RD: if (HPTWStall) NextWalkerState = L3_RD;
+	    L3_RD: if (DCacheStall) NextWalkerState = L3_RD;
 	                else 			NextWalkerState = L2_ADR;
 //	    LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
 //		  		else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
@@ -177,7 +179,7 @@ module hptw
 				else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
 		  		else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
 		 		else 				NextWalkerState = FAULT;			
-	    L2_RD: if (HPTWStall) NextWalkerState = L2_RD;
+	    L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
 	      			else 			NextWalkerState = L1_ADR;
 //	    LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
 //				else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
@@ -186,7 +188,7 @@ module hptw
 				else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
 		  		else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
 		 		else 				NextWalkerState = FAULT;	
-	    L1_RD: if (HPTWStall) NextWalkerState = L1_RD;
+	    L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
 	      			else 			NextWalkerState = L0_ADR;
 //	    LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
 //	      		else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
@@ -194,11 +196,13 @@ module hptw
 	    L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
 		  		else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
 		 		else 				NextWalkerState = FAULT;
-	    L0_RD: if (HPTWStall) NextWalkerState = L0_RD;
+	    L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
 	      			else 			NextWalkerState = LEAF;
 //	    LEVEL0: if (ValidLeafPTE) 	NextWalkerState = LEAF;
 //				else 				NextWalkerState = FAULT;
-	    LEAF: 						NextWalkerState = IDLE;
+	    LEAF: 	if (DTLBWalk)		NextWalkerState = IDLE; // updates TLB
+		        else                NextWalkerState = LEAF_DELAY;
+	    LEAF_DELAY: 				NextWalkerState = IDLE;		 // give time to allow address translation
 	    FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
  	                        else NextWalkerState = IDLE;
 	    default: begin