diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 0e7487eb..b6e8d0b4 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -106,7 +106,7 @@ module alu #(parameter WIDTH=32) ( assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; // Select appropriate ALU Result - if (`ZBS_SUPPORTED) begin + if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) begin always_comb if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect @@ -150,7 +150,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBBResult = 0; // Final Result B instruction select mux - if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder + if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder always_comb case (BSelect) //ZBA_ZBB_ZBC_ZBS diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d6e0c191..ff5bafa6 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -239,7 +239,7 @@ module controller( assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand assign ALUControlD = {W64D, SubArithD, ALUOpD}; - if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags + if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 463ab0c4..9126f09c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -105,6 +105,10 @@ logic [3:0] dummy; "coremark": tests = coremark; "fpga": tests = fpga; "ahb" : tests = ahb; + "arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba; + "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; + "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; + "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; "arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b; endcase end else begin // RV32 @@ -130,7 +134,10 @@ logic [3:0] dummy; "wally32periph": tests = wally32periph; "embench": tests = embench; "coremark": tests = coremark; - "arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba; + "arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba; + "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; + "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; + "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; endcase end diff --git a/testbench/tests.vh b/testbench/tests.vh index f894d58f..631775ae 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -836,17 +836,17 @@ string imperas32f[] = '{ }; - string wally64a[] = '{ + string wally64a[] = '{ `WALLYTEST, "rv64i_m/privilege/src/WALLY-amo-01.S", "rv64i_m/privilege/src/WALLY-lrsc-01.S" }; - string wally32a[] = '{ + string wally32a[] = '{ `WALLYTEST, "rv32i_m/privilege/src/WALLY-amo-01.S", "rv32i_m/privilege/src/WALLY-lrsc-01.S" - }; + }; string arch64priv[] = '{ `RISCVARCHTEST, @@ -881,14 +881,128 @@ string imperas32f[] = '{ "rv32i_m/Zifencei/src/Fencei.S" }; - string arch32ba[] = '{ + string arch32zba[] = '{ `RISCVARCHTEST, - // *** unclear why add.uw isn't in the list "rv32i_m/B/src/sh1add-01.S", - "rv32i_m/B/src/sh1add-02.S", - "rv32i_m/B/src/sh1add-013.S" + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S" }; + string arch32zbb[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_32-01.S", + "rv32i_m/B/src/rev8_32-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h_32-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/rol-01.S" + }; + + string arch32zbc[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S" + }; + + string arch32zbs[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S" + }; + + string arch32b[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S", + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S", + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_32-01.S", + "rv32i_m/B/src/rev8_32-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h_32-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/rol-01.S", + "rv32i_m/B/src/sh1add-01.S", + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S", + "rv32i_m/I/src/add-01.S", + "rv32i_m/I/src/addi-01.S", + "rv32i_m/I/src/and-01.S", + "rv32i_m/I/src/andi-01.S", + "rv32i_m/I/src/auipc-01.S", + "rv32i_m/I/src/beq-01.S", + "rv32i_m/I/src/bge-01.S", + "rv32i_m/I/src/bgeu-01.S", + "rv32i_m/I/src/blt-01.S", + "rv32i_m/I/src/bltu-01.S", + "rv32i_m/I/src/bne-01.S", + "rv32i_m/I/src/fence-01.S", + "rv32i_m/I/src/jal-01.S", + "rv32i_m/I/src/jalr-01.S", + "rv32i_m/I/src/lb-align-01.S", + "rv32i_m/I/src/lbu-align-01.S", + "rv32i_m/I/src/lh-align-01.S", + "rv32i_m/I/src/lhu-align-01.S", + "rv32i_m/I/src/lui-01.S", + "rv32i_m/I/src/lw-align-01.S", + "rv32i_m/I/src/or-01.S", + "rv32i_m/I/src/ori-01.S", + "rv32i_m/I/src/sb-align-01.S", + "rv32i_m/I/src/sh-align-01.S", + "rv32i_m/I/src/sll-01.S", + "rv32i_m/I/src/slli-01.S", + "rv32i_m/I/src/slt-01.S", + "rv32i_m/I/src/slti-01.S", + "rv32i_m/I/src/sltiu-01.S", + "rv32i_m/I/src/sltu-01.S", + "rv32i_m/I/src/sra-01.S", + "rv32i_m/I/src/srai-01.S", + "rv32i_m/I/src/srl-01.S", + "rv32i_m/I/src/srli-01.S", + "rv32i_m/I/src/sub-01.S", + "rv32i_m/I/src/sw-align-01.S", + "rv32i_m/I/src/xor-01.S", + "rv32i_m/I/src/xori-01.S" +}; + string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", @@ -1422,101 +1536,59 @@ string arch64b[] = '{ "rv64i_m/B/src/binvi-01.S", "rv64i_m/B/src/bset-01.S", "rv64i_m/B/src/bseti-01.S" - /*"rv64i_m/B/src/add.uw-01.S", - "rv64i_m/B/src/bclr-01.S", - "rv64i_m/B/src/bclri-01.S", - "rv64i_m/B/src/bext-01.S", - "rv64i_m/B/src/bexti-01.S", - "rv64i_m/B/src/binv-01.S", - "rv64i_m/B/src/binvi-01.S", - "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S", - "rv64i_m/B/src/clmul-01.S", - - - - "rv64i_m/B/src/rol-01.S", - - - - - */ }; -string arch32b[] = '{ + string arch64zba[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add.uw-01.S" + }; + + + +string arch64zbb[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/rev8-01.S", + "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rol-01.S" +}; + +string arch64zbc[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S" +}; + +string arch64zbs[] = '{ `RISCVARCHTEST, - "rv32i_m/B/src/clmul-01.S", - "rv32i_m/B/src/clmulh-01.S", - "rv32i_m/B/src/clmulr-01.S", - "rv32i_m/B/src/bclr-01.S", - "rv32i_m/B/src/bclri-01.S", - "rv32i_m/B/src/bext-01.S", - "rv32i_m/B/src/bexti-01.S", - "rv32i_m/B/src/binv-01.S", - "rv32i_m/B/src/binvi-01.S", - "rv32i_m/B/src/bset-01.S", - "rv32i_m/B/src/bseti-01.S", - "rv32i_m/B/src/max-01.S", - "rv32i_m/B/src/maxu-01.S", - "rv32i_m/B/src/min-01.S", - "rv32i_m/B/src/minu-01.S", - "rv32i_m/B/src/orcb_32-01.S", - "rv32i_m/B/src/rev8_32-01.S", - "rv32i_m/B/src/andn-01.S", - "rv32i_m/B/src/orn-01.S", - "rv32i_m/B/src/xnor-01.S", - "rv32i_m/B/src/zext.h_32-01.S", - "rv32i_m/B/src/sext.b-01.S", - "rv32i_m/B/src/sext.h-01.S", - "rv32i_m/B/src/clz-01.S", - "rv32i_m/B/src/cpop-01.S", - "rv32i_m/B/src/ctz-01.S", - "rv32i_m/B/src/ror-01.S", - "rv32i_m/B/src/rori-01.S", - "rv32i_m/B/src/rol-01.S", - "rv32i_m/B/src/sh1add-01.S", - "rv32i_m/B/src/sh2add-01.S", - "rv32i_m/B/src/sh3add-01.S", - "rv32i_m/I/src/add-01.S", - "rv32i_m/I/src/addi-01.S", - "rv32i_m/I/src/and-01.S", - "rv32i_m/I/src/andi-01.S", - "rv32i_m/I/src/auipc-01.S", - "rv32i_m/I/src/beq-01.S", - "rv32i_m/I/src/bge-01.S", - "rv32i_m/I/src/bgeu-01.S", - "rv32i_m/I/src/blt-01.S", - "rv32i_m/I/src/bltu-01.S", - "rv32i_m/I/src/bne-01.S", - "rv32i_m/I/src/fence-01.S", - "rv32i_m/I/src/jal-01.S", - "rv32i_m/I/src/jalr-01.S", - "rv32i_m/I/src/lb-align-01.S", - "rv32i_m/I/src/lbu-align-01.S", - "rv32i_m/I/src/lh-align-01.S", - "rv32i_m/I/src/lhu-align-01.S", - "rv32i_m/I/src/lui-01.S", - "rv32i_m/I/src/lw-align-01.S", - "rv32i_m/I/src/or-01.S", - "rv32i_m/I/src/ori-01.S", - "rv32i_m/I/src/sb-align-01.S", - "rv32i_m/I/src/sh-align-01.S", - "rv32i_m/I/src/sll-01.S", - "rv32i_m/I/src/slli-01.S", - "rv32i_m/I/src/slt-01.S", - "rv32i_m/I/src/slti-01.S", - "rv32i_m/I/src/sltiu-01.S", - "rv32i_m/I/src/sltu-01.S", - "rv32i_m/I/src/sra-01.S", - "rv32i_m/I/src/srai-01.S", - "rv32i_m/I/src/srl-01.S", - "rv32i_m/I/src/srli-01.S", - "rv32i_m/I/src/sub-01.S", - "rv32i_m/I/src/sw-align-01.S", - "rv32i_m/I/src/xor-01.S", - "rv32i_m/I/src/xori-01.S" - - /*"rv64i_m/B/src/add.uw-01.S", "rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclri-01.S", "rv64i_m/B/src/bext-01.S", @@ -1524,18 +1596,11 @@ string arch32b[] = '{ "rv64i_m/B/src/binv-01.S", "rv64i_m/B/src/binvi-01.S", "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S", - "rv64i_m/B/src/clmul-01.S", - - - - "rv64i_m/B/src/rol-01.S", - - - - - */ + "rv64i_m/B/src/bseti-01.S" }; + + + string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S",