From 80f026a73492e43247c893dc54bdc63b992da760 Mon Sep 17 00:00:00 2001
From: Katherine Parry <kparry4@gmail.com>
Date: Tue, 7 Dec 2021 14:15:43 -0800
Subject: [PATCH 01/95] FMA uses one LOA

---
 addins/riscv-arch-test                        |   2 +-
 wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv |  12 +-
 wally-pipelined/src/fpu/fma.sv                | 214 ++++++++++++------
 3 files changed, 155 insertions(+), 73 deletions(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 84d04381..be67c99b 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
diff --git a/wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv b/wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
index de5e849d..7d984dff 100644
--- a/wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
+++ b/wally-pipelined/fpu-testfloat/FMA/tbgen/tb.sv
@@ -1,5 +1,10 @@
 
-`include "../../../config/rv64icfd/wally-config.vh"
+//`include "../../../config/old/rv64icfd/wally-config.vh"
+
+`define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
+`define NE   11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
+`define NF   52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
+`define XLEN 64
 module testbench3();
 
  logic [31:0] errors=0;
@@ -174,8 +179,9 @@ always @(posedge clk)
  // check results on falling edge of clk
   always @(negedge clk) begin
  
-  //  fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
 	if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~((XNaNE && (FMAResM[`FLEN-2:0] == {XExpE,1'b1,X[`NF-2:0]})) || (YNaNE && (FMAResM[`FLEN-2:0] == {YExpE,1'b1,Y[`NF-2:0]}))  || (ZNaNE && (FMAResM[`FLEN-2:0] == {ZExpE,1'b1,Z[`NF-2:0]})) || (FMAResM[`FLEN-2:0] == ans[`FLEN-2:0]))))) begin
+  //  fp = $fopen("/home/kparry/riscv-wally/wally-pipelined/src/fpu/FMA/tbgen/results.dat","w");
+	// if((FmtE==1'b1) & (FMAFlgM != flags[4:0] || (FMAResM != ans))) begin
         $display( "%h %h %h %h %h %h %h  Wrong ",X,Y, Z, FMAResM, ans, FMAFlgM, flags);
 		if(FMAResM == 64'h8000000000000000) $display( "FMAResM=-zero ");
 		if(XDenormE) $display( "xdenorm ");
@@ -193,7 +199,7 @@ always @(posedge clk)
 		if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ~ans[`NF-1]) $display( "ans=sigNaN ");
 		if(ans[`FLEN-2:`NF] == {`NE{1'b1}} && ans[`NF-1:0] != 0 && ans[`NF-1]) $display( "ans=qutNaN ");
         errors = errors + 1;
-
+	  //if (errors == 10)
 		$stop;
     end
     if((FmtE==1'b0)&(FMAFlgM != flags[4:0] || (!wnan && (FMAResM != ans)) || (wnan && ansnan && ~(((XNaNE && (FMAResM[30:0] == {X[30:23],1'b1,X[21:0]})) || (YNaNE && (FMAResM[30:0] == {Y[30:23],1'b1,Y[21:0]}))  || (ZNaNE && (FMAResM[30:0] == {Z[30:23],1'b1,Z[21:0]})) || (FMAResM[30:0] == ans[30:0]))) ))) begin
diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv
index db55ee5c..6ad3f986 100644
--- a/wally-pipelined/src/fpu/fma.sv
+++ b/wally-pipelined/src/fpu/fma.sv
@@ -23,8 +23,11 @@
 ///////////////////////////////////////////
 
 `include "wally-config.vh"
-//    `include "../../../config/rv64icfd/wally-config.vh"
 
+// `define FLEN 64//(`Q_SUPPORTED ? 128 : `D_SUPPORTED ? 64 : 32)
+// `define NE   11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
+// `define NF   52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
+// `define XLEN 64
 module fma(
     input logic                 clk,
     input logic                 reset,
@@ -113,7 +116,7 @@ module fma1(
     logic [3*`NF+5:0]   AlignedAddendE;     // Z aligned for addition in U(NF+5.2NF+1)
     logic [3*`NF+6:0]   AlignedAddendInv;   // aligned addend possibly inverted
     logic [2*`NF+1:0]   ProdManKilled;      // the product's mantissa possibly killed
-    logic [3*`NF+6:0]   NegProdManKilled;   // a negated ProdManKilled
+    logic [3*`NF+4:0]   NegProdManKilled;   // a negated ProdManKilled
     logic [8:0]         PNormCnt, NNormCnt; // the positive and nagitive LOA results
     logic [3*`NF+6:0]   PreSum, NegPreSum;  // positive and negitve versions of the sum
 
@@ -149,11 +152,11 @@ module fma1(
         
     add add(.AlignedAddendE, .ProdManE, .PSgnE, .ZSgnEffE, .KillProdE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .NegSumE, .PreSum, .NegPreSum, .InvZE, .XZeroE, .YZeroE);
     
-    loa loa(.AlignedAddendE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .PNormCnt, .NNormCnt);
+    loa loa(.A(AlignedAddendInv+{162'b0,InvZE}), .P(ProdManKilled), .NegSumE, .NormCntE);
 
     // Choose the positive sum and accompanying LZA result.
     assign SumE = NegSumE ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
-    assign NormCntE = NegSumE ? NNormCnt : PNormCnt;
+    // assign NormCntE = NegSumE ? NNormCnt : PNormCnt;
 
 
 endmodule
@@ -311,7 +314,7 @@ module add(
     input logic                 XZeroE, YZeroE, // is the input zero
     output logic [3*`NF+6:0] AlignedAddendInv,  // aligned addend possibly inverted
     output logic [2*`NF+1:0] ProdManKilled,     // the product's mantissa possibly killed
-    output logic [3*`NF+6:0] NegProdManKilled,  // a negated ProdManKilled
+    output logic [3*`NF+4:0] NegProdManKilled,  // a negated ProdManKilled
     output logic                NegSumE,        // was the sum negitive
     output logic                InvZE,          // do you invert Z
     output logic [3*`NF+6:0]   PreSum, NegPreSum// possibly negitive sum
@@ -327,99 +330,65 @@ module add(
     assign InvZE = ZSgnEffE ^ PSgnE;
 
     // Choose an inverted or non-inverted addend - the one has to be added now for the LZA
-    assign AlignedAddendInv = InvZE ? -{1'b0, AlignedAddendE} : {1'b0, AlignedAddendE};
+    assign AlignedAddendInv = InvZE ? {1'b1, ~AlignedAddendE} : {1'b0, AlignedAddendE};
     // Kill the product if the product is too small to effect the addition (determined in fma1.sv)
     assign ProdManKilled = ProdManE&{2*`NF+2{~KillProdE}};
     // Negate ProdMan for LZA and the negitive sum calculation
-    assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, -ProdManKilled, 2'b0};
+    assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, ~ProdManKilled&{2*`NF+2{~(XZeroE|YZeroE)}}};
 
 
+    // Is the sum negitive
+    assign NegSumE = (AlignedAddendE > {54'b0, ProdManKilled, 2'b0})&InvZE; //***use this to avoid addition and final muxing???
 
     // Do the addition
     //      - calculate a positive and negitive sum in parallel
-    assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0};
-    assign NegPreSum = AlignedAddendE + NegProdManKilled;
+    assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE};
+    assign NegPreSum = AlignedAddendE + {NegProdManKilled, 2'b0} + {{(3*`NF+3){1'b0}},~(XZeroE|YZeroE),2'b0};
      
-    // Is the sum negitive
-    assign NegSumE = PreSum[3*`NF+6];
 
 endmodule
 
 
-module loa(
-    input logic [3*`NF+5:0] AlignedAddendE,     // Z aligned for addition in U(NF+5.2NF+1)
-    input logic [3*`NF+6:0] AlignedAddendInv,   // aligned addend possibly inverted
-    input logic [2*`NF+1:0] ProdManKilled,      // the product's mantissa possibly killed
-    input logic [3*`NF+6:0] NegProdManKilled,   // a negated ProdManKilled
-    output logic [8:0]      PNormCnt, NNormCnt  // positive and negitive LOA result    
-);
-
-    // LZAs one for the positive result and one for the negitive
-    //      - the +1 from inverting causes problems for normalization
-    posloa posloa(AlignedAddendInv, ProdManKilled, PNormCnt);
-    negloa negloa({1'b0,AlignedAddendE}, NegProdManKilled, NNormCnt);
-
-endmodule
-
-
-module posloa(
+module loa( //https://ieeexplore.ieee.org/abstract/document/930098
     input logic  [3*`NF+6:0] A,     // addend
     input logic  [2*`NF+1:0] P,     // product
-    output logic [8:0]       PCnt   // normalization shift count for the positive result
+    input logic              NegSumE, // is the sum negitive
+    output logic [8:0]       NormCntE   // normalization shift count for the positive result
     ); 
     
 
-    // calculate the propagate (T) and kill (Z) bits
     logic [3*`NF+6:0] T;
+    logic [3*`NF+5:0] G;
     logic [3*`NF+5:0] Z;
     assign T[3*`NF+6:2*`NF+4] = A[3*`NF+6:2*`NF+4];
-    assign Z[3*`NF+5:2*`NF+4] = A[3*`NF+5:2*`NF+4];
+    assign G[3*`NF+5:2*`NF+4] = 0;
+    assign Z[3*`NF+5:2*`NF+4] = ~A[3*`NF+5:2*`NF+4];
     assign T[2*`NF+3:2] = A[2*`NF+3:2]^P;
-    assign Z[2*`NF+3:2] = A[2*`NF+3:2]|P;
+    assign G[2*`NF+3:2] = A[2*`NF+3:2]&P;
+    assign Z[2*`NF+3:2] = ~A[2*`NF+3:2]&~P;
     assign T[1:0] = A[1:0];
-    assign Z[1:0] = A[1:0];
+    assign G[1:0] = 0;
+    assign Z[1:0] = ~A[1:0];
     
 
     // Apply function to determine Leading pattern
     logic [3*`NF+6:0] f;
-    assign f = T^{Z[3*`NF+5:0], 1'b0};
+    assign f = NegSumE ? T^{~G[3*`NF+5:0],1'b1} : T^{~Z[3*`NF+5:0], 1'b1};
 
-    lzc lzc(.f, .Cnt(PCnt));
+    lzc lzc(.f, .NormCntE);
   
 endmodule
 
-module negloa(
-    input logic  [3*`NF+6:0]    A,      // addend
-    input logic  [3*`NF+6:0]    P,      // product
-    output logic [8:0]          NCnt    // normalization shift count for the negitive result
-    ); 
-    
-    // calculate the propagate (T) and kill (Z) bits
-    logic [3*`NF+6:0] T;
-    logic [3*`NF+5:0] Z;
-    assign T = A^P;
-    assign Z = ~(A[3*`NF+5:0]|P[3*`NF+5:0]);
-    
-
-    // Apply function to determine Leading pattern
-    logic [3*`NF+6:0] f;
-    assign f = T^{~Z, 1'b0};
-    
-    lzc lzc(.f, .Cnt(NCnt));
-  
-endmodule
-
-
 module lzc(
     input logic  [3*`NF+6:0]    f,
-    output logic [8:0]          Cnt    // normalization shift count for the negitive result
+    output logic [8:0]          NormCntE    // normalization shift
 );
     
     logic [8:0] i;
     always_comb begin
         i = 0;
         while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1;  // search for leading one
-        Cnt = i;
+        NormCntE = i;
     end
 endmodule
 
@@ -479,7 +448,7 @@ module fma2(
     // Normalization
     ///////////////////////////////////////////////////////////////////////////////
 
-    normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum,
+    normalize normalize(.SumM, .ZExpM, .ProdExpM, .NormCntM, .FmtM, .KillProdM, .AddendStickyM, .NormSum, .NegSumM,
             .SumZero, .NormSumSticky, .UfSticky, .SumExp, .ResultDenorm);
 
 
@@ -611,6 +580,80 @@ module resultselect(
 endmodule
 
 
+// module normalize(
+//     input logic  [3*`NF+5:0]    SumM,       // the positive sum
+//     input logic  [`NE-1:0]      ZExpM,      // exponent of Z
+//     input logic  [`NE+1:0]      ProdExpM,   // X exponent + Y exponent - bias
+//     input logic  [8:0]          NormCntM,   // normalization shift count
+//     input logic                 FmtM,       // precision 1 = double 0 = single
+//     input logic                 KillProdM,  // is the product set to zero
+//     input logic                 AddendStickyM,  // the sticky bit caclulated from the aligned addend
+//     input logic                 NegSumM,    // was the sum negitive
+//     output logic [`NF+2:0]      NormSum,        // normalized sum
+//     output logic                SumZero,        // is the sum zero
+//     output logic                NormSumSticky, UfSticky,    // sticky bits
+//     output logic [`NE+1:0]      SumExp,         // exponent of the normalized sum
+//     output logic                ResultDenorm    // is the result denormalized
+// );
+//     logic [`NE+1:0]     FracLen;            // length of the fraction
+//     logic [`NE+1:0]     SumExpTmp;          // exponent of the normalized sum not taking into account denormal or zero results
+//     logic [8:0]         DenormShift;        // right shift if the result is denormalized //***change this later
+//     logic [3*`NF+5:0]   CorrSumShifted;     // the shifted sum after LZA correction
+//     logic [3*`NF+7:0]   SumShifted;         // the shifted sum before LZA correction
+//     logic [`NE+1:0]     SumExpTmpTmp;       // the exponent of the normalized sum with the `FLEN bias
+//     logic               PreResultDenorm;    // is the result denormalized - calculated before LZA corection
+//     logic               PreResultDenorm2;    // is the result denormalized - calculated before LZA corection
+//     logic               LZAPlus1;           // add one to the sum's exponent due to LZA correction
+
+//     ///////////////////////////////////////////////////////////////////////////////
+//     // Normalization
+//     ///////////////////////////////////////////////////////////////////////////////
+
+//     // Determine if the sum is zero
+//     assign SumZero = ~(|SumM);
+
+//     // determine the length of the fraction based on precision
+//     assign FracLen = FmtM ? `NF+1 : 13'd24;
+
+//     // calculate the sum's exponent
+//     assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); // ****try moving this into previous stage
+//     assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; // ***move this ^ the subtraction by a constant isn't simplified
+    
+//     logic SumDLTEZ, SumDGEFL, SumSLTEZ, SumSGEFL;
+//     assign SumDLTEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
+//     assign SumDGEFL = ($signed(SumExpTmpTmp)>=$signed(-(13'd`NF+13'd1)));
+//     assign SumSLTEZ = $signed(SumExpTmpTmp) <= $signed(13'd1023-13'd127);
+//     assign SumSGEFL = ($signed(SumExpTmpTmp)>=$signed(-13'd24+13'd1023-13'd127)) | ~|SumExpTmpTmp;
+//     assign PreResultDenorm2 = (FmtM ? SumDLTEZ : SumSLTEZ) & (FmtM ? SumDGEFL : SumSGEFL) & ~SumZero; //***make sure math good
+//     // always_comb begin
+//     //     assert (PreResultDenorm == PreResultDenorm2) else $fatal ("PreResultDenorms not equal");
+//     // end
+
+
+
+//     // Determine if the result is denormal
+//     // assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
+
+//     // Determine the shift needed for denormal results
+//     //  - if not denorm add 1 to shift out the leading 1
+//     assign DenormShift = PreResultDenorm2 ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
+//     // Normalize the sum
+//     assign SumShifted = {2'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
+//     // LZA correction
+//     assign LZAPlus1 = SumShifted[3*`NF+7];
+//     assign CorrSumShifted =  LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
+//     assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3];
+//     // Calculate the sticky bit
+//     assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | (|CorrSumShifted[136:2*`NF+3]&~FmtM);
+//     assign UfSticky = AddendStickyM | NormSumSticky;
+
+//     // Determine sum's exponent
+//     assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}};
+//     // recalculate if the result is denormalized
+//     assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
+
+// endmodule
+
 module normalize(
     input logic  [3*`NF+5:0]    SumM,       // the positive sum
     input logic  [`NE-1:0]      ZExpM,      // exponent of Z
@@ -619,6 +662,7 @@ module normalize(
     input logic                 FmtM,       // precision 1 = double 0 = single
     input logic                 KillProdM,  // is the product set to zero
     input logic                 AddendStickyM,  // the sticky bit caclulated from the aligned addend
+    input logic                 NegSumM,    // was the sum negitive
     output logic [`NF+2:0]      NormSum,        // normalized sum
     output logic                SumZero,        // is the sum zero
     output logic                NormSumSticky, UfSticky,    // sticky bits
@@ -629,15 +673,29 @@ module normalize(
     logic [`NE+1:0]     SumExpTmp;          // exponent of the normalized sum not taking into account denormal or zero results
     logic [8:0]         DenormShift;        // right shift if the result is denormalized //***change this later
     logic [3*`NF+5:0]   CorrSumShifted;     // the shifted sum after LZA correction
-    logic [3*`NF+7:0]   SumShifted;         // the shifted sum before LZA correction
+    logic [3*`NF+8:0]   SumShifted;         // the shifted sum before LZA correction
     logic [`NE+1:0]     SumExpTmpTmp;       // the exponent of the normalized sum with the `FLEN bias
     logic               PreResultDenorm;    // is the result denormalized - calculated before LZA corection
-    logic               LZAPlus1;           // add one to the sum's exponent due to LZA correction
+    logic               PreResultDenorm2;   // is the result denormalized - calculated before LZA corection
+    logic               LZAPlus1, LZAPlus2; // add one or two to the sum's exponent due to LZA correction
 
     ///////////////////////////////////////////////////////////////////////////////
     // Normalization
     ///////////////////////////////////////////////////////////////////////////////
 
+
+    // logic [8:0] supposedNormCnt;
+    // logic [8:0] i;
+    // always_comb begin
+    //         i = 0;
+    //         while (~SumM[3*`NF+5-i] && $unsigned(i) <= $unsigned(3*`NF+5)) i = i+1;  // search for leading one
+    //         supposedNormCnt = i;    // compute shift count
+    // end
+
+    // always_comb begin
+    //     assert (NormCntM == supposedNormCnt | NormCntM == supposedNormCnt+1 | NormCntM == supposedNormCnt+2) else $fatal ("normcnt not expected");
+    // end
+
     // Determine if the sum is zero
     assign SumZero = ~(|SumM);
 
@@ -645,19 +703,36 @@ module normalize(
     assign FracLen = FmtM ? `NF+1 : 13'd24;
 
     // calculate the sum's exponent
-    assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4));
-    assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}};
+    assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); // ****try moving this into previous stage
+    assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; // ***move this ^ the subtraction by a constant isn't simplified
+    
+    logic SumDLTEZ, SumDGEFL, SumSLTEZ, SumSGEFL;
+    assign SumDLTEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
+    assign SumDGEFL = ($signed(SumExpTmpTmp)>=$signed(-(13'd`NF+13'd1)));
+    assign SumSLTEZ = $signed(SumExpTmpTmp) <= $signed(13'd1023-13'd127);
+    assign SumSGEFL = ($signed(SumExpTmpTmp)>=$signed(-13'd24+13'd1023-13'd127)) | ~|SumExpTmpTmp;
+    assign PreResultDenorm2 = (FmtM ? SumDLTEZ : SumSLTEZ) & (FmtM ? SumDGEFL : SumSGEFL) & ~SumZero; //***make sure math good
+    // always_comb begin
+    //     assert (PreResultDenorm == PreResultDenorm2) else $fatal ("PreResultDenorms not equal");
+    // end
+
+    // 010. when should be 001.
+    //      - shift left one
+    //      - add one from exp
+    //      - if kill prod dont add to exp
 
     // Determine if the result is denormal
-    assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
+    // assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
 
     // Determine the shift needed for denormal results
     //  - if not denorm add 1 to shift out the leading 1
-    assign DenormShift = PreResultDenorm ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
+    assign DenormShift = PreResultDenorm2 ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
     // Normalize the sum
-    assign SumShifted = {2'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
+    assign SumShifted = {3'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
     // LZA correction
     assign LZAPlus1 = SumShifted[3*`NF+7];
+    assign LZAPlus2 = SumShifted[3*`NF+8];
+	// the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
     assign CorrSumShifted =  LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
     assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3];
     // Calculate the sticky bit
@@ -665,9 +740,10 @@ module normalize(
     assign UfSticky = AddendStickyM | NormSumSticky;
 
     // Determine sum's exponent
-    assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}};
+    //                          if plus1                     If plus2                                      if said denorm but norm plus 1     if said denorm (-1 val) but norm plus 2
+    assign SumExp = (SumExpTmp+{12'b0, LZAPlus1&~KillProdM}+{11'b0, LZAPlus2&~KillProdM, 1'b0}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]&~KillProdM}+{11'b0, &SumExpTmp&SumShifted[3*`NF+6]&~KillProdM, 1'b0}) & {`NE+2{~(SumZero|ResultDenorm)}};
     // recalculate if the result is denormalized
-    assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
+    assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
 
 endmodule
 

From 021faaf8cd5cc6d0e98602e71a0822104a70ffd5 Mon Sep 17 00:00:00 2001
From: slmnemo <nlucio@Tera.Eng.HMC.Edu>
Date: Wed, 8 Dec 2021 00:15:30 -0800
Subject: [PATCH 02/95] Removed .* from mmu instance inside lsu.sv.

---
 wally-pipelined/src/lsu/lsu.sv | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index a6250203..75ae4ccd 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -187,7 +187,9 @@ module lsu
 		 .DCacheStall(DCacheStall));
   
   mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
-  dmmu(.PAdr(MemPAdrMtoDCache),
+  dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+       .PrivilegeModeW, .DisableTranslation(DisableTranslation),
+       .PAdr(MemPAdrMtoDCache),
        .VAdr(MemAdrM),
        .Size(Funct3MtoDCache[1:0]),
        .PTE(PTE),
@@ -196,18 +198,16 @@ module lsu
        .TLBFlush(DTLBFlushM),
        .PhysicalAddress(MemPAdrM),
        .TLBMiss(DTLBMissM),
-       .TLBPageFault(DTLBPageFaultM),
-       .ExecuteAccessF(1'b0),
-       //.AtomicAccessM(AtomicMaskedM[1]),
-       .AtomicAccessM(1'b0),
-       .WriteAccessM(MemRWMtoLRSC[0]),
-       .ReadAccessM(MemRWMtoLRSC[1]),
-       .DisableTranslation(DisableTranslation),
-       .InstrAccessFaultF(),
        .Cacheable(CacheableM),
        .Idempotent(),
        .AtomicAllowed(),
-       .*); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
+       .TLBPageFault(DTLBPageFaultM),
+       .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
+       .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), 
+       .WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]),
+       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
+       //.AtomicAccessM(AtomicMaskedM[1]),
+       ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
 
 
   assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;

From 15bdf5680ed3d1d05c28a58c43d813d02b7e9a05 Mon Sep 17 00:00:00 2001
From: Noah Limpert <nlimpert@g.hmc.edu>
Date: Wed, 8 Dec 2021 00:24:27 -0800
Subject: [PATCH 03/95] removed .* instantiation from ieu.sv and datapth.sv in
 ieu folder

---
 wally-pipelined/src/ieu/datapath.sv |  2 +-
 wally-pipelined/src/ieu/ieu.sv      | 66 +++++++++++++++++++++++++++--
 2 files changed, 64 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 838d83a7..0679f8c3 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -96,7 +96,7 @@ module datapath (
   //Mux for writting floating point 
   
   regfile regf(clk, reset, {RegWriteW | FWriteIntW}, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
-  extend ext(.InstrD(InstrD[31:7]), .*);
+  extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
  
   // Execute stage pipeline register and logic
   flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E);
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index e9c6d117..06849522 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -90,9 +90,69 @@ module ieu (
   logic             MemReadE, CSRReadE;
   logic             JumpE;
            
-  controller c(.*);
-  datapath   dp(.*);             
-  forward    fw(.*);
+  controller c(
+    .clk, .reset,
+    // Decode stage control signals
+    .StallD, .FlushD, .InstrD, .ImmSrcD,
+    .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
+    // Execute stage control signals
+    .StallE, .FlushE, .FlagsE, 
+    .PCSrcE,        // for datapath and Hazard Unit
+    .ALUControlE, .ALUSrcAE, .ALUSrcBE,
+    .TargetSrcE,
+    .MemReadE, .CSRReadE, // for Hazard Unit
+    .Funct3E, .MulDivE, .W64E,
+    .JumpE,	
+    // Memory stage control signals
+    .StallM, .FlushM, .MemRWM,
+    .CSRReadM, .CSRWriteM, .PrivilegedM,
+    .SCE, .AtomicE, .AtomicM, .Funct3M,
+    .RegWriteM,     // for Hazard Unit
+    .InvalidateICacheM, .FlushDCacheM, .InstrValidM, 
+    // Writeback stage control signals
+    .StallW, .FlushW,
+    .RegWriteW,     // for datapath and Hazard Unit
+    .ResultSrcW,
+    // Stall during CSRs
+    .CSRWritePendingDEM,
+    .StoreStallD
+  );
+
+  datapath   dp(
+    .clk, .reset,
+    // Decode stage signals
+    .ImmSrcD, .InstrD,
+    // Execute stage signals
+    .StallE, .FlushE, .ForwardAE, .ForwardBE,
+    .ALUControlE, .ALUSrcAE, .ALUSrcBE,
+    .TargetSrcE, .JumpE, .IllegalFPUInstrE,
+    .FWriteDataE, .PCE, .PCLinkE, .FlagsE,
+    .PCTargetE,
+    .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
+    .SrcAE, .SrcBE,
+    // Memory stage signals
+    .StallM, .FlushM, .FWriteIntM, .FIntResM, 
+    .SrcAM, .WriteDataM, .MemAdrM, .MemAdrE,
+    // Writeback stage signals
+    .StallW, .FlushW, .FWriteIntW, .RegWriteW, 
+    .SquashSCW, .ResultSrcW, .ReadDataW,
+    // input  logic [`XLEN-1:0] PCLinkW,
+    .CSRReadValW, .ReadDataM, .MulDivResultW, 
+    // Hazard Unit signals 
+    .Rs1D, .Rs2D, .Rs1E, .Rs2E,
+    .RdE, .RdM, .RdW 
+  );             
+  
+  forward    fw(
+    .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
+    .MemReadE, .MulDivE, .CSRReadE,
+    .RegWriteM, .RegWriteW,
+    .FWriteIntE, .FWriteIntM, .FWriteIntW,
+    .SCE,
+    // Forwarding controls
+    .ForwardAE, .ForwardBE,
+    .FPUStallD, .LoadStallD, .MulDivStallD, .CSRRdStallD
+    );
 
 endmodule
 

From 7d614869a1118d6689c61507f46cd3de2b3709db Mon Sep 17 00:00:00 2001
From: slmnemo <nlucio@Tera.Eng.HMC.Edu>
Date: Wed, 8 Dec 2021 01:03:02 -0800
Subject: [PATCH 04/95] Removed .*s from wally-pipelined/src/uncore/uncore.sv

---
 wally-pipelined/src/uncore/uncore.sv | 63 ++++++++++++++++++++++++----
 1 file changed, 54 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index 8e3998e9..50941c32 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -85,40 +85,85 @@ module uncore (
   assign {HSELEXT, HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
 
   // subword accesses: converts HWDATAIN to HWDATA
-  subwordwrite sww(.*);
+  subwordwrite sww(
+    .HRDATA, 
+    .HADDRD, .HSIZED, 
+    .HWDATAIN, .HWDATA);
 
   generate
     // tightly integrated memory
     if (`TIM_SUPPORTED) begin : dtim
-      dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
+      dtim #(
+        .BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (
+        .HCLK, .HRESETn, 
+        .HSELTim, .HADDR,
+        .HWRITE, .HREADY,
+        .HTRANS, .HWDATA, .HREADTim,
+        .HRESPTim, .HREADYTim);
     end
 
     if (`BOOTTIM_SUPPORTED) begin : bootdtim
       dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE), .PRELOAD("blink-led.mem"))
-      bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
+      bootdtim(
+        .HCLK, .HRESETn, 
+        .HSELTim(HSELBootTim), .HADDR,
+        .HWRITE, .HREADY, .HTRANS,
+        .HWDATA,
+        .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim));
     end
 
     // memory-mapped I/O peripherals
     if (`CLINT_SUPPORTED == 1) begin : clint
-      clint clint(.HADDR(HADDR[15:0]), .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT), .*);
+      clint clint(
+        .HCLK, .HRESETn,
+        .HSELCLINT, .HADDR(HADDR[15:0]), .HWRITE,
+        .HWDATA, .HREADY, .HTRANS,
+        .HREADCLINT,
+        .HRESPCLINT, .HREADYCLINT,
+        .MTIME(MTIME_CLINT), .MTIMECMP(MTIMECMP_CLINT),
+        .TimerIntM, .SwIntM);
+
     end else begin : clint
       assign MTIME_CLINT = 0; assign MTIMECMP_CLINT = 0;
       assign TimerIntM = 0; assign SwIntM = 0;
     end
     if (`PLIC_SUPPORTED == 1) begin : plic
-      plic plic(.HADDR(HADDR[27:0]), .*);
+      plic plic(
+        .HCLK, .HRESETn, 
+        .HSELPLIC, .HADDR(HADDR[27:0]),
+        .HWRITE, .HREADY, .HTRANS, .HWDATA,
+        .UARTIntr, .GPIOIntr,
+        .HREADPLIC, .HRESPPLIC, .HREADYPLIC,
+        .ExtIntM);
     end else begin : plic
       assign ExtIntM = 0;
     end
     if (`GPIO_SUPPORTED == 1) begin : gpio
-      gpio gpio(.HADDR(HADDR[7:0]), .*); 
+      gpio gpio(
+        .HCLK, .HRESETn, .HSELGPIO,
+        .HADDR(HADDR[7:0]), 
+        .HWDATA,
+        .HWRITE, .HREADY, 
+        .HTRANS,
+        .HREADGPIO,
+        .HRESPGPIO, .HREADYGPIO,
+        .GPIOPinsIn,
+        .GPIOPinsOut, .GPIOPinsEn,
+        .GPIOIntr);
+
     end else begin : gpio
       assign GPIOPinsOut = 0; assign GPIOPinsEn = 0; assign GPIOIntr = 0;
     end
     if (`UART_SUPPORTED == 1) begin : uart
-      uart uart(.HADDR(HADDR[2:0]), .TXRDYb(), .RXRDYb(), .INTR(UARTIntr), .SIN(UARTSin), .SOUT(UARTSout),
-                .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), 
-                .RTSb(), .DTRb(), .OUT1b(), .OUT2b(), .*);
+      uart uart(
+        .HCLK, .HRESETn, 
+        .HSELUART,
+        .HADDR(HADDR[2:0]), 
+        .HWRITE, .HWDATA,
+        .HREADUART, .HRESPUART, .HREADYUART,
+        .SIN(UARTSin), .DSRb(1'b1), .DCDb(1'b1), .CTSb(1'b0), .RIb(1'b1), // from E1A driver from RS232 interface
+        .SOUT(UARTSout), .RTSb(), .DTRb(),                                // to E1A driver to RS232 interface
+        .OUT1b(), .OUT2b(), .INTR(UARTIntr), .TXRDYb(), .RXRDYb());       // to CPU
     end else begin : uart
       assign UARTSout = 0; assign UARTIntr = 0; 
     end

From 255cc26126db1843bce543f65f505459393d372d Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Wed, 8 Dec 2021 07:01:22 -0800
Subject: [PATCH 05/95] increase regression's expectations of buildroot to 246
 million

---
 wally-pipelined/regression/regression-wally.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index 828c2b7c..a0591d6a 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -34,7 +34,7 @@ configs = [
 ]
 def getBuildrootTC(short):
     INSTR_LIMIT = 100000 # multiple of 100000
-    MAX_EXPECTED = 182000000
+    MAX_EXPECTED = 246000000
     if short:
         BRcmd="vsim > {} -c <<!\ndo wally-buildroot-batch.do "+str(INSTR_LIMIT)+" 1 0\n!"
         BRgrepstr=str(INSTR_LIMIT)+" instructions"

From 9ddd065340e5e41112f12fb4dc79189085bfb4c7 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 8 Dec 2021 13:40:32 -0600
Subject: [PATCH 06/95] Updated coremark testbench with the extra ports from
 FPGA merge. Fixed coremark Makefile to create work directory.

---
 benchmarks/riscv-coremark/Makefile                   |  7 ++++---
 wally-pipelined/regression/wally-coremark.do         |  2 +-
 wally-pipelined/testbench/testbench-coremark_bare.sv | 11 ++++++++---
 3 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/benchmarks/riscv-coremark/Makefile b/benchmarks/riscv-coremark/Makefile
index a5b47239..1247d3d7 100644
--- a/benchmarks/riscv-coremark/Makefile
+++ b/benchmarks/riscv-coremark/Makefile
@@ -14,10 +14,11 @@ work/coremark.bare.riscv.objdump: work/coremark.bare.riscv
 
 work/coremark.bare.riscv: $(sources)
 #	make -C $(cmbase) PORT_DIR=/home/harris/riscv-wally/benchmarks/riscv-coremark/riscv64-baremetal compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64g"
-	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/courses/e190ax/riscvcompiler XCFLAGS="-march=rv64im"
-	mv $(cmbase)/coremark.bare.riscv work
+	make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=/opt/riscv XCFLAGS="-march=rv64imd"
+	mkdir -p work/
+	mv $(cmbase)/coremark.bare.riscv work/
 
 .PHONY: clean
 
 clean:
-	rm -f work/*
\ No newline at end of file
+	rm -f work/*
diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do
index 37b26f8b..b403016a 100644
--- a/wally-pipelined/regression/wally-coremark.do
+++ b/wally-pipelined/regression/wally-coremark.do
@@ -35,7 +35,7 @@ vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testb
 vopt +acc work.testbench -o workopt 
 vsim workopt
 
-mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/RAM
+mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/dtim/RAM
 
 view wave
 
diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index ebf6e29a..06ca47b0 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -54,8 +54,13 @@ module testbench();
   logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
   logic UARTSin, UARTSout;
   logic SDCCLK;
-  tri1 SDCCmd;
-  tri1 [3:0] SDCDat;
+  logic      SDCCmdIn;
+  logic      SDCCmdOut;
+  logic      SDCCmdOE;
+  logic [3:0] SDCDatIn;
+
+  logic             HREADY;
+  logic 	    HSELEXT;
 
   assign SDCmd = 1'bz;
   assign SDCDat = 4'bz;
@@ -95,7 +100,7 @@ module testbench();
       totalerrors = 0;
       // read test vectors into memory
       memfilename = tests[0];
-      $readmemh(memfilename, dut.uncore.dtim.RAM);
+      $readmemh(memfilename, dut.uncore.dtim.dtim.RAM);
       //for(j=268437955; j < 268566528; j = j+1)
         //dut.uncore.dtim.RAM[j] = 64'b0;
 //      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";

From d936342c9708c85f52b4f60d2b894c3efbe95647 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 8 Dec 2021 12:33:53 -0800
Subject: [PATCH 07/95] Refactoring ALU and datapath muxes

---
 addins/riscv-arch-test                        |   2 +-
 addins/riscv-isa-sim                          |   2 +-
 wally-pipelined/regression/sim-wally          |   2 +-
 wally-pipelined/src/fpu/fcvt.sv               |   4 +-
 wally-pipelined/src/fpu/fpu.sv                |   6 +-
 wally-pipelined/src/ieu/alu.sv                |  60 ++++++-----
 wally-pipelined/src/ieu/comparator.sv         |  52 +++++++++
 wally-pipelined/src/ieu/controller.sv         | 102 +++++++++---------
 wally-pipelined/src/ieu/datapath.sv           |  30 +++---
 wally-pipelined/src/ieu/ieu.sv                |   6 +-
 .../src/wally/wallypipelinedhart.sv           |   7 +-
 .../src/wally/wallypipelinedsoc.sv            |   9 +-
 12 files changed, 176 insertions(+), 106 deletions(-)
 create mode 100644 wally-pipelined/src/ieu/comparator.sv

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 84d04381..be67c99b 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
diff --git a/addins/riscv-isa-sim b/addins/riscv-isa-sim
index d22b2801..ddcfa6cc 160000
--- a/addins/riscv-isa-sim
+++ b/addins/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit d22b280198e74b871e04fc0ddb622fb825fdae49
+Subproject commit ddcfa6cc3d80818140a459e590296c3079c5a3ec
diff --git a/wally-pipelined/regression/sim-wally b/wally-pipelined/regression/sim-wally
index 1479d007..0c118256 100755
--- a/wally-pipelined/regression/sim-wally
+++ b/wally-pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv32g arch32f"
+vsim -do "do wally-pipelined.do rv32g arch32i"
 
diff --git a/wally-pipelined/src/fpu/fcvt.sv b/wally-pipelined/src/fpu/fcvt.sv
index 479da90c..087de263 100644
--- a/wally-pipelined/src/fpu/fcvt.sv
+++ b/wally-pipelined/src/fpu/fcvt.sv
@@ -10,7 +10,7 @@ module fcvt (
     input logic             XInfE,      // is X infinity
     input logic             XDenormE,   // is X denormalized
     input logic [10:0]      BiasE,      // bias - depends on precision (max exponent/2)
-    input logic [`XLEN-1:0] SrcAE,      // integer input
+    input logic [`XLEN-1:0] ForwardedSrcAE,      // integer input
     input logic [2:0]       FOpCtrlE,   // chooses which instruction is done (full list below)
     input logic [2:0]       FrmE,       // rounding mode 000 = rount to nearest, ties to even   001 = round twords zero  010 = round down  011 = round up  100 = round to nearest, ties to max magnitude
     input logic             FmtE,       // precision 1 = double 0 = single
@@ -73,7 +73,7 @@ module fcvt (
 ////////////////////////////////////////////////////////
 
     // position the input in the most significant bits
-    assign IntIn = FOpCtrlE[2] ? {SrcAE, {64-`XLEN{1'b0}}} : {SrcAE[31:0], 32'b0};
+    assign IntIn = FOpCtrlE[2] ? {ForwardedSrcAE, {64-`XLEN{1'b0}}} : {ForwardedSrcAE[31:0], 32'b0};
     // make the integer positive
     assign PosInt = IntIn[64-1]&~FOpCtrlE[1] ? -IntIn : IntIn;
     // determine the integer's sign
diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv
index 91af0509..d38dcd51 100755
--- a/wally-pipelined/src/fpu/fpu.sv
+++ b/wally-pipelined/src/fpu/fpu.sv
@@ -30,7 +30,7 @@ module fpu (
   input logic [2:0] 	   FRM_REGW, // Rounding mode from CSR
   input logic [31:0] 	   InstrD, // instruction from IFU
   input logic [`XLEN-1:0]  ReadDataW,// Read data from memory
-  input logic [`XLEN-1:0]  SrcAE, // Integer input being processed (from IEU)
+  input logic [`XLEN-1:0]  ForwardedSrcAE, // Integer input being processed (from IEU)
   input logic 		   StallE, StallM, StallW, // stall signals from HZU
   input logic 		   FlushE, FlushM, FlushW, // flush signals from HZU
   input logic [4:0] 	   RdM, RdW, // which FP register to write to (from IEU)
@@ -229,7 +229,7 @@ module fpu (
 			  .XSNaNE, .ClassResE);
 
      // Convert
-     fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .SrcAE, .FOpCtrlE, .FmtE, .FrmE,
+     fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
 		.CvtResE, .CvtFlgE);
      
      // data to be stored in memory - to IEU
@@ -238,7 +238,7 @@ module fpu (
      assign FWriteDataE = FSrcYE[`XLEN-1:0];     
      
      // Align SrcA to MSB when single precicion
-     mux2  #(64)  SrcAMux({{32{1'b1}}, SrcAE[31:0]}, {{64-`XLEN{1'b1}}, SrcAE}, FmtE, AlignedSrcAE);
+     mux2  #(64)  SrcAMux({{32{1'b1}}, ForwardedSrcAE[31:0]}, {{64-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
      
      // select a result that may be written to the FP register
      mux5  #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE);
diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index ac2c06dd..2ed6c75d 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -27,62 +27,66 @@
 
 module alu #(parameter WIDTH=32) (
   input  logic [WIDTH-1:0] a, b,
-  input  logic [4:0]       alucontrol,
+  input  logic [2:0]       ALUControl,
+  input  logic [2:0]       Funct3,
   output logic [WIDTH-1:0] result,
-  output logic [2:0]       flags);
+  output logic [WIDTH-1:0] sum);
 
-  logic [WIDTH-1:0] condinvb, presum, sum, shift, slt, sltu, bor;
-  logic        right, arith, w64;
-  logic        carry, zero, neg;
+  logic [WIDTH-1:0] condinvb, sumtrunc, shift, slt, sltu, bor;
+  logic        right; //, arith, w64;
+  logic        carry, neg;
   logic        lt, ltu;
   logic        overflow;
+  logic        W64, SubArith, ALUOp;
 
+  assign {W64, SubArith, ALUOp} = ALUControl;
   // addition
-  assign condinvb = alucontrol[3] ? ~b : b;
-  assign {carry, presum} = a + condinvb + {{(WIDTH-1){1'b0}},alucontrol[3]};
+  // *** make sure condinvb is only applied when it should be (sub, slt/sltu)
+  assign condinvb = SubArith ? ~b : b;
+  assign {carry, sum} = a + condinvb + {{(WIDTH-1){1'b0}}, SubArith};
   
   // support W-type RV64I ADDW/SUBW/ADDIW that sign-extend 32-bit result to 64 bits
   generate
     if (WIDTH==64)
-      assign sum = w64 ? {{32{presum[31]}}, presum[31:0]} : presum;
+      assign sumtrunc = W64 ? {{32{sum[31]}}, sum[31:0]} : sum;
     else
-      assign sum = presum;
+      assign sumtrunc = sum;
   endgenerate
   
   // shifts
-  assign arith = alucontrol[3]; // sra
-  assign w64 = alucontrol[4];
-  assign right = (alucontrol[2:0] == 3'b101); // sra or srl
-  shifter sh(a, b[5:0], right, arith, w64, shift);
+ // assign arith = alucontrol[3]; // sra
+ // assign w64 = alucontrol[4];
+  assign right = (Funct3[2:0] == 3'b101); // sra or srl
+  shifter sh(a, b[5:0], right, SubArith, W64, shift);
   
   // OR optionally passes zero when ALUControl[3] is set, supporting lui
-  assign bor = alucontrol[3] ? b : a|b;
+  // *** not needed anymore; simplify control
+  //assign bor = alucontrol[3] ? b : a|b;
   
   // condition code flags based on add/subtract output
-  assign zero = (sum == 0);
   assign neg  = sum[WIDTH-1];
   // overflow occurs when the numbers being added have the same sign 
   // and the result has the opposite sign
   assign overflow = (a[WIDTH-1] ~^ condinvb[WIDTH-1]) & (a[WIDTH-1] ^ sum[WIDTH-1]);
   assign lt = neg ^ overflow;
   assign ltu = ~carry;
-  assign flags = {zero, lt, ltu};
-
+ 
   // slt
   assign slt = {{(WIDTH-1){1'b0}}, lt};
   assign sltu = {{(WIDTH-1){1'b0}}, ltu};
  
   always_comb
-    case (alucontrol[2:0])
-      3'b000: result = sum;       // add or sub
-      3'b001: result = shift;     // sll
-      3'b010: result = slt;       // slt
-      3'b011: result = sltu;      // sltu
-      3'b100: result = a ^ b;     // xor
-      3'b101: result = shift;     // sra or srl
-      3'b110: result = bor;       // or / pass through input b for lui
-      3'b111: result = a & b;     // and
-    endcase
-
+    if (~ALUOp) result = sumtrunc;
+    else 
+      case (Funct3)
+        3'b000: result = sumtrunc;       // add or sub
+        3'b001: result = shift;     // sll
+        3'b010: result = slt;       // slt
+        3'b011: result = sltu;      // sltu
+        3'b100: result = a ^ b;     // xor
+        3'b101: result = shift;     // sra or srl
+        3'b110: result = a | b;     // or 
+        3'b111: result = a & b;     // and
+      endcase
 endmodule
 
diff --git a/wally-pipelined/src/ieu/comparator.sv b/wally-pipelined/src/ieu/comparator.sv
new file mode 100644
index 00000000..8178d338
--- /dev/null
+++ b/wally-pipelined/src/ieu/comparator.sv
@@ -0,0 +1,52 @@
+///////////////////////////////////////////
+// comparator.sv
+//
+// Written: David_Harris@hmc.edu 8 December 2021
+// Modified: 
+//
+// Purpose: Branch comparison
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+`include "wally-config.vh"
+
+module comparator #(parameter WIDTH=32) (
+  input  logic [WIDTH-1:0] a, b,
+  output logic [2:0]       flags);
+
+  logic [WIDTH-1:0] bbar, diff;
+  logic             carry, zero, neg, overflow, lt, ltu;
+
+  // NOTE: This can be replaced by some faster logic optimized
+  // to just compute flags and not the difference.
+
+  // subtraction
+  assign bbar = ~b;
+  assign {carry, diff} = a + bbar;
+
+  // condition code flags based on add/subtract output
+  assign zero = (diff == 0);
+  assign neg  = diff[WIDTH-1];
+  // overflow occurs when the numbers being subtracted have the opposite sign 
+  // and the result has the opposite sign fron the first
+  assign overflow = (a[WIDTH-1] ^ b[WIDTH-1]) & (a[WIDTH-1] ^ diff[WIDTH-1]);
+  assign lt = neg ^ overflow;
+  assign ltu = ~carry;
+  assign flags = {zero, lt, ltu};
+endmodule
+
diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 449066bf..97ffda48 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -38,9 +38,9 @@ module controller(
   input logic 	     StallE, FlushE,  
   input logic  [2:0] FlagsE, 
   output logic       PCSrcE,        // for datapath and Hazard Unit
-  output logic [4:0] ALUControlE, 
+  output logic [2:0] ALUControlE, 
   output logic 	     ALUSrcAE, ALUSrcBE,
-  output logic       TargetSrcE,
+  output logic       ALUResultSrcE,
   output logic       MemReadE, CSRReadE, // for Hazard Unit
   output logic [2:0] Funct3E,
   output logic       MulDivE, W64E,
@@ -70,7 +70,7 @@ module controller(
   logic [6:0] Funct7D;
   logic [4:0] Rs1D;
 
-  `define CTRLW 24
+  `define CTRLW 23
 
   // pipelined control signals
   logic 	    RegWriteD, RegWriteE;
@@ -78,10 +78,10 @@ module controller(
   logic [1:0] MemRWD, MemRWE;
   logic		    JumpD;
   logic		    BranchD, BranchE;
-  logic	[1:0] ALUOpD;
-  logic [4:0] ALUControlD;
+  logic	      ALUOpD;
+  logic [2:0] ALUControlD;
   logic 	    ALUSrcAD, ALUSrcBD;
-  logic       TargetSrcD, W64D, MulDivD;
+  logic       ALUResultSrcD, W64D, MulDivD;
   logic       CSRZeroSrcD;
   logic       CSRReadD;
   logic [1:0] AtomicD;
@@ -92,12 +92,13 @@ module controller(
   logic       PrivilegedD, PrivilegedE;
   logic       InvalidateICacheE, FlushDCacheE;
   logic [`CTRLW-1:0] ControlsD;
-  logic        aluc3D;
+  logic        SubArithD;
   logic        subD, sraD, sltD, sltuD;
   logic        BranchTakenE;
   logic        zeroE, ltE, ltuE;
   logic        unused;
-	
+	logic        BranchFlagE;
+
   // Extract fields
   assign OpD = InstrD[6:0];
   assign Funct3D = InstrD[14:12];
@@ -108,50 +109,50 @@ module controller(
   generate
     always_comb
       case(OpD)
-      // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_TargetSrc_W64_CSRRead_Privileged_Fence_MulDiv_Atomic_Illegal
-        7'b0000000:   ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // illegal instruction
-        7'b0000011:   ControlsD = `CTRLW'b1_000_01_10_001_0_00_0_0_0_0_0_0_0_00_0; // lw
-        7'b0000111:   ControlsD = `CTRLW'b0_000_01_10_001_0_00_0_0_0_0_0_0_0_00_0; // flw
-        7'b0001111:   ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_1_0_00_0; // fence
-        7'b0010011:   ControlsD = `CTRLW'b1_000_01_00_000_0_10_0_0_0_0_0_0_0_00_0; // I-type ALU
-        7'b0010111:   ControlsD = `CTRLW'b1_100_11_00_000_0_00_0_0_0_0_0_0_0_00_0; // auipc
+      // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MulDiv_Atomic_Illegal
+        7'b0000000:   ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // illegal instruction
+        7'b0000011:   ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw
+        7'b0000111:   ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // flw
+        7'b0001111:   ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
+        7'b0010011:   ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU
+        7'b0010111:   ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc
         7'b0011011: if (`XLEN == 64)
-                      ControlsD = `CTRLW'b1_000_01_00_000_0_10_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
+                      ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
                     else
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
-        7'b0100011:   ControlsD = `CTRLW'b0_001_01_01_000_0_00_0_0_0_0_0_0_0_00_0; // sw
-        7'b0100111:   ControlsD = `CTRLW'b0_001_01_01_000_0_00_0_0_0_0_0_0_0_00_0; // fsw
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
+        7'b0100011:   ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // sw
+        7'b0100111:   ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // fsw
         7'b0101111: if (`A_SUPPORTED) begin
                       if (InstrD[31:27] == 5'b00010)
-                        ControlsD = `CTRLW'b1_000_00_10_001_0_00_0_0_0_0_0_0_0_01_0; // lr
+                        ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr
                       else if (InstrD[31:27] == 5'b00011)
-                        ControlsD = `CTRLW'b1_101_01_01_100_0_00_0_0_0_0_0_0_0_01_0; // sc
+                        ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc
                       else 
-                        ControlsD = `CTRLW'b1_101_01_11_001_0_00_0_0_0_0_0_0_0_10_0;; // amo
+                        ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0;; // amo
                     end else
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
         7'b0110011: if (Funct7D == 7'b0000000 || Funct7D == 7'b0100000)
-                      ControlsD = `CTRLW'b1_000_00_00_000_0_10_0_0_0_0_0_0_0_00_0; // R-type 
+                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type 
                     else if (Funct7D == 7'b0000001 && `M_SUPPORTED)
-                      ControlsD = `CTRLW'b1_000_00_00_011_0_00_0_0_0_0_0_0_1_00_0; // Multiply/Divide
+                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/Divide
                     else
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
-        7'b0110111:   ControlsD = `CTRLW'b1_100_01_00_000_0_11_0_0_0_0_0_0_0_00_0; // lui
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
+        7'b0110111:   ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
         7'b0111011: if ((Funct7D == 7'b0000000 || Funct7D == 7'b0100000) && `XLEN == 64)
-                      ControlsD = `CTRLW'b1_000_00_00_000_0_10_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
+                      ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
                     else if (Funct7D == 7'b0000001 && `M_SUPPORTED && `XLEN == 64)
-                      ControlsD = `CTRLW'b1_000_00_00_011_0_00_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
+                      ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
                     else
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
         //7'b1010011:   ControlsD = `CTRLW'b0_000_00_00_101_0_00_0_0_0_0_0_0_0_00_1; // FP
-        7'b1100011:   ControlsD = `CTRLW'b0_010_00_00_000_1_01_0_0_0_0_0_0_0_00_0; // beq
-        7'b1100111:   ControlsD = `CTRLW'b1_000_00_00_000_0_00_1_1_0_0_0_0_0_00_0; // jalr
-        7'b1101111:   ControlsD = `CTRLW'b1_011_00_00_000_0_00_1_0_0_0_0_0_0_00_0; // jal
+        7'b1100011:   ControlsD = `CTRLW'b0_010_00_00_000_1_0_0_0_0_0_0_0_0_00_0; // beq
+        7'b1100111:   ControlsD = `CTRLW'b1_000_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
+        7'b1101111:   ControlsD = `CTRLW'b1_011_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
         7'b1110011: if (Funct3D == 3'b000)
-                      ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
+                      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
                     else
-                      ControlsD = `CTRLW'b1_000_00_00_010_0_00_0_0_0_1_0_0_0_00_0; // csrs
-        default:      ControlsD = `CTRLW'b0_000_00_00_000_0_00_0_0_0_0_0_0_0_00_1; // non-implemented instruction
+                      ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
+        default:      ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
       endcase
   endgenerate
 
@@ -159,7 +160,7 @@ module controller(
   // squash control signals if coming from an illegal compressed instruction
   assign IllegalBaseInstrFaultD = ControlsD[0];
   assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
-          ResultSrcD, BranchD, ALUOpD, JumpD, TargetSrcD, W64D, CSRReadD, 
+          ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, 
           PrivilegedD, FenceD, MulDivD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD;
           // *** move Privileged, CSRwrite??  Or move controller out of IEU into datapath and handle all instructions
 
@@ -172,15 +173,19 @@ module controller(
   assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);
   assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
 
-  assign aluc3D = subD | sraD | sltD | sltuD; // TRUE for R-type subtracts and sra, slt, sltu
+  assign SubArithD = subD | sraD | sltD | sltuD; // TRUE for R-type subtracts and sra, slt, sltu
+//  assign SubArithD = aluc3D; // ***cleanup
 
-  always_comb
+  // *** replace all of this
+  assign ALUControlD = {W64D, SubArithD, ALUOpD};
+/*  always_comb
     case(ALUOpD)
       2'b00:                ALUControlD = 5'b00000; // addition
-      2'b01:                ALUControlD = 5'b01000;  // subtraction
-      2'b11:                ALUControlD = 5'b01110;  // pass B through for lui
+      2'b01:                ALUControlD = 5'b00000;  // add for branch offset
+//      2'b01:                ALUControlD = 5'b01000;  // subtraction
+//      2'b11:                ALUControlD = 5'b01110;  // pass B through for lui ***no longer used
       default:              ALUControlD = {W64D, aluc3D, Funct3D}; // R-type instructions
-    endcase
+    endcase*/
 
   // Fences
   // Ordinary fence is presently a nop
@@ -201,14 +206,15 @@ module controller(
   flopenrc #(1)  controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
 
   // Execute stage pipeline control register and logic
-  flopenrc #(29) controlregE(clk, reset, FlushE, ~StallE,
-                           {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, TargetSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, InvalidateICacheD, FlushDCacheD, InstrValidD},
-                           {RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, TargetSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
+  flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE,
+                           {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, InvalidateICacheD, FlushDCacheD, InstrValidD},
+                           {RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
 
   // Branch Logic
   assign {zeroE, ltE, ltuE} = FlagsE;
-  
-  always_comb
+  mux4 #(1) branchflagmux(zeroE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
+  assign BranchTakenE = BranchFlagE ^ Funct3E[0];
+/*  always_comb
     case(Funct3E)
       3'b000:  BranchTakenE = zeroE;  // beq
       3'b001:  BranchTakenE = ~zeroE; // bne
@@ -217,7 +223,7 @@ module controller(
       3'b110:  BranchTakenE = ltuE;   // bltu
       3'b111:  BranchTakenE = ~ltuE;  // bgeu
       default: BranchTakenE = 1'b0; // undefined mode
-    endcase
+    endcase*/
     
   assign PCSrcE = JumpE | BranchE & BranchTakenE;
 
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 838d83a7..b85100a0 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -30,12 +30,13 @@ module datapath (
   // Decode stage signals
   input  logic [2:0]       ImmSrcD,
   input  logic [31:0]      InstrD,
+  input  logic [2:0]       Funct3E,
   // Execute stage signals
   input  logic             StallE, FlushE,
   input  logic [1:0]       ForwardAE, ForwardBE,
-  input  logic [4:0]       ALUControlE,
+  input  logic [2:0]       ALUControlE,
   input  logic             ALUSrcAE, ALUSrcBE,
-  input  logic             TargetSrcE, 
+  input  logic             ALUResultSrcE, 
   input  logic             JumpE,
   input  logic             IllegalFPUInstrE,
   input  logic [`XLEN-1:0] FWriteDataE,
@@ -44,7 +45,6 @@ module datapath (
   output logic [2:0]       FlagsE,
   output logic [`XLEN-1:0] PCTargetE,
   output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-  output logic [`XLEN-1:0] SrcAE, SrcBE,
   // Memory stage signals
   input  logic             StallM, FlushM,
   input  logic             FWriteIntM,
@@ -75,11 +75,12 @@ module datapath (
   logic [`XLEN-1:0] ExtImmE;
 
   // logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path.
+  logic [`XLEN-1:0] SrcAE, SrcBE;
   logic [`XLEN-1:0] SrcAE2, SrcBE2;
 
-  logic [`XLEN-1:0] ALUResultE;
+  logic [`XLEN-1:0] ALUResultE, AltResultE, ALUPreResultE;
   logic [`XLEN-1:0] WriteDataE;
-  logic [`XLEN-1:0] TargetBaseE;
+  logic [`XLEN-1:0] AddressE;
   // Memory stage signals
   logic [`XLEN-1:0] ALUResultM;
   logic [`XLEN-1:0] ResultM;
@@ -110,18 +111,23 @@ module datapath (
   mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
   mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
-  mux2  #(`XLEN)  srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);  
+//  mux2  #(`XLEN)  srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);  
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
-  mux2  #(`XLEN)  srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
-  alu   #(`XLEN)  alu(SrcAE2, SrcBE2, ALUControlE, ALUResultE, FlagsE);
-  mux2  #(`XLEN)  targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE);
-  assign  PCTargetE = ExtImmE + TargetBaseE;
+//  mux2  #(`XLEN)  srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
+  alu   #(`XLEN)  alu(SrcAE/*SrcAE2*/, SrcBE/*SrcBE2*/, ALUControlE, Funct3E, ALUPreResultE, AddressE /*, FlagsE */);
+  // redo ALUControlE to simplify - jus needs ALUAddE, Funct3E, W64E
+  comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
+//  mux2  #(`XLEN)  targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE); // *** PCE alsready should be selectable for SrcAE
+//  assign  PCTargetE = ExtImmE + TargetBaseE;
+  mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
+  mux2 #(`XLEN) aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE);
 
   // Memory stage pipeline register
   flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
   flopenrc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ~StallM, ALUResultE, ALUResultM);
-  assign MemAdrM = ALUResultM;
-  assign MemAdrE = ALUResultE;  
+  assign MemAdrE = AddressE;   // *** clean up this naming
+  assign PCTargetE = AddressE; // *** clean up this naming
+  flopenrc #(`XLEN) AddressNReg(clk, reset, FlushM, ~StallM, MemAdrE, MemAdrM);
   flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
   flopenrc #(5)    RdMEg(clk, reset, FlushM, ~StallM, RdE, RdM);	
   mux2  #(`XLEN)   resultmuxM(ALUResultM, FIntResM, FWriteIntM, ResultM);
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index e9c6d117..51b991b7 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -41,7 +41,7 @@ module ieu (
   output logic 		   MulDivE, W64E,
   output logic [2:0] 	   Funct3E,
   output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-  output logic [`XLEN-1:0] SrcAE, SrcBE,
+//  output logic [`XLEN-1:0] SrcAE, SrcBE,
   input logic 		   FWriteIntM,
 
   // Memory stage interface
@@ -76,10 +76,10 @@ module ieu (
 
   logic [2:0]  ImmSrcD;
   logic [2:0]  FlagsE;
-  logic [4:0]  ALUControlE;
+  logic [2:0]  ALUControlE;
   logic        ALUSrcAE, ALUSrcBE;
   logic [2:0]  ResultSrcW;
-  logic        TargetSrcE;
+  logic        ALUResultSrcE;
   logic        SCE;
   logic [4:0]  RdE;
 
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index ea56b6ec..4e8dbc47 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -60,7 +60,7 @@ module wallypipelinedhart (
   logic 		    CSRReadM, CSRWriteM, PrivilegedM;
   logic [1:0] 		    AtomicE;
   logic [1:0] 		    AtomicM;
-  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE, SrcAE, SrcBE;
+  logic [`XLEN-1:0] 	ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
   logic [`XLEN-1:0] 	    SrcAM;
   logic [2:0] 		    Funct3E;
   //  logic [31:0] InstrF;
@@ -211,7 +211,8 @@ module wallypipelinedhart (
      .PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE,
      .FWriteDataE, .PCTargetE, .MulDivE, .W64E,
      .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-     .SrcAE, .SrcBE, .FWriteIntM,
+     //.SrcAE, .SrcBE, 
+     .FWriteIntM,
 
      // Memory stage interface
      .SquashSCW, // from LSU
@@ -364,7 +365,7 @@ module wallypipelinedhart (
      .FRM_REGW, // Rounding mode from CSR
      .InstrD, // instruction from IFU
      .ReadDataW,// Read data from memory
-     .SrcAE, // Integer input being processed (from IEU)
+     .ForwardedSrcAE, // Integer input being processed (from IEU)
      .StallE, .StallM, .StallW, // stall signals from HZU
      .FlushE, .FlushM, .FlushW, // flush signals from HZU
      .RdM, .RdW, // which FP register to write to (from IEU)
diff --git a/wally-pipelined/src/wally/wallypipelinedsoc.sv b/wally-pipelined/src/wally/wallypipelinedsoc.sv
index 8f3a2234..56d785b1 100644
--- a/wally-pipelined/src/wally/wallypipelinedsoc.sv
+++ b/wally-pipelined/src/wally/wallypipelinedsoc.sv
@@ -32,11 +32,12 @@
 `include "wally-config.vh"
 
 module wallypipelinedsoc (
-  input logic 		   clk, reset_ext, 
+  input  logic 		   clk, reset_ext, 
+  output logic       reset,
   // AHB Lite Interface
   // inputs from external memory
-  input logic [`AHBW-1:0]  HRDATAEXT,
-  input logic 		   HREADYEXT, HRESPEXT,
+  input  logic [`AHBW-1:0]  HRDATAEXT,
+  input  logic 		   HREADYEXT, HRESPEXT,
   output logic 		   HSELEXT,
   // outputs to external memory, shared with uncore memory
   output logic 		   HCLK, HRESETn,
@@ -62,7 +63,7 @@ module wallypipelinedsoc (
 );
 
   // Uncore signals
-  logic 		   reset;
+//  logic 		   reset;
   logic [`AHBW-1:0] HRDATA;   // from AHB mux in uncore
   logic             HRESP;
   logic             TimerIntM, SwIntM; // from CLINT

From 5f0521d497f8f6f4a97a19ce74ce8f7d822a7efd Mon Sep 17 00:00:00 2001
From: Noah Limpert <nlimpert@g.hmc.edu>
Date: Wed, 8 Dec 2021 13:34:33 -0800
Subject: [PATCH 08/95] updated fcmp.sv instantiation to remove x*'s

---
 wally-pipelined/src/fpu/fcmp.sv | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/fpu/fcmp.sv b/wally-pipelined/src/fpu/fcmp.sv
index b47e6eab..a60cc8f6 100755
--- a/wally-pipelined/src/fpu/fcmp.sv
+++ b/wally-pipelined/src/fpu/fcmp.sv
@@ -76,7 +76,12 @@ module fcmp (
 
    // Determine final values based on output of magnitude comparison, 
    // sign bits, and special case testing. 
-   exception_cmp_2 exc2 (.invalid(Invalid), .fcc(FCC), .LT_mag(LT), .EQ_mag(EQ), .ANaN(XNaNE), .BNaN(YNaNE), .Azero(XZeroE), .Bzero(YZeroE), .FOpCtrlE(FOpCtrlE), .A(op1), .B(op2), .FSrcXE, .FSrcYE, .*);
+   exception_cmp_2 exc2 (
+      .invalid(Invalid), .fcc(FCC), .LT_mag(LT), .EQ_mag(EQ), 
+      .ANaN(XNaNE), .BNaN(YNaNE), .Azero(XZeroE), .Bzero(YZeroE), 
+      .FOpCtrlE, .A(op1), .B(op2), .FSrcXE, .FSrcYE, 
+      .FmtE, .CmpResE
+      );
 
 endmodule // fpcomp
 

From a1f8f7babec732ca92f42c58d39cf6037a16e877 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 8 Dec 2021 13:48:04 -0800
Subject: [PATCH 09/95] Refactored IEU/ALU logic

---
 wally-pipelined/src/ieu/controller.sv | 2 +-
 wally-pipelined/src/ieu/datapath.sv   | 7 +------
 wally-pipelined/src/ieu/ieu.sv        | 7 +++----
 3 files changed, 5 insertions(+), 11 deletions(-)

diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 97ffda48..90ab5af6 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -173,7 +173,7 @@ module controller(
   assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);
   assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
 
-  assign SubArithD = subD | sraD | sltD | sltuD; // TRUE for R-type subtracts and sra, slt, sltu
+  assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
 //  assign SubArithD = aluc3D; // ***cleanup
 
   // *** replace all of this
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 9070d2d1..b0645f81 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -111,14 +111,9 @@ module datapath (
   mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
   mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
-//  mux2  #(`XLEN)  srcamux2(SrcAE, PCLinkE, JumpE, SrcAE2);  
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
-//  mux2  #(`XLEN)  srcbmux2(SrcBE, {`XLEN{1'b0}}, JumpE, SrcBE2); // *** May be able to remove this mux.
-  alu   #(`XLEN)  alu(SrcAE/*SrcAE2*/, SrcBE/*SrcBE2*/, ALUControlE, Funct3E, ALUPreResultE, AddressE /*, FlagsE */);
-  // redo ALUControlE to simplify - jus needs ALUAddE, Funct3E, W64E
+  alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUPreResultE, AddressE);
   comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
-//  mux2  #(`XLEN)  targetsrcmux(PCE, SrcAE, TargetSrcE, TargetBaseE); // *** PCE alsready should be selectable for SrcAE
-//  assign  PCTargetE = ExtImmE + TargetBaseE;
   mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
   mux2 #(`XLEN) aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE);
 
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index 9d2c3ace..4619b337 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -99,7 +99,7 @@ module ieu (
     .StallE, .FlushE, .FlagsE, 
     .PCSrcE,        // for datapath and Hazard Unit
     .ALUControlE, .ALUSrcAE, .ALUSrcBE,
-    .TargetSrcE,
+    .ALUResultSrcE,
     .MemReadE, .CSRReadE, // for Hazard Unit
     .Funct3E, .MulDivE, .W64E,
     .JumpE,	
@@ -124,12 +124,11 @@ module ieu (
     .ImmSrcD, .InstrD,
     // Execute stage signals
     .StallE, .FlushE, .ForwardAE, .ForwardBE,
-    .ALUControlE, .ALUSrcAE, .ALUSrcBE,
-    .TargetSrcE, .JumpE, .IllegalFPUInstrE,
+    .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE,
+    .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
     .FWriteDataE, .PCE, .PCLinkE, .FlagsE,
     .PCTargetE,
     .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-    .SrcAE, .SrcBE,
     // Memory stage signals
     .StallM, .FlushM, .FWriteIntM, .FIntResM, 
     .SrcAM, .WriteDataM, .MemAdrM, .MemAdrE,

From 741a21d0df8b69225e84bd8781868834fb4fc412 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 8 Dec 2021 15:50:15 -0600
Subject: [PATCH 10/95] Fixed some issues with the SDC having a different
 counter.  When this is copied into synthesis the file names where the same
 and it gave a conflict. Remove preload from dtim.

---
 wally-pipelined/src/sdc/{counter.sv => SDCcounter.sv} | 0
 wally-pipelined/src/uncore/dtim.sv                    | 2 +-
 wally-pipelined/src/uncore/uncore.sv                  | 2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename wally-pipelined/src/sdc/{counter.sv => SDCcounter.sv} (100%)

diff --git a/wally-pipelined/src/sdc/counter.sv b/wally-pipelined/src/sdc/SDCcounter.sv
similarity index 100%
rename from wally-pipelined/src/sdc/counter.sv
rename to wally-pipelined/src/sdc/SDCcounter.sv
diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv
index 59beebb6..31d8fec5 100644
--- a/wally-pipelined/src/uncore/dtim.sv
+++ b/wally-pipelined/src/uncore/dtim.sv
@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
+module dtim #(parameter BASE=0, RANGE = 65535) (
   input  logic             HCLK, HRESETn, 
   input  logic             HSELTim,
   input  logic [31:0]      HADDR,
diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index 50941c32..97057b23 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -103,7 +103,7 @@ module uncore (
     end
 
     if (`BOOTTIM_SUPPORTED) begin : bootdtim
-      dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE), .PRELOAD("blink-led.mem"))
+      dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE))
       bootdtim(
         .HCLK, .HRESETn, 
         .HSELTim(HSELBootTim), .HADDR,

From f2f15c04952efb96fc4d347ac36a00b887964949 Mon Sep 17 00:00:00 2001
From: slmnemo <nlucio@Tera.Eng.HMC.Edu>
Date: Wed, 8 Dec 2021 14:02:53 -0800
Subject: [PATCH 11/95] Removed .* from /wally-pipelined/src/uncore/uart.sv

---
 wally-pipelined/src/uncore/uart.sv | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/uncore/uart.sv b/wally-pipelined/src/uncore/uart.sv
index 0341d30c..e4c7d295 100644
--- a/wally-pipelined/src/uncore/uart.sv
+++ b/wally-pipelined/src/uncore/uart.sv
@@ -84,7 +84,19 @@ module uart (
   
   logic BAUDOUTb;  // loop tx clock BAUDOUTb back to rx clock RCLK
   // *** make sure reads don't occur on UART unless fully selected because they could change state.  This applies to all peripherals
-  uartPC16550D u(.RCLK(BAUDOUTb), .*);
+  uartPC16550D u(  
+    // Processor Interface
+    .HCLK, .HRESETn,
+    .A, .Din, 
+    .Dout,
+    .MEMRb, .MEMWb, 
+    .INTR, .TXRDYb, .RXRDYb,
+    // Clocks
+    .BAUDOUTb, .RCLK(BAUDOUTb),
+    // E1A Driver
+    .SIN, .DSRb, .DCDb, .CTSb, .RIb,
+    .SOUT, .RTSb, .DTRb, .OUT1b, .OUT2b
+);
 
 endmodule
 

From 5feccaec683a81e53522274b7f4ef83243b2f08f Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Wed, 8 Dec 2021 14:11:43 -0800
Subject: [PATCH 12/95] fix release of ReadDataM

---
 wally-pipelined/testbench/testbench-linux.sv | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index a757e4f7..82e69720 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -444,12 +444,13 @@ module testbench();
       end \
       if(`"STAGE`"=="M") begin \
         // override on special conditions \
-        if (dut.hart.lsu.MemPAdrM == 'h10000005) begin \
+        if (dut.hart.lsu.MemPAdrM == 'h10000005) \
           //$display("%tns, %d instrs: Overwrite UART's LSR in memory stage.", $time, InstrCountW-1); \
           force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
-        end \
+        else \
+          release dut.hart.ieu.dp.ReadDataM; \
         if(textM.substr(0,5) == "rdtime") begin \
-          $display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
+          //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
           force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
         end \
       end \
@@ -550,10 +551,10 @@ module testbench();
           //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
           release dut.uncore.clint.clint.MTIME;
         end 
-        if (ExpectedMemAdrM == 'h10000005) begin
+        //if (ExpectedMemAdrM == 'h10000005) begin
           //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
-          release dut.hart.ieu.dp.ReadDataM;
-        end
+          //release dut.hart.ieu.dp.ReadDataM;
+        //end
       end
     end
   end

From f7b2d3b6df407702b0a96c8342f20f9cd7a6fdc8 Mon Sep 17 00:00:00 2001
From: bbracker <bbracker@hmc.edu>
Date: Wed, 8 Dec 2021 16:07:26 -0800
Subject: [PATCH 13/95] fix recursive signal logging for graphical sims

---
 wally-pipelined/regression/linux-wave.do      | 329 +++++++++---------
 wally-pipelined/regression/wally-buildroot.do |   4 +-
 2 files changed, 167 insertions(+), 166 deletions(-)

diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index 77ed87b2..4532b932 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -234,133 +234,138 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
+add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/funct
+add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/result
+add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
+add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
+add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
 add wave -noupdate -expand -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
-add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
-add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
-add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
-add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
-add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
+add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
+add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
@@ -382,20 +387,20 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pm
 add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
 add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
 add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PhysicalAddress
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/ReadAccessM
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/WriteAccessM
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/Match
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/FirstMatch
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/R
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X
-add wave -noupdate -expand -group lsu -expand -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PhysicalAddress
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/ReadAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/WriteAccessM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/Match
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/FirstMatch
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/R
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/W
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/X
+add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pmpchecker/L
 add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
@@ -409,24 +414,24 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /test
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
-add wave -noupdate -expand -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
-add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
-add wave -noupdate -expand -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
-add wave -noupdate -expand -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW
-add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW
-add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/STVAL
-add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
-add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
-add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
-add wave -noupdate -expand -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
+add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
+add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
+add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
+add wave -noupdate -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW
+add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW
+add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/STVAL
+add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
+add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
+add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
+add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
@@ -523,12 +528,8 @@ add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
 add wave -noupdate /testbench/dut/hart/ifu/PCTargetE
 add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
 add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
-add wave -noupdate /testbench/dut/uncore/dtim/A
-add wave -noupdate /testbench/dut/uncore/dtim/memwrite
-add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
-add wave -noupdate /testbench/dut/uncore/dtim/risingHREADYTim
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 23} {454406 ns} 0} {{Cursor 3} {29725 ns} 1}
+WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1}
 quietly wave cursor active 1
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 314
@@ -544,4 +545,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {454266 ns} {454536 ns}
+WaveRestoreZoom {14157667 ns} {14157811 ns}
diff --git a/wally-pipelined/regression/wally-buildroot.do b/wally-pipelined/regression/wally-buildroot.do
index 7fc87452..2ef74547 100644
--- a/wally-pipelined/regression/wally-buildroot.do
+++ b/wally-pipelined/regression/wally-buildroot.do
@@ -37,8 +37,8 @@ vsim workopt -suppress 8852,12070
 #-- Run the Simulation 
 run -all
 do linux-wave.do
-add log -r /*
+add log -recursive /*
 run -all
 
 exec ./slack-notifier/slack-notifier.py
-##quit
+#quit

From 37079626cdd683cc5cdb9ae7f3a2729956ba3c19 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 9 Dec 2021 11:44:12 -0600
Subject: [PATCH 14/95] Fixed numerous errors in the preformance counter
 updates. Fixed dcache reporting of access and misses. Added performance
 counter tracking to coremark.

---
 .../riscv64-baremetal/syscalls.c              |  16 +-
 wally-pipelined/regression/wave-coremark.do   | 502 ++++++++++++++++++
 wally-pipelined/src/cache/dcachefsm.sv        |  15 +-
 wally-pipelined/src/privileged/csrc.sv        |  12 +-
 4 files changed, 525 insertions(+), 20 deletions(-)
 create mode 100644 wally-pipelined/regression/wave-coremark.do

diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c b/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c
index 093c6fa2..96a2f627 100644
--- a/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c
+++ b/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c
@@ -7,6 +7,7 @@
 #include <limits.h>
 #include <sys/signal.h>
 #include "util.h"
+#include "coremark.h"
 #include <stdlib.h>
 
 #define SYS_write 64
@@ -57,7 +58,7 @@ static uintptr_t syscall(uintptr_t which, uint64_t arg0, uint64_t arg1, uint64_t
   return magic_mem[0];
 }
 
-#define NUM_COUNTERS 2
+#define NUM_COUNTERS 3
 static uintptr_t counters[NUM_COUNTERS];
 static char* counter_names[NUM_COUNTERS];
 
@@ -73,6 +74,16 @@ void setStats(int enable)
 
   READ_CTR(mcycle);
   READ_CTR(minstret);
+  READ_CTR(mhpmcounter3);
+  READ_CTR(mhpmcounter4);
+  READ_CTR(mhpmcounter5);
+  READ_CTR(mhpmcounter6);
+  READ_CTR(mhpmcounter7);
+  READ_CTR(mhpmcounter8);
+  READ_CTR(mhpmcounter9);
+  READ_CTR(mhpmcounter10);
+  READ_CTR(mhpmcounter11);
+  READ_CTR(mhpmcounter12);  
 
 #undef READ_CTR
 }
@@ -143,7 +154,8 @@ void _init(int cid, int nc)
     if (counters[i])
       pbuf += sprintf(pbuf, "%s = %d\n", counter_names[i], counters[i]);
   if (pbuf != buf)
-    printstr(buf);
+    //printstr(buf);
+    ee_printf(buf);
 
   exit(ret);
 }
diff --git a/wally-pipelined/regression/wave-coremark.do b/wally-pipelined/regression/wave-coremark.do
new file mode 100644
index 00000000..5ce1a232
--- /dev/null
+++ b/wally-pipelined/regression/wave-coremark.do
@@ -0,0 +1,502 @@
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /testbench/clk
+add wave -noupdate /testbench/reset
+add wave -noupdate /testbench/test
+add wave -noupdate /testbench/memfilename
+add wave -noupdate /testbench/dut/hart/SATP_REGW
+add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
+add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
+add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
+add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -expand -group HDU -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
+add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
+add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
+add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
+add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
+add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
+add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
+add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
+add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBValidF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BPInstrClassF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/BTBPredPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/RASPCF
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
+add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/TargetPC
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/hart/ifu/bpred/bpred/BPPredE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/PCSrcE
+add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/hart/ifu/bpred/bpred/BPPredDirWrongE
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateEN
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdatePC
+add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/hart/ifu/bpred/bpred/TargetPredictor/UpdateTarget
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PCE
+add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/TargetWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/FallThroughWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionPCWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/InstrClassE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/PredictionInstrClassWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
+add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
+add wave -noupdate -group {instruction pipeline} /testbench/InstrW
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -group {Decode Stage} /testbench/InstrDName
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
+add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
+add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
+add wave -noupdate -group alu -divider internals
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2E
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdE
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdM
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RdW
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/MemReadE
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteM
+add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/RegWriteW
+add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardAE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/ForwardBE
+add wave -noupdate -group Forward -color Thistle /testbench/dut/hart/ieu/fw/LoadStallD
+add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/WriteDataE
+add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
+add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
+add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/hart/PCF
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/hart/PCE
+add wave -noupdate -group PCS /testbench/dut/hart/PCM
+add wave -noupdate -group PCS /testbench/PCW
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallM
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
+add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
+add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
+add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/InstrReadF
+add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/MemSizeM
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HCLK
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESETn
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRDATA
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HREADY
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HRESP
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDR
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWDATA
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITE
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZE
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HBURST
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HPROT
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HTRANS
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
+add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
+add wave -noupdate -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
+add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
+add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
+add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
+add wave -noupdate -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushAdrFlag
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
+add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/FetchCountFlag
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
+add wave -noupdate -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
+add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
+add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
+add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
+add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBMiss
+add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
+add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/TLBPageFault
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/LoadAccessFaultM
+add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/hart/lsu/dmmu/StoreAccessFaultM
+add wave -noupdate -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBPAdr
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/PTE
+add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/hart/lsu/dmmu/genblk1/tlb/TLBWrite
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PhysicalAddress
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/SelRegions
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Cacheable
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/Idempotent
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/AtomicAllowed
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/pmachecker/PMAAccessFault
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAInstrAccessFaultF
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMALoadAccessFaultM
+add wave -noupdate -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PMAStoreAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
+add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
+add wave -noupdate -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
+add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
+add wave -noupdate -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
+add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
+add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
+add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
+add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
+add wave -noupdate /testbench/dut/hart/lsu/dcache/VAdr
+add wave -noupdate /testbench/dut/hart/lsu/dcache/MemPAdrM
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWRITE
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADY
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HTRANS
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWDATA
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
+add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWDATA
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWRITE
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADY
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HTRANS
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HRESPGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADYGPIO
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn
+add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HCLK
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HSELCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HADDR
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWRITE
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWDATA
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADY
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HTRANS
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HRESPCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADYCLINT
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM
+add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HCLK
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESETn
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HSELUART
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HADDR
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWRITE
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWDATA
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADUART
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESPUART
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADYUART
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/CTSb
+add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/RIb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/SOUT
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RTSb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/DTRb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT1b
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT2b
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb
+add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb
+add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK
+add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
+add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
+add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
+add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
+add wave -noupdate -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/CYCLE_REGW
+add wave -noupdate -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
+add wave -noupdate -label LoadStall -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[3]}
+add wave -noupdate -label {Branch Instr} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[5]}
+add wave -noupdate -label {BP Dir Wrong} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[4]}
+add wave -noupdate -label {Jump, Jal, Jalr} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[7]}
+add wave -noupdate -label {RAS Wrong} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[8]}
+add wave -noupdate -label {BTB Wrong} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[6]}
+add wave -noupdate -label {BP Class Non CFI Wrong} -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[10]}
+add wave -noupdate -label DCacheAccess -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[11]}
+add wave -noupdate -label DCacheMiss -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[12]}
+add wave -noupdate -label Return -radix unsigned {/testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW[9]}
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/InstrValidM
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/InstrValidNotFlushedM
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/BPPredDirWrongM
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/genblk1/LoadStallM
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/genblk1/NextHPMCOUNTERM
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/DCacheMiss
+add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/DCacheAccess
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 6} {17923831 ns} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 250
+configure wave -valuecolwidth 297
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ns} {18715695 ns}
diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index 55abd40e..cbfd2091 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -143,6 +143,9 @@ module dcachefsm
   assign AnyCPUReqM = |MemRWM | (|AtomicM);
   assign CntEn = PreCntEn & AHBAck;
 
+  // outputs for the performance counters.
+  assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY;
+  assign DCacheMiss = DCacheAccess & CacheableM & ~CacheHit;
 
   always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_READY;
@@ -165,8 +168,6 @@ module dcachefsm
     CommittedM = 1'b0;        
     SelUncached = 1'b0;
     SelEvict = 1'b0;
-    DCacheAccess = 1'b0;
-    DCacheMiss = 1'b0;
     LRUWriteEn = 1'b0;
     MemAfterIWalkDone = 1'b0;
     SelFlush = 1'b0;
@@ -184,8 +185,6 @@ module dcachefsm
 	DCacheStall = 1'b0;
 	AHBRead = 1'b0;	  
 	AHBWrite = 1'b0;
-	DCacheAccess = 1'b0;
-	DCacheMiss = 1'b0;
 	SelAdrM = 2'b00;
 	SRAMWordWriteEnableM = 1'b0;
 	SetDirty = 1'b0;
@@ -234,7 +233,6 @@ module dcachefsm
 	// read hit valid cached
 	else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
 	  DCacheStall = 1'b0;
-	  DCacheAccess = 1'b1;
 	  LRUWriteEn = 1'b1;
 	  
 	  if(StallWtoDCache) begin
@@ -266,8 +264,6 @@ module dcachefsm
 	  NextState = STATE_MISS_FETCH_WDV;
 	  CntReset = 1'b1;
 	  DCacheStall = 1'b1;
-	  DCacheAccess = 1'b1;
-	  DCacheMiss = 1'b1;
 	end
 	// uncached write
 	else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
@@ -616,8 +612,6 @@ module dcachefsm
       // itlb => instruction page fault states with memory request.
       STATE_PTW_FAULT_READY: begin
 	DCacheStall = 1'b0;
-	DCacheAccess = 1'b0;
-	DCacheMiss = 1'b0;
 	LRUWriteEn = 1'b0;
 	SelAdrM = 2'b00;
 	MemAfterIWalkDone = 1'b0;
@@ -633,7 +627,6 @@ module dcachefsm
 	// read hit valid cached
 	if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
 	  DCacheStall = 1'b0;
-	  DCacheAccess = 1'b1;
 	  LRUWriteEn = 1'b1;
 	  
 	  if(StallWtoDCache) begin
@@ -668,8 +661,6 @@ module dcachefsm
 	  NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
 	  CntReset = 1'b1;
 	  DCacheStall = 1'b1;
-	  DCacheAccess = 1'b1;
-	  DCacheMiss = 1'b1;
 	end
 	// uncached write
 	else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv
index 7450b614..f1e3c966 100644
--- a/wally-pipelined/src/privileged/csrc.sv
+++ b/wally-pipelined/src/privileged/csrc.sv
@@ -130,11 +130,11 @@ module csrc #(parameter
 
 	logic LoadStallE, LoadStallM;
 	
-	flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(FlushE), .en(~StallE), .d(LoadStallD), .q(LoadStallE));
+	flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE));  // don't flush the load stall during a load stall.
 	flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));	
 	
         assign CounterEvent[2] = InstrValidNotFlushedM;
-        assign CounterEvent[3] = LoadStallM & InstrValidNotFlushedM;
+        assign CounterEvent[3] = LoadStallM;  // don't want to suppress on flush as this only happens if flushed.
         assign CounterEvent[4] = BPPredDirWrongM & InstrValidNotFlushedM;
         assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;
         assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;
@@ -142,8 +142,8 @@ module csrc #(parameter
         assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;
         assign CounterEvent[9] = InstrClassM[3] & InstrValidNotFlushedM;
         assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM;
-        assign CounterEvent[11] = DCacheAccess & InstrValidNotFlushedM;
-        assign CounterEvent[12] = DCacheMiss & InstrValidNotFlushedM;      
+        assign CounterEvent[11] = DCacheAccess;
+        assign CounterEvent[12] = DCacheMiss;      
         assign CounterEvent[`COUNTERS-1:13] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
       end
       
@@ -152,7 +152,7 @@ module csrc #(parameter
             assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
             always @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
               if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
-              else if (~StallW) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
+              else HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
 
             if (`XLEN==32) begin
                 logic [`COUNTERS-1:3] WriteHPMCOUNTERHM;
@@ -162,7 +162,7 @@ module csrc #(parameter
                 assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
                 always @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
                     if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
-                    else if (~StallW) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
+                    else  HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
             end else begin
                 assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
             end

From 4cea8d1a29be64cd30c2d808d3d3f9bcb8f3e02c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Thu, 9 Dec 2021 14:48:17 -0600
Subject: [PATCH 15/95] Performance counters now output of coremark.

---
 .../riscv64-baremetal/syscalls.c              | 25 +++++++++++++++++--
 .../config/coremark_bare/wally-config.vh      |  7 +++---
 2 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c b/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c
index 96a2f627..8945385b 100644
--- a/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c
+++ b/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c
@@ -154,8 +154,29 @@ void _init(int cid, int nc)
     if (counters[i])
       pbuf += sprintf(pbuf, "%s = %d\n", counter_names[i], counters[i]);
   if (pbuf != buf)
-    //printstr(buf);
-    ee_printf(buf);
+    printstr(buf);
+  counters[3] = read_csr(mhpmcounter3) - counters[3];
+  counters[4] = read_csr(mhpmcounter4) - counters[4];
+  counters[5] = read_csr(mhpmcounter5) - counters[5];
+  counters[6] = read_csr(mhpmcounter6) - counters[6];
+  counters[7] = read_csr(mhpmcounter7) - counters[7];
+  counters[8] = read_csr(mhpmcounter8) - counters[8];
+  counters[9] = read_csr(mhpmcounter9) - counters[9];
+  counters[10] = read_csr(mhpmcounter10) - counters[10];
+  counters[11] = read_csr(mhpmcounter11) - counters[11];
+  counters[12] = read_csr(mhpmcounter12) - counters[12];    
+
+  ee_printf("Load Stalls %d\n", counters[3]);
+  ee_printf("D-Cache Accesses %d\n", counters[11]);
+  ee_printf("D-Cache Misses %d\n", counters[12]);    
+  ee_printf("Branches %d\n", counters[5]);
+  ee_printf("Branches Miss Predictions %d\n", counters[4]);
+  ee_printf("BTB Misses %d\n", counters[6]);
+  ee_printf("Jump, JAL, JALR %d\n", counters[7]);
+  ee_printf("RAS Wrong %d\n", counters[8]);
+  ee_printf("Returns %d\n", counters[9]);
+  ee_printf("BP Class Wrong %d\n", counters[10]);
+  ee_printf("Done printing performance counters\n");
 
   exit(ret);
 }
diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh
index ae479a25..0adca26b 100644
--- a/wally-pipelined/config/coremark_bare/wally-config.vh
+++ b/wally-pipelined/config/coremark_bare/wally-config.vh
@@ -37,7 +37,7 @@
 
 //`define MISA (32'h00000104)
 //`define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0)
-`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 `define ZICSR_SUPPORTED 1
 `define ZIFENCEI_SUPPORTED 1
 `define COUNTERS 32
@@ -62,10 +62,9 @@
 // Cache configuration.  Sizes should be a power of two
 // typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
 `define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 2048
+`define DCACHE_WAYSIZEINBYTES 4096
 `define DCACHE_BLOCKLENINBITS 256
-`define DCACHE_REPLBITS 3
-`define ICACHE_NUMWAYS 1
+`define ICACHE_NUMWAYS 4
 `define ICACHE_WAYSIZEINBYTES 4096
 `define ICACHE_BLOCKLENINBITS 256
 

From 1a82b504834fa8d71eac6d76d00a2d993efd1dc7 Mon Sep 17 00:00:00 2001
From: Kevin <kevin12kim27@gmail.com>
Date: Fri, 10 Dec 2021 20:26:20 -0800
Subject: [PATCH 16/95] edited one testbench, yet to run regression

---
 .../testbench/testbench-coremark_bare.sv      | 24 ++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index 06ca47b0..5d5b0cc6 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -72,7 +72,29 @@ module testbench();
   assign HREADYEXT = 1;
   assign HRESPEXT = 0;
   assign HRDATAEXT = 0;
-  wallypipelinedsoc dut(.*); 
+  wallypipelinedsoc dut(.clk, .reset_ext, 
+  .HRDATAEXT,
+  .HREADYEXT, .HRESPEXT,
+  .HSELEXT,
+  .HCLK, .HRESETn,
+  .HADDR,
+  .HWDATA,
+  .HWRITE,
+  .HSIZE,
+  .HBURST,
+  .HPROT,
+  .HTRANS,
+  .HMASTLOCK,
+  .HREADY,
+  .GPIOPinsIn,
+  .GPIOPinsOut, .GPIOPinsEn,
+  .UARTSin,
+  .UARTSout,
+  .SDCCmdIn,
+  .SDCCmdOut,
+  .SDCCmdOE,			  
+  .SDCDatIn,
+  .SDCCLK); 
 
   logic [31:0] InstrW;
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);

From 82bab8e90e485c687a8fb7679a73b9c16160e14b Mon Sep 17 00:00:00 2001
From: kwan <kwan@tera.eng.hmc.edu>
Date: Sun, 12 Dec 2021 09:54:14 -0800
Subject: [PATCH 17/95] Privilige .*s removed

---
 addins/riscv-arch-test                       |  2 +-
 wally-pipelined/src/privileged/privileged.sv | 69 +++++++++++++++++---
 2 files changed, 60 insertions(+), 11 deletions(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index be67c99b..84d04381 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
+Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index a6c3f2d8..512364e6 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -21,7 +21,8 @@
 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
 // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
 // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ SOFTWARE.
 ///////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -84,7 +85,7 @@ module privileged (
 
   logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
   logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW;
-//  logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
+  //  logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
   logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
 
   logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
@@ -111,8 +112,8 @@ module privileged (
   ///////////////////////////////////////////
 
   // get bits of DELEG registers based on CAUSE
-//  assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
-//  assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
+  //  assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
+  //  assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
   assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
   assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : SEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; // depricated
   
@@ -143,15 +144,44 @@ module privileged (
 
   ///////////////////////////////////////////
   // decode privileged instructions
-  ///////////////////////////////////////////
 
-  privdec pmd(.InstrM(InstrM[31:20]), .*);
+
+  ///////////////////////////////////////////
+  
+  privdec pmd(.InstrM(InstrM[31:20]), 
+              .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
+              .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, 
+              .uretM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
 
   ///////////////////////////////////////////
   // Control and Status Registers
   ///////////////////////////////////////////
-
-  csr csr(.*);
+  
+  csr csr(.clk,. reset,
+          .FlushE, .FlushM, .FlushW,
+          .StallE, .StallM, .StallW,
+          .InstrM, .PCM, .SrcAM,
+          .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM,
+          .TimerIntM, .ExtIntM, .SwIntM,
+          .MTIME_CLINT, .MTIMECMP_CLINT,
+          .InstrValidM, .FRegWriteM, .LoadStallD,
+          .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, 
+          .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess,
+          .NextPrivilegeModeM, .PrivilegeModeW,
+          .CauseM, .NextFaultMtvalM, .STATUS_MPP,
+          .STATUS_SPP, .STATUS_TSR,
+          .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
+          .MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, 
+          .SATP_REGW,
+          .MIP_REGW, .MIE_REGW, .SIP_REGW, S.IE_REGW,
+          .STATUS_MIE, .STATUS_SIE,
+          .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW,
+          .PMPCFG_ARRAY_REGW,
+          .PMPADDR_ARRAY_REGW,
+          .SetFflagsM,
+          .FRM_REGW, 
+          .CSRReadValW,
+          .IllegalCSRAccessM);
 
   ///////////////////////////////////////////
   // Extract exceptions by name and handle them 
@@ -188,9 +218,28 @@ module privileged (
   flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM,
                   {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
                   {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
-  // *** it should be possible to compbine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
+  // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
+  
+  trap trap(.clk, .reset,
+            .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
+            .BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
+            .LoadAccessFaultM, .StoreAccessFaultM, .EcallFaultM, .InstrPageFaultM,
+            .LoadPageFaultM, .StorePageFaultM,
+            .mretM, .sretM, .uretM,
+            .PrivilegeModeW, .NextPrivilegeModeM
+            .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
+            .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
+            .STATUS_MIE, .STATUS_SIE
+            .PCM,
+            .InstrMisalignedAdrM, .MemAdrM, 
+            .InstrM,
+            .InstrValidM, .CommittedM,
+            .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
+            .InterruptM,
+            .ExceptionM,
+            .PendingInterruptM,
+            .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);
 
-  trap trap(.*);
 
 endmodule
 

From a95efea0b34f219c420e9ff7f6b613a0869ba791 Mon Sep 17 00:00:00 2001
From: kwan <kwan@tera.eng.hmc.edu>
Date: Sun, 12 Dec 2021 09:55:45 -0800
Subject: [PATCH 18/95] Priviledged .* removed

---
 wally-pipelined/src/privileged/privileged.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 512364e6..3cb7a183 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -22,7 +22,7 @@
 // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
 // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
+// SOFTWARE.
 ///////////////////////////////////////////
 
 `include "wally-config.vh"

From 545c5861860b181e08f9893349a0e9a70258a487 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 12 Dec 2021 15:05:50 -0600
Subject: [PATCH 19/95] Added proper credit to Richard Davis, the author of the
 original sd card reader.

---
 wally-pipelined/src/hazard/hazard.sv        | 18 +++++++++---------
 wally-pipelined/src/sdc/clkdivider.sv       |  5 +++--
 wally-pipelined/src/sdc/counter.sv          |  5 +++--
 wally-pipelined/src/sdc/crc16_sipo_np_ce.sv |  5 +++--
 wally-pipelined/src/sdc/crc7_pipo.sv        |  5 +++--
 wally-pipelined/src/sdc/crc7_sipo_np_ce.sv  |  4 ++--
 wally-pipelined/src/sdc/piso_generic_ce.sv  |  4 ++--
 wally-pipelined/src/sdc/sd_clk_fsm.sv       |  4 ++--
 wally-pipelined/src/sdc/sd_cmd_fsm.sv       |  4 ++--
 wally-pipelined/src/sdc/sd_dat_fsm.sv       |  4 ++--
 wally-pipelined/src/sdc/sd_top.sv           |  4 ++--
 wally-pipelined/src/sdc/sipo_generic_ce.sv  |  4 ++--
 12 files changed, 35 insertions(+), 31 deletions(-)

diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv
index 72deeac0..9ff93020 100644
--- a/wally-pipelined/src/hazard/hazard.sv
+++ b/wally-pipelined/src/hazard/hazard.sv
@@ -27,16 +27,16 @@
 
 module hazard(
   // Detect hazards
-	      input logic  BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
-	      input logic  LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD,
-	      input logic  LSUStall, ICacheStallF,
-              input logic  FPUStallD, FStallD,
-	      input logic  DivBusyE,FDivBusyE,
-	      input logic  EcallFaultM, BreakpointFaultM,
-        input logic  InvalidateICacheM,
+(* mark_debug = "true" *)	      input logic  BPPredWrongE, CSRWritePendingDEM, RetM, TrapM,
+(* mark_debug = "true" *)	      input logic  LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD,
+(* mark_debug = "true" *)	      input logic  LSUStall, ICacheStallF,
+(* mark_debug = "true" *)              input logic  FPUStallD, FStallD,
+(* mark_debug = "true" *)	      input logic  DivBusyE,FDivBusyE,
+(* mark_debug = "true" *)	      input logic  EcallFaultM, BreakpointFaultM,
+(* mark_debug = "true" *)        input logic  InvalidateICacheM,
   // Stall & flush outputs
-	      output logic StallF, StallD, StallE, StallM, StallW,
-	      output logic FlushF, FlushD, FlushE, FlushM, FlushW
+(* mark_debug = "true" *)	      output logic StallF, StallD, StallE, StallM, StallW,
+(* mark_debug = "true" *)	      output logic FlushF, FlushD, FlushE, FlushM, FlushW
 );
 
   logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
diff --git a/wally-pipelined/src/sdc/clkdivider.sv b/wally-pipelined/src/sdc/clkdivider.sv
index 8dc8a312..d4218aa4 100644
--- a/wally-pipelined/src/sdc/clkdivider.sv
+++ b/wally-pipelined/src/sdc/clkdivider.sv
@@ -1,8 +1,9 @@
 ///////////////////////////////////////////
 // clock divider.sv
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
+// Converted to system verilog.
 //
 // Purpose: clock divider for sd flash
 // 
diff --git a/wally-pipelined/src/sdc/counter.sv b/wally-pipelined/src/sdc/counter.sv
index 689c443e..29ef2fd1 100644
--- a/wally-pipelined/src/sdc/counter.sv
+++ b/wally-pipelined/src/sdc/counter.sv
@@ -1,8 +1,9 @@
 ///////////////////////////////////////////
 // counter.sv
 //
-// Written: Ross Thompson
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson
+// Converted to system verilog.
 //
 // Purpose: basic up counter
 // 
diff --git a/wally-pipelined/src/sdc/crc16_sipo_np_ce.sv b/wally-pipelined/src/sdc/crc16_sipo_np_ce.sv
index 444555c7..9f12abc0 100644
--- a/wally-pipelined/src/sdc/crc16_sipo_np_ce.sv
+++ b/wally-pipelined/src/sdc/crc16_sipo_np_ce.sv
@@ -1,8 +1,9 @@
 ///////////////////////////////////////////
 // crc16 sipo np ce
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
+// Converted to system verilog.
 //
 // Purpose: CRC16 generator SIPO using register_ce
 //              w/o appending any zero-bits to the message
diff --git a/wally-pipelined/src/sdc/crc7_pipo.sv b/wally-pipelined/src/sdc/crc7_pipo.sv
index 46ba0062..4172a2c9 100644
--- a/wally-pipelined/src/sdc/crc7_pipo.sv
+++ b/wally-pipelined/src/sdc/crc7_pipo.sv
@@ -1,8 +1,9 @@
 ///////////////////////////////////////////
 // crc7 sipo np ce
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
+// Converted to system verilog.
 //
 // Purpose:  takes 40 bits of input, generates 7 bit CRC after a single
 // clock cycle!
diff --git a/wally-pipelined/src/sdc/crc7_sipo_np_ce.sv b/wally-pipelined/src/sdc/crc7_sipo_np_ce.sv
index 5721aa95..7039c1fc 100644
--- a/wally-pipelined/src/sdc/crc7_sipo_np_ce.sv
+++ b/wally-pipelined/src/sdc/crc7_sipo_np_ce.sv
@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // crc16 sipo np ce
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
 //
 // Purpose: CRC7 generator SIPO using register_ce
 //          w/o appending any zero-bits othe message
diff --git a/wally-pipelined/src/sdc/piso_generic_ce.sv b/wally-pipelined/src/sdc/piso_generic_ce.sv
index ad1d6a17..022d0e8b 100644
--- a/wally-pipelined/src/sdc/piso_generic_ce.sv
+++ b/wally-pipelined/src/sdc/piso_generic_ce.sv
@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // piso generic ce
 //
-// Written: Ross Thompson September 18, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 18, 2021
 //
 // 
 // A component of the Wally configurable RISC-V project.
diff --git a/wally-pipelined/src/sdc/sd_clk_fsm.sv b/wally-pipelined/src/sdc/sd_clk_fsm.sv
index 558f695f..d56b443d 100644
--- a/wally-pipelined/src/sdc/sd_clk_fsm.sv
+++ b/wally-pipelined/src/sdc/sd_clk_fsm.sv
@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sd_clk_fsm.sv
 //
-// Written: Ross Thompson September 19, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 19, 2021
 //
 // Purpose: Controls clock dividers.
 // Replaces s_disable_sd_clocks, s_select_hs_clk, s_enable_hs_clk
diff --git a/wally-pipelined/src/sdc/sd_cmd_fsm.sv b/wally-pipelined/src/sdc/sd_cmd_fsm.sv
index fedb4b2f..ef9467e9 100644
--- a/wally-pipelined/src/sdc/sd_cmd_fsm.sv
+++ b/wally-pipelined/src/sdc/sd_cmd_fsm.sv
@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sd_clk_fsm.sv
 //
-// Written: Ross Thompson September 19, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 19, 2021
 //
 // Purpose: Finite state machine for the SD CMD bus
 // 
diff --git a/wally-pipelined/src/sdc/sd_dat_fsm.sv b/wally-pipelined/src/sdc/sd_dat_fsm.sv
index 7726f1cb..72747b83 100644
--- a/wally-pipelined/src/sdc/sd_dat_fsm.sv
+++ b/wally-pipelined/src/sdc/sd_dat_fsm.sv
@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sd_dat_fsm.sv
 //
-// Written: Ross Thompson September 19, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 19, 2021
 //
 // Purpose: Runs in parallel with sd_cmd_fsm to control activity on the DAT
 // bus of the SD card.
diff --git a/wally-pipelined/src/sdc/sd_top.sv b/wally-pipelined/src/sdc/sd_top.sv
index b18b3d17..02315271 100644
--- a/wally-pipelined/src/sdc/sd_top.sv
+++ b/wally-pipelined/src/sdc/sd_top.sv
@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sd_top.sv
 //
-// Written: Ross Thompson September 19, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 19, 2021
 //
 // Purpose: SD card controller
 // 
diff --git a/wally-pipelined/src/sdc/sipo_generic_ce.sv b/wally-pipelined/src/sdc/sipo_generic_ce.sv
index 210767af..e76a41b1 100644
--- a/wally-pipelined/src/sdc/sipo_generic_ce.sv
+++ b/wally-pipelined/src/sdc/sipo_generic_ce.sv
@@ -1,8 +1,8 @@
 ///////////////////////////////////////////
 // sipo_generic_ce
 //
-// Written: Ross Thompson September 20, 2021
-// Modified: 
+// Written: Richard Davis
+// Modified: Ross Thompson September 20, 2021
 //
 // Purpose:  serial to n-bit parallel shift register using register_ce.
 // When given a n-bit word as input transmit the message serially MSB (leftmost)

From f2628494e3a640b44b57b6abf1c4f481aff1ab1e Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 12 Dec 2021 15:06:29 -0600
Subject: [PATCH 20/95] Missed constraints file for xilinx ILA.

---
 fpga/constraints/debug2.xdc | 447 ++++++++++++++++++++++++++++++++++++
 1 file changed, 447 insertions(+)
 create mode 100644 fpga/constraints/debug2.xdc

diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
new file mode 100644
index 00000000..9cb695b9
--- /dev/null
+++ b/fpga/constraints/debug2.xdc
@@ -0,0 +1,447 @@
+create_debug_core u_ila_0 ila
+
+set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
+set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
+set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
+set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
+set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
+set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
+set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
+startgroup 
+set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
+set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
+set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
+set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
+endgroup
+connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]
+set_property port_width 64 [get_debug_ports u_ila_0/probe0]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
+connect_debug_port u_ila_0/probe0 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HWDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HWDATA[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe1]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
+connect_debug_port u_ila_0/probe1 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/HRDATA[0]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[1]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[2]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[3]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[4]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[5]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[6]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[7]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[8]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[9]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[10]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[11]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[12]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[13]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[14]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[15]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[16]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[17]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[18]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[19]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[20]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[21]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[22]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[23]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[24]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[25]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[26]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[27]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[28]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[29]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[30]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[31]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[32]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[33]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[34]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[35]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[36]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[37]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[38]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[39]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[40]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[41]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[42]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[43]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[44]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[45]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[46]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[47]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[48]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[49]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[50]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[51]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[52]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[53]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[54]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[55]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[56]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[57]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[58]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[59]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[60]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[61]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[62]} {wallypipelinedsoc/hart/lsu/dcache/HRDATA[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe2]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
+connect_debug_port u_ila_0/probe2 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[0]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[1]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[2]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[3]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[4]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[5]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[6]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[7]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[8]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[9]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[10]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[11]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[12]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[13]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[14]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[15]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[16]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[17]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[18]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[19]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[20]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[21]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[22]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[23]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[24]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[25]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[26]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[27]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[28]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[29]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[30]} {wallypipelinedsoc/hart/lsu/dcache/AHBPAdr[31]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe3]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
+connect_debug_port u_ila_0/probe3 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIP_REGW[11]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe4]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
+connect_debug_port u_ila_0/probe4 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MCAUSE_REGW[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe5]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
+connect_debug_port u_ila_0/probe5 [get_nets [list {wallypipelinedsoc/hart/ReadDataM[0]} {wallypipelinedsoc/hart/ReadDataM[1]} {wallypipelinedsoc/hart/ReadDataM[2]} {wallypipelinedsoc/hart/ReadDataM[3]} {wallypipelinedsoc/hart/ReadDataM[4]} {wallypipelinedsoc/hart/ReadDataM[5]} {wallypipelinedsoc/hart/ReadDataM[6]} {wallypipelinedsoc/hart/ReadDataM[7]} {wallypipelinedsoc/hart/ReadDataM[8]} {wallypipelinedsoc/hart/ReadDataM[9]} {wallypipelinedsoc/hart/ReadDataM[10]} {wallypipelinedsoc/hart/ReadDataM[11]} {wallypipelinedsoc/hart/ReadDataM[12]} {wallypipelinedsoc/hart/ReadDataM[13]} {wallypipelinedsoc/hart/ReadDataM[14]} {wallypipelinedsoc/hart/ReadDataM[15]} {wallypipelinedsoc/hart/ReadDataM[16]} {wallypipelinedsoc/hart/ReadDataM[17]} {wallypipelinedsoc/hart/ReadDataM[18]} {wallypipelinedsoc/hart/ReadDataM[19]} {wallypipelinedsoc/hart/ReadDataM[20]} {wallypipelinedsoc/hart/ReadDataM[21]} {wallypipelinedsoc/hart/ReadDataM[22]} {wallypipelinedsoc/hart/ReadDataM[23]} {wallypipelinedsoc/hart/ReadDataM[24]} {wallypipelinedsoc/hart/ReadDataM[25]} {wallypipelinedsoc/hart/ReadDataM[26]} {wallypipelinedsoc/hart/ReadDataM[27]} {wallypipelinedsoc/hart/ReadDataM[28]} {wallypipelinedsoc/hart/ReadDataM[29]} {wallypipelinedsoc/hart/ReadDataM[30]} {wallypipelinedsoc/hart/ReadDataM[31]} {wallypipelinedsoc/hart/ReadDataM[32]} {wallypipelinedsoc/hart/ReadDataM[33]} {wallypipelinedsoc/hart/ReadDataM[34]} {wallypipelinedsoc/hart/ReadDataM[35]} {wallypipelinedsoc/hart/ReadDataM[36]} {wallypipelinedsoc/hart/ReadDataM[37]} {wallypipelinedsoc/hart/ReadDataM[38]} {wallypipelinedsoc/hart/ReadDataM[39]} {wallypipelinedsoc/hart/ReadDataM[40]} {wallypipelinedsoc/hart/ReadDataM[41]} {wallypipelinedsoc/hart/ReadDataM[42]} {wallypipelinedsoc/hart/ReadDataM[43]} {wallypipelinedsoc/hart/ReadDataM[44]} {wallypipelinedsoc/hart/ReadDataM[45]} {wallypipelinedsoc/hart/ReadDataM[46]} {wallypipelinedsoc/hart/ReadDataM[47]} {wallypipelinedsoc/hart/ReadDataM[48]} {wallypipelinedsoc/hart/ReadDataM[49]} {wallypipelinedsoc/hart/ReadDataM[50]} {wallypipelinedsoc/hart/ReadDataM[51]} {wallypipelinedsoc/hart/ReadDataM[52]} {wallypipelinedsoc/hart/ReadDataM[53]} {wallypipelinedsoc/hart/ReadDataM[54]} {wallypipelinedsoc/hart/ReadDataM[55]} {wallypipelinedsoc/hart/ReadDataM[56]} {wallypipelinedsoc/hart/ReadDataM[57]} {wallypipelinedsoc/hart/ReadDataM[58]} {wallypipelinedsoc/hart/ReadDataM[59]} {wallypipelinedsoc/hart/ReadDataM[60]} {wallypipelinedsoc/hart/ReadDataM[61]} {wallypipelinedsoc/hart/ReadDataM[62]} {wallypipelinedsoc/hart/ReadDataM[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe6]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
+connect_debug_port u_ila_0/probe6 [get_nets [list {wallypipelinedsoc/hart/WriteDataM[0]} {wallypipelinedsoc/hart/WriteDataM[1]} {wallypipelinedsoc/hart/WriteDataM[2]} {wallypipelinedsoc/hart/WriteDataM[3]} {wallypipelinedsoc/hart/WriteDataM[4]} {wallypipelinedsoc/hart/WriteDataM[5]} {wallypipelinedsoc/hart/WriteDataM[6]} {wallypipelinedsoc/hart/WriteDataM[7]} {wallypipelinedsoc/hart/WriteDataM[8]} {wallypipelinedsoc/hart/WriteDataM[9]} {wallypipelinedsoc/hart/WriteDataM[10]} {wallypipelinedsoc/hart/WriteDataM[11]} {wallypipelinedsoc/hart/WriteDataM[12]} {wallypipelinedsoc/hart/WriteDataM[13]} {wallypipelinedsoc/hart/WriteDataM[14]} {wallypipelinedsoc/hart/WriteDataM[15]} {wallypipelinedsoc/hart/WriteDataM[16]} {wallypipelinedsoc/hart/WriteDataM[17]} {wallypipelinedsoc/hart/WriteDataM[18]} {wallypipelinedsoc/hart/WriteDataM[19]} {wallypipelinedsoc/hart/WriteDataM[20]} {wallypipelinedsoc/hart/WriteDataM[21]} {wallypipelinedsoc/hart/WriteDataM[22]} {wallypipelinedsoc/hart/WriteDataM[23]} {wallypipelinedsoc/hart/WriteDataM[24]} {wallypipelinedsoc/hart/WriteDataM[25]} {wallypipelinedsoc/hart/WriteDataM[26]} {wallypipelinedsoc/hart/WriteDataM[27]} {wallypipelinedsoc/hart/WriteDataM[28]} {wallypipelinedsoc/hart/WriteDataM[29]} {wallypipelinedsoc/hart/WriteDataM[30]} {wallypipelinedsoc/hart/WriteDataM[31]} {wallypipelinedsoc/hart/WriteDataM[32]} {wallypipelinedsoc/hart/WriteDataM[33]} {wallypipelinedsoc/hart/WriteDataM[34]} {wallypipelinedsoc/hart/WriteDataM[35]} {wallypipelinedsoc/hart/WriteDataM[36]} {wallypipelinedsoc/hart/WriteDataM[37]} {wallypipelinedsoc/hart/WriteDataM[38]} {wallypipelinedsoc/hart/WriteDataM[39]} {wallypipelinedsoc/hart/WriteDataM[40]} {wallypipelinedsoc/hart/WriteDataM[41]} {wallypipelinedsoc/hart/WriteDataM[42]} {wallypipelinedsoc/hart/WriteDataM[43]} {wallypipelinedsoc/hart/WriteDataM[44]} {wallypipelinedsoc/hart/WriteDataM[45]} {wallypipelinedsoc/hart/WriteDataM[46]} {wallypipelinedsoc/hart/WriteDataM[47]} {wallypipelinedsoc/hart/WriteDataM[48]} {wallypipelinedsoc/hart/WriteDataM[49]} {wallypipelinedsoc/hart/WriteDataM[50]} {wallypipelinedsoc/hart/WriteDataM[51]} {wallypipelinedsoc/hart/WriteDataM[52]} {wallypipelinedsoc/hart/WriteDataM[53]} {wallypipelinedsoc/hart/WriteDataM[54]} {wallypipelinedsoc/hart/WriteDataM[55]} {wallypipelinedsoc/hart/WriteDataM[56]} {wallypipelinedsoc/hart/WriteDataM[57]} {wallypipelinedsoc/hart/WriteDataM[58]} {wallypipelinedsoc/hart/WriteDataM[59]} {wallypipelinedsoc/hart/WriteDataM[60]} {wallypipelinedsoc/hart/WriteDataM[61]} {wallypipelinedsoc/hart/WriteDataM[62]} {wallypipelinedsoc/hart/WriteDataM[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe7]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
+connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/PCM[0]} {wallypipelinedsoc/hart/PCM[1]} {wallypipelinedsoc/hart/PCM[2]} {wallypipelinedsoc/hart/PCM[3]} {wallypipelinedsoc/hart/PCM[4]} {wallypipelinedsoc/hart/PCM[5]} {wallypipelinedsoc/hart/PCM[6]} {wallypipelinedsoc/hart/PCM[7]} {wallypipelinedsoc/hart/PCM[8]} {wallypipelinedsoc/hart/PCM[9]} {wallypipelinedsoc/hart/PCM[10]} {wallypipelinedsoc/hart/PCM[11]} {wallypipelinedsoc/hart/PCM[12]} {wallypipelinedsoc/hart/PCM[13]} {wallypipelinedsoc/hart/PCM[14]} {wallypipelinedsoc/hart/PCM[15]} {wallypipelinedsoc/hart/PCM[16]} {wallypipelinedsoc/hart/PCM[17]} {wallypipelinedsoc/hart/PCM[18]} {wallypipelinedsoc/hart/PCM[19]} {wallypipelinedsoc/hart/PCM[20]} {wallypipelinedsoc/hart/PCM[21]} {wallypipelinedsoc/hart/PCM[22]} {wallypipelinedsoc/hart/PCM[23]} {wallypipelinedsoc/hart/PCM[24]} {wallypipelinedsoc/hart/PCM[25]} {wallypipelinedsoc/hart/PCM[26]} {wallypipelinedsoc/hart/PCM[27]} {wallypipelinedsoc/hart/PCM[28]} {wallypipelinedsoc/hart/PCM[29]} {wallypipelinedsoc/hart/PCM[30]} {wallypipelinedsoc/hart/PCM[31]} {wallypipelinedsoc/hart/PCM[32]} {wallypipelinedsoc/hart/PCM[33]} {wallypipelinedsoc/hart/PCM[34]} {wallypipelinedsoc/hart/PCM[35]} {wallypipelinedsoc/hart/PCM[36]} {wallypipelinedsoc/hart/PCM[37]} {wallypipelinedsoc/hart/PCM[38]} {wallypipelinedsoc/hart/PCM[39]} {wallypipelinedsoc/hart/PCM[40]} {wallypipelinedsoc/hart/PCM[41]} {wallypipelinedsoc/hart/PCM[42]} {wallypipelinedsoc/hart/PCM[43]} {wallypipelinedsoc/hart/PCM[44]} {wallypipelinedsoc/hart/PCM[45]} {wallypipelinedsoc/hart/PCM[46]} {wallypipelinedsoc/hart/PCM[47]} {wallypipelinedsoc/hart/PCM[48]} {wallypipelinedsoc/hart/PCM[49]} {wallypipelinedsoc/hart/PCM[50]} {wallypipelinedsoc/hart/PCM[51]} {wallypipelinedsoc/hart/PCM[52]} {wallypipelinedsoc/hart/PCM[53]} {wallypipelinedsoc/hart/PCM[54]} {wallypipelinedsoc/hart/PCM[55]} {wallypipelinedsoc/hart/PCM[56]} {wallypipelinedsoc/hart/PCM[57]} {wallypipelinedsoc/hart/PCM[58]} {wallypipelinedsoc/hart/PCM[59]} {wallypipelinedsoc/hart/PCM[60]} {wallypipelinedsoc/hart/PCM[61]} {wallypipelinedsoc/hart/PCM[62]} {wallypipelinedsoc/hart/PCM[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe8]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
+connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe9]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
+connect_debug_port u_ila_0/probe9 [get_nets [list {wallypipelinedsoc/hart/InstrM[0]} {wallypipelinedsoc/hart/InstrM[1]} {wallypipelinedsoc/hart/InstrM[2]} {wallypipelinedsoc/hart/InstrM[3]} {wallypipelinedsoc/hart/InstrM[4]} {wallypipelinedsoc/hart/InstrM[5]} {wallypipelinedsoc/hart/InstrM[6]} {wallypipelinedsoc/hart/InstrM[7]} {wallypipelinedsoc/hart/InstrM[8]} {wallypipelinedsoc/hart/InstrM[9]} {wallypipelinedsoc/hart/InstrM[10]} {wallypipelinedsoc/hart/InstrM[11]} {wallypipelinedsoc/hart/InstrM[12]} {wallypipelinedsoc/hart/InstrM[13]} {wallypipelinedsoc/hart/InstrM[14]} {wallypipelinedsoc/hart/InstrM[15]} {wallypipelinedsoc/hart/InstrM[16]} {wallypipelinedsoc/hart/InstrM[17]} {wallypipelinedsoc/hart/InstrM[18]} {wallypipelinedsoc/hart/InstrM[19]} {wallypipelinedsoc/hart/InstrM[20]} {wallypipelinedsoc/hart/InstrM[21]} {wallypipelinedsoc/hart/InstrM[22]} {wallypipelinedsoc/hart/InstrM[23]} {wallypipelinedsoc/hart/InstrM[24]} {wallypipelinedsoc/hart/InstrM[25]} {wallypipelinedsoc/hart/InstrM[26]} {wallypipelinedsoc/hart/InstrM[27]} {wallypipelinedsoc/hart/InstrM[28]} {wallypipelinedsoc/hart/InstrM[29]} {wallypipelinedsoc/hart/InstrM[30]} {wallypipelinedsoc/hart/InstrM[31]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe10]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
+connect_debug_port u_ila_0/probe10 [get_nets [list {wallypipelinedsoc/hart/MemRWM[0]} {wallypipelinedsoc/hart/MemRWM[1]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe11]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
+connect_debug_port u_ila_0/probe11 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIE_REGW[11]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe12]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
+connect_debug_port u_ila_0/probe12 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrm/MEPC_REGW[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe13]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
+connect_debug_port u_ila_0/probe13 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrm/MIP_REGW[11]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 5 [get_debug_ports u_ila_0/probe14]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
+connect_debug_port u_ila_0/probe14 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[3]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/r_curr_state[4]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe15]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
+connect_debug_port u_ila_0/probe15 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_ERROR_CODE_Q[2]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe16]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
+connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_Q[3]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe17]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
+connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState[31]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe18]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
+connect_debug_port u_ila_0/probe18 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SEPC_REGW[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe19]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
+connect_debug_port u_ila_0/probe19 [get_nets [list {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[0]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[1]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[2]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[3]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[4]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[5]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[6]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[7]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[8]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[9]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[10]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[11]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[12]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[13]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[14]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[15]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[16]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[17]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[18]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[19]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[20]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[21]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[22]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[23]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[24]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[25]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[26]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[27]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[28]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[29]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[30]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[31]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[32]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[33]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[34]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[35]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[36]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[37]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[38]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[39]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[40]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[41]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[42]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[43]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[44]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[45]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[46]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[47]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[48]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[49]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[50]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[51]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[52]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[53]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[54]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[55]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[56]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[57]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[58]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[59]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[60]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[61]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[62]} {wallypipelinedsoc/hart/priv/csr/csrs/SCAUSE_REGW[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe20]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
+connect_debug_port u_ila_0/probe20 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/SEPC_REGW[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe21]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
+connect_debug_port u_ila_0/probe21 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIP_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIP_REGW[9]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe22]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
+connect_debug_port u_ila_0/probe22 [get_nets [list {wallypipelinedsoc/hart/priv/trap/SIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/SIE_REGW[9]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 63 [get_debug_ports u_ila_0/probe23]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
+connect_debug_port u_ila_0/probe23 [get_nets [list {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/STVEC_REGW[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe24]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
+connect_debug_port u_ila_0/probe24 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/r_curr_state[3]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe25]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
+connect_debug_port u_ila_0/probe25 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/i_SD_DAT[3]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 12 [get_debug_ports u_ila_0/probe26]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
+connect_debug_port u_ila_0/probe26 [get_nets [list {wallypipelinedsoc/hart/priv/trap/PendingIntsM[0]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[1]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[2]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[3]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[4]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[5]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[6]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[7]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[8]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[9]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[10]} {wallypipelinedsoc/hart/priv/trap/PendingIntsM[11]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe27]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
+connect_debug_port u_ila_0/probe27 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[0]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[2]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[4]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[6]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[8]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[10]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[11]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[12]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[13]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[14]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[15]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[16]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[17]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[18]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[19]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[20]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[21]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[22]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[23]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[24]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[25]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[26]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[27]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[28]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[29]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[30]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[31]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[32]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[33]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[34]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[35]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[36]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[37]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[38]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[39]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[40]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[41]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[42]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[43]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[44]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[45]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[46]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[47]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[48]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[49]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[50]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[51]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[52]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[53]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[54]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[55]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[56]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[57]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[58]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[59]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[60]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[61]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[62]} {wallypipelinedsoc/hart/priv/trap/MEPC_REGW[63]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 6 [get_debug_ports u_ila_0/probe28]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
+connect_debug_port u_ila_0/probe28 [get_nets [list {wallypipelinedsoc/hart/priv/trap/MIE_REGW[1]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[3]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[5]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[7]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[9]} {wallypipelinedsoc/hart/priv/trap/MIE_REGW[11]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe29]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
+connect_debug_port u_ila_0/probe29 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_IC_OUT[3]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe30]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
+connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[0]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[1]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[2]} {wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/r_curr_state[3]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe31]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
+connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[0]} {wallypipelinedsoc/hart/lsu/dcache/DCtoAHBSizeM[1]} ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe32]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
+connect_debug_port u_ila_0/probe32 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBAck ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe33]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
+connect_debug_port u_ila_0/probe33 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBRead ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe34]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
+connect_debug_port u_ila_0/probe34 [get_nets [list wallypipelinedsoc/hart/lsu/dcache/AHBWrite ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe35]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
+connect_debug_port u_ila_0/probe35 [get_nets [list wallypipelinedsoc/hart/priv/trap/BreakpointFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe36]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
+connect_debug_port u_ila_0/probe36 [get_nets [list wallypipelinedsoc/uncore/uart.uart/DTRb ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe37]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
+connect_debug_port u_ila_0/probe37 [get_nets [list wallypipelinedsoc/hart/priv/trap/EcallFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe38]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
+connect_debug_port u_ila_0/probe38 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DAT0_Q ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe39]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
+connect_debug_port u_ila_0/probe39 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_dat_fsm/i_DATA_CRC16_GOOD ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe40]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
+connect_debug_port u_ila_0/probe40 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_CRC16 ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe41]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
+connect_debug_port u_ila_0/probe41 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/i_ERROR_DAT_TIMES_OUT ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe42]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
+connect_debug_port u_ila_0/probe42 [get_nets [list wallypipelinedsoc/hart/priv/trap/IllegalInstrFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe43]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
+connect_debug_port u_ila_0/probe43 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrAccessFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe44]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
+connect_debug_port u_ila_0/probe44 [get_nets [list wallypipelinedsoc/hart/priv/trap/InstrPageFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe45]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
+connect_debug_port u_ila_0/probe45 [get_nets [list wallypipelinedsoc/hart/InstrValidM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe46]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
+connect_debug_port u_ila_0/probe46 [get_nets [list wallypipelinedsoc/uncore/uart.uart/INTR ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe47]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
+connect_debug_port u_ila_0/probe47 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadAccessFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe48]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
+connect_debug_port u_ila_0/probe48 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadMisalignedFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe49]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
+connect_debug_port u_ila_0/probe49 [get_nets [list wallypipelinedsoc/hart/priv/trap/LoadPageFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe50]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
+connect_debug_port u_ila_0/probe50 [get_nets [list wallypipelinedsoc/hart/priv/trap/mretM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe51]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
+connect_debug_port u_ila_0/probe51 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_clk_fsm/o_G_CLK_SD_EN ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe52]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe52]
+connect_debug_port u_ila_0/probe52 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CLK ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe53]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe53]
+connect_debug_port u_ila_0/probe53 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe54]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe54]
+connect_debug_port u_ila_0/probe54 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/o_SD_CMD_OE ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe55]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe55]
+connect_debug_port u_ila_0/probe55 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/my_sd_cmd_fsm/o_SD_CMD_OE ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe56]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe56]
+connect_debug_port u_ila_0/probe56 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT1b ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe57]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe57]
+connect_debug_port u_ila_0/probe57 [get_nets [list wallypipelinedsoc/uncore/uart.uart/OUT2b ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe58]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe58]
+connect_debug_port u_ila_0/probe58 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe59]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe59]
+connect_debug_port u_ila_0/probe59 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RTSb ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe60]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe60]
+connect_debug_port u_ila_0/probe60 [get_nets [list wallypipelinedsoc/uncore/uart.uart/RXRDYb ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe61]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe61]
+connect_debug_port u_ila_0/probe61 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SIN ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe62]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe62]
+connect_debug_port u_ila_0/probe62 [get_nets [list wallypipelinedsoc/uncore/uart.uart/SOUT ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe63]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe63]
+connect_debug_port u_ila_0/probe63 [get_nets [list wallypipelinedsoc/hart/priv/trap/sretM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe64]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe64]
+connect_debug_port u_ila_0/probe64 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreAccessFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe65]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe65]
+connect_debug_port u_ila_0/probe65 [get_nets [list wallypipelinedsoc/hart/priv/trap/StoreMisalignedFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe66]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe66]
+connect_debug_port u_ila_0/probe66 [get_nets [list wallypipelinedsoc/hart/priv/trap/StorePageFaultM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe67]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe67]
+connect_debug_port u_ila_0/probe67 [get_nets [list wallypipelinedsoc/hart/TrapM ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe68]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe68]
+connect_debug_port u_ila_0/probe68 [get_nets [list wallypipelinedsoc/uncore/uart.uart/TXRDYb ]]
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe69]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe69]
+connect_debug_port u_ila_0/probe69 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_EN ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe70]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe70]
+connect_debug_port u_ila_0/probe70 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_RST ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe71]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe71]
+connect_debug_port u_ila_0/probe71 [get_nets [list wallypipelinedsoc/uncore/sdc.SDC/sd_top/w_IC_UP_DOWN ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe72]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe72]
+connect_debug_port u_ila_0/probe72 [get_nets [list wallypipelinedsoc/hart/hzu/BPPredWrongE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe73]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe73]
+connect_debug_port u_ila_0/probe73 [get_nets [list wallypipelinedsoc/hart/hzu/CSRWritePendingDEM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe74]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe74]
+connect_debug_port u_ila_0/probe74 [get_nets [list wallypipelinedsoc/hart/hzu/RetM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe75]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe75]
+connect_debug_port u_ila_0/probe75 [get_nets [list wallypipelinedsoc/hart/hzu/TrapM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe76]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe76]
+connect_debug_port u_ila_0/probe76 [get_nets [list wallypipelinedsoc/hart/hzu/LoadStallD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe77]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe77]
+connect_debug_port u_ila_0/probe77 [get_nets [list wallypipelinedsoc/hart/hzu/StoreStallD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe78]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe78]
+connect_debug_port u_ila_0/probe78 [get_nets [list wallypipelinedsoc/hart/hzu/MulDivStallD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe79]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe79]
+connect_debug_port u_ila_0/probe79 [get_nets [list wallypipelinedsoc/hart/hzu/CSRRdStallD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe80]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe80]
+connect_debug_port u_ila_0/probe80 [get_nets [list wallypipelinedsoc/hart/hzu/LSUStall ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe81]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe81]
+connect_debug_port u_ila_0/probe81 [get_nets [list wallypipelinedsoc/hart/hzu/ICacheStallF ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe82]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe82]
+connect_debug_port u_ila_0/probe82 [get_nets [list wallypipelinedsoc/hart/hzu/FPUStallD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe83]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe83]
+connect_debug_port u_ila_0/probe83 [get_nets [list wallypipelinedsoc/hart/hzu/FStallD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe84]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe84]
+connect_debug_port u_ila_0/probe84 [get_nets [list wallypipelinedsoc/hart/hzu/DivBusyE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe85]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe85]
+connect_debug_port u_ila_0/probe85 [get_nets [list wallypipelinedsoc/hart/hzu/FDivBusyE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe86]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe86]
+connect_debug_port u_ila_0/probe86 [get_nets [list wallypipelinedsoc/hart/hzu/EcallFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe87]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe87]
+connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/hart/hzu/BreakpointFaultM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe88]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
+connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/hart/hzu/InvalidateICacheMp ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe89]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe89]
+connect_debug_port u_ila_0/probe89 [get_nets [list wallypipelinedsoc/hart/hzu/StallF ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe90]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe90]
+connect_debug_port u_ila_0/probe90 [get_nets [list wallypipelinedsoc/hart/hzu/StallD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe91]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe91]
+connect_debug_port u_ila_0/probe91 [get_nets [list wallypipelinedsoc/hart/hzu/StallE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe92]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
+connect_debug_port u_ila_0/probe92 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe93]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
+connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/hart/hzu/StallW ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe94]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe94]
+connect_debug_port u_ila_0/probe94 [get_nets [list wallypipelinedsoc/hart/hzu/FlushF ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe95]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe95]
+connect_debug_port u_ila_0/probe95 [get_nets [list wallypipelinedsoc/hart/hzu/FlushD ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe96]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe96]
+connect_debug_port u_ila_0/probe96 [get_nets [list wallypipelinedsoc/hart/hzu/FlushE ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe97]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe97]
+connect_debug_port u_ila_0/probe97 [get_nets [list wallypipelinedsoc/hart/hzu/FlushM ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe98]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe98]
+connect_debug_port u_ila_0/probe98 [get_nets [list wallypipelinedsoc/hart/hzu/FlushW ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 24 [get_debug_ports u_ila_0/probe99]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
+connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[23]}]]

From 68745d40f2d80a83ff188c8422f05a86e5b96710 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 12 Dec 2021 17:21:44 -0600
Subject: [PATCH 21/95] Modified FPGA to add additional signals to ILA. 
 Created advanced trigger for ILA using vivado's tsm language.

---
 fpga/constraints/debug2.xdc            |  6 +++--
 fpga/debug_notes.org                   | 16 ++++++++++++
 fpga/generator/Makefile                |  2 +-
 fpga/trigger_issues.tsm                | 36 ++++++++++++++++++++++++++
 wally-pipelined/src/cache/icachefsm.sv |  2 +-
 5 files changed, 58 insertions(+), 4 deletions(-)
 create mode 100644 fpga/debug_notes.org
 create mode 100644 fpga/trigger_issues.tsm

diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 9cb695b9..917c2b6d 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -389,7 +389,7 @@ connect_debug_port u_ila_0/probe87 [get_nets [list wallypipelinedsoc/hart/hzu/Br
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe88]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe88]
-connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/hart/hzu/InvalidateICacheMp ]]
+connect_debug_port u_ila_0/probe88 [get_nets [list wallypipelinedsoc/hart/hzu/InvalidateICacheM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe89]
@@ -411,10 +411,11 @@ set_property port_width 1 [get_debug_ports u_ila_0/probe92]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe92]
 connect_debug_port u_ila_0/probe92 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]]
 
+# StallW is StallM.  trying to connect to StallW causes issues.
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe93]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe93]
-connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/hart/hzu/StallW ]]
+connect_debug_port u_ila_0/probe93 [get_nets [list wallypipelinedsoc/hart/hzu/StallM ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe94]
@@ -445,3 +446,4 @@ create_debug_port u_ila_0 probe
 set_property port_width 24 [get_debug_ports u_ila_0/probe99]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
 connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[23]}]]
+
diff --git a/fpga/debug_notes.org b/fpga/debug_notes.org
new file mode 100644
index 00000000..84952d8c
--- /dev/null
+++ b/fpga/debug_notes.org
@@ -0,0 +1,16 @@
+* December 12, 2021
+Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
+InstrM = f884_3803
+PCM = ffff_ffff_8030_8004
+
+Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
+InstrM = 0207_ba03
+PCM = ffff_ffff_8034_89fe
+
+Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
+InstrM = 0016_c383
+PCM = ffff_ffff_8030_7504
+
+Indefinite lockup in the dcache with STATE_PTW_FAULT_CPU_BUSY
+InstrM = 0006_a703
+PCM = ffff_ffff_8028_fa02
diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile
index c65e522f..bf9402e1 100644
--- a/fpga/generator/Makefile
+++ b/fpga/generator/Makefile
@@ -3,7 +3,7 @@ dst := IP
 all: FPGA
 
 FPGA: IP
-	vivado -mode batch -source wally.tcl | tee wally.log
+	vivado -mode batch -source wally.tcl 2>&1 | tee wally.log
 
 IP: $(dst)/xlnx_proc_sys_reset.log \
 	$(dst)/xlnx_ddr4.log \
diff --git a/fpga/trigger_issues.tsm b/fpga/trigger_issues.tsm
new file mode 100644
index 00000000..421c0a7a
--- /dev/null
+++ b/fpga/trigger_issues.tsm
@@ -0,0 +1,36 @@
+##################################################
+#
+# For info on creating trigger state machines:
+#   1) In the main Vivado menu bar, select
+#      Window > Language Templates
+#   2) In the Templates window, select
+#      Debug > Trigger State Machine
+#   3) Refer to the entry 'Info' for an overview
+#      of the trigger state machine language.
+#
+# More information can be found in this document:
+#
+#   Vivado Design Suite User Guide: Programming
+#   and Debugging (UG908)
+#
+##################################################
+state state_reset:
+    if(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then
+        reset_counter $counter0;
+        goto state_begin_count;
+    else
+        goto state_reset;
+    endif
+    
+state state_begin_count:
+    if($counter0 == 16'h0064) then
+        goto state_trigger;
+    elseif(wallypipelinedsoc/hart/lsu/dcache/dcachefsm/CurrState == 32'h00000015) then
+        increment_counter $counter0;
+        goto state_begin_count;
+    else
+        goto state_reset;
+    endif
+    
+state state_trigger:
+    trigger;
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index fa0268bb..433328ab 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -114,7 +114,7 @@ module icachefsm
 		STATE_CPU_BUSY_SPILL		
 		} statetype;
   
-  statetype CurrState, NextState;
+  (* mark_debug = "true" *)  statetype CurrState, NextState;
   logic 		       PreCntEn;
 
   // the FSM is always runing, do not stall.

From f758a53247872bcf8bb1882f99d933fb738b90f4 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 12 Dec 2021 17:31:39 -0600
Subject: [PATCH 22/95] Revert "Priviledged .* removed"

This reverts commit a95efea0b34f219c420e9ff7f6b613a0869ba791.
---
 wally-pipelined/src/privileged/privileged.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 3cb7a183..512364e6 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -22,7 +22,7 @@
 // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
 // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
-// SOFTWARE.
+ SOFTWARE.
 ///////////////////////////////////////////
 
 `include "wally-config.vh"

From 395766219bf3cc426d299b14caae7268bb39b4f9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 12 Dec 2021 17:31:57 -0600
Subject: [PATCH 23/95] Revert "Privilige .*s removed"

This reverts commit 82bab8e90e485c687a8fb7679a73b9c16160e14b.
---
 addins/riscv-arch-test                       |  2 +-
 wally-pipelined/src/privileged/privileged.sv | 69 +++-----------------
 2 files changed, 11 insertions(+), 60 deletions(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 84d04381..be67c99b 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 512364e6..a6c3f2d8 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -21,8 +21,7 @@
 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
 // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
 // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- SOFTWARE.
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -85,7 +84,7 @@ module privileged (
 
   logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
   logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW;
-  //  logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
+//  logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
   logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
 
   logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
@@ -112,8 +111,8 @@ module privileged (
   ///////////////////////////////////////////
 
   // get bits of DELEG registers based on CAUSE
-  //  assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
-  //  assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
+//  assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
+//  assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
   assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
   assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : SEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; // depricated
   
@@ -144,44 +143,15 @@ module privileged (
 
   ///////////////////////////////////////////
   // decode privileged instructions
-
-
   ///////////////////////////////////////////
-  
-  privdec pmd(.InstrM(InstrM[31:20]), 
-              .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
-              .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, 
-              .uretM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
+
+  privdec pmd(.InstrM(InstrM[31:20]), .*);
 
   ///////////////////////////////////////////
   // Control and Status Registers
   ///////////////////////////////////////////
-  
-  csr csr(.clk,. reset,
-          .FlushE, .FlushM, .FlushW,
-          .StallE, .StallM, .StallW,
-          .InstrM, .PCM, .SrcAM,
-          .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM,
-          .TimerIntM, .ExtIntM, .SwIntM,
-          .MTIME_CLINT, .MTIMECMP_CLINT,
-          .InstrValidM, .FRegWriteM, .LoadStallD,
-          .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, 
-          .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess,
-          .NextPrivilegeModeM, .PrivilegeModeW,
-          .CauseM, .NextFaultMtvalM, .STATUS_MPP,
-          .STATUS_SPP, .STATUS_TSR,
-          .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
-          .MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, 
-          .SATP_REGW,
-          .MIP_REGW, .MIE_REGW, .SIP_REGW, S.IE_REGW,
-          .STATUS_MIE, .STATUS_SIE,
-          .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW,
-          .PMPCFG_ARRAY_REGW,
-          .PMPADDR_ARRAY_REGW,
-          .SetFflagsM,
-          .FRM_REGW, 
-          .CSRReadValW,
-          .IllegalCSRAccessM);
+
+  csr csr(.*);
 
   ///////////////////////////////////////////
   // Extract exceptions by name and handle them 
@@ -218,28 +188,9 @@ module privileged (
   flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM,
                   {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
                   {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
-  // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
-  
-  trap trap(.clk, .reset,
-            .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
-            .BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
-            .LoadAccessFaultM, .StoreAccessFaultM, .EcallFaultM, .InstrPageFaultM,
-            .LoadPageFaultM, .StorePageFaultM,
-            .mretM, .sretM, .uretM,
-            .PrivilegeModeW, .NextPrivilegeModeM
-            .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
-            .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
-            .STATUS_MIE, .STATUS_SIE
-            .PCM,
-            .InstrMisalignedAdrM, .MemAdrM, 
-            .InstrM,
-            .InstrValidM, .CommittedM,
-            .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
-            .InterruptM,
-            .ExceptionM,
-            .PendingInterruptM,
-            .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);
+  // *** it should be possible to compbine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
 
+  trap trap(.*);
 
 endmodule
 

From 98420cb988ecbe7b52a2e05784cec5c81d1be2d0 Mon Sep 17 00:00:00 2001
From: Kevin <kevin12kim27@gmail.com>
Date: Sun, 12 Dec 2021 17:53:26 -0800
Subject: [PATCH 24/95]  dot stars conversions on the rest of the testbenches

---
 .../testbench/testbench-coremark.sv           |  5 +++-
 .../testbench/testbench-coremark_bare.sv      | 27 +++----------------
 wally-pipelined/testbench/testbench-fpga.sv   | 11 ++++----
 .../testbench/testbench-privileged.sv         |  5 +++-
 wally-pipelined/testbench/testbench.sv        |  5 +++-
 5 files changed, 22 insertions(+), 31 deletions(-)

diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv
index 2feccab5..8f6683d3 100644
--- a/wally-pipelined/testbench/testbench-coremark.sv
+++ b/wally-pipelined/testbench/testbench-coremark.sv
@@ -64,7 +64,10 @@ module testbench();
   assign HREADYEXT = 1;
   assign HRESPEXT = 0;
   assign HRDATAEXT = 0;
-  wallypipelinedsoc dut(.*); 
+  wallypipelinedsoc dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
   // Track names of instructions
   logic [31:0] InstrW;
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW, dut.hart.ifu.InstrM, InstrW);
diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index 5d5b0cc6..33378cc3 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -72,29 +72,10 @@ module testbench();
   assign HREADYEXT = 1;
   assign HRESPEXT = 0;
   assign HRDATAEXT = 0;
-  wallypipelinedsoc dut(.clk, .reset_ext, 
-  .HRDATAEXT,
-  .HREADYEXT, .HRESPEXT,
-  .HSELEXT,
-  .HCLK, .HRESETn,
-  .HADDR,
-  .HWDATA,
-  .HWRITE,
-  .HSIZE,
-  .HBURST,
-  .HPROT,
-  .HTRANS,
-  .HMASTLOCK,
-  .HREADY,
-  .GPIOPinsIn,
-  .GPIOPinsOut, .GPIOPinsEn,
-  .UARTSin,
-  .UARTSout,
-  .SDCCmdIn,
-  .SDCCmdOut,
-  .SDCCmdOE,			  
-  .SDCDatIn,
-  .SDCCLK); 
+  wallypipelinedsoc dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
 
   logic [31:0] InstrW;
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);
diff --git a/wally-pipelined/testbench/testbench-fpga.sv b/wally-pipelined/testbench/testbench-fpga.sv
index 1fdfdbad..b10eb8fd 100644
--- a/wally-pipelined/testbench/testbench-fpga.sv
+++ b/wally-pipelined/testbench/testbench-fpga.sv
@@ -596,13 +596,14 @@ string tests32f[] = '{
   assign UARTSin = 1;
  
   dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) 
-  dtim (.*, .HSELTim(HSELEXT),
-	.HREADTim(HRDATAEXT),
-	.HREADYTim(HREADYEXT),
-	.HRESPTim(HRESPEXT));
+  dtim (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELTim(HSELEXT), 
+        .HREADTim(HRDATAEXT), .HREADYTim(HREADYEXT), .HRESPTim(HRESPEXT));
  
 
-  wallypipelinedsocwrapper dut(.*); 
+  wallypipelinedsocwrapper dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
 
   // Track names of instructions
   instrTrackerTB it(clk, reset, dut.wallypipelinedsoc.hart.ieu.dp.FlushE,
diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv
index 335223b2..f3f68e0c 100644
--- a/wally-pipelined/testbench/testbench-privileged.sv
+++ b/wally-pipelined/testbench/testbench-privileged.sv
@@ -91,7 +91,10 @@ module testbench();
   assign HRESPEXT = 0;
   assign HRDATAEXT = 0;
 
-  wallypipelinedsoc dut(.*); 
+  wallypipelinedsoc dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
   flopenr  #(32)   InstrWReg(clk, reset, ~dut.hart.ieu.dp.StallW,  dut.hart.ifu.InstrM, InstrW);
   // Track names of instructions
   instrTrackerTBPriv it(clk, reset, dut.hart.ieu.dp.FlushE,
diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv
index 14a7b8d5..703b8aae 100644
--- a/wally-pipelined/testbench/testbench.sv
+++ b/wally-pipelined/testbench/testbench.sv
@@ -146,7 +146,10 @@ logic [3:0] dummy;
   assign HRESPEXT = 0;
   assign HRDATAEXT = 0;
 
-  wallypipelinedsoc dut(.*); 
+  wallypipelinedsoc dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+                        .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
+                        .HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
+                        .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
 
   // Track names of instructions
   instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,

From a365e86197a21d0e0748274b4e1a62fb1fd9b0b5 Mon Sep 17 00:00:00 2001
From: kwan <kwan@tera.eng.hmc.edu>
Date: Mon, 13 Dec 2021 00:22:01 -0800
Subject: [PATCH 25/95] priviledge .* fixed, passed local regression

---
 wally-pipelined/src/privileged/privileged.sv | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 3cb7a183..59c0f90d 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -147,7 +147,7 @@ module privileged (
 
 
   ///////////////////////////////////////////
-  
+  //privdec pmd(.InstrM(InstrM[31:20]),.*);
   privdec pmd(.InstrM(InstrM[31:20]), 
               .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
               .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, 
@@ -156,8 +156,8 @@ module privileged (
   ///////////////////////////////////////////
   // Control and Status Registers
   ///////////////////////////////////////////
-  
-  csr csr(.clk,. reset,
+  //csr csr(.*);
+  csr csr(.clk, .reset,
           .FlushE, .FlushM, .FlushW,
           .StallE, .StallM, .StallW,
           .InstrM, .PCM, .SrcAM,
@@ -171,9 +171,9 @@ module privileged (
           .CauseM, .NextFaultMtvalM, .STATUS_MPP,
           .STATUS_SPP, .STATUS_TSR,
           .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
-          .MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW, 
+          .MEDELEG_REGW, .MIDELEG_REGW, .SEDELEG_REGW, .SIDELEG_REGW, 
           .SATP_REGW,
-          .MIP_REGW, .MIE_REGW, .SIP_REGW, S.IE_REGW,
+          .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
           .STATUS_MIE, .STATUS_SIE,
           .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW,
           .PMPCFG_ARRAY_REGW,
@@ -219,17 +219,17 @@ module privileged (
                   {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
                   {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
   // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
-  
+  //trap trap(.*);
   trap trap(.clk, .reset,
             .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
             .BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
             .LoadAccessFaultM, .StoreAccessFaultM, .EcallFaultM, .InstrPageFaultM,
             .LoadPageFaultM, .StorePageFaultM,
             .mretM, .sretM, .uretM,
-            .PrivilegeModeW, .NextPrivilegeModeM
+            .PrivilegeModeW, .NextPrivilegeModeM,
             .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
             .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
-            .STATUS_MIE, .STATUS_SIE
+            .STATUS_MIE, .STATUS_SIE,
             .PCM,
             .InstrMisalignedAdrM, .MemAdrM, 
             .InstrM,

From 8f79a12cbbf19a1f5b6c0d355f04442b438c95d0 Mon Sep 17 00:00:00 2001
From: kwan <kwan@tera.eng.hmc.edu>
Date: Mon, 13 Dec 2021 00:34:43 -0800
Subject: [PATCH 26/95] priviledge .* removed, passed regression

---
 addins/riscv-arch-test                       |  2 +-
 wally-pipelined/src/privileged/privileged.sv | 71 ++++++++++++++++----
 2 files changed, 60 insertions(+), 13 deletions(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index be67c99b..84d04381 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
+Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 8dbd53a3..c5bc8a45 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -21,7 +21,8 @@
 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
 // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
 // BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+// SOFTWARE.
 ///////////////////////////////////////////
 
 `include "wally-config.vh"
@@ -84,7 +85,7 @@ module privileged (
 
   logic [`XLEN-1:0] CauseM, NextFaultMtvalM;
   logic [`XLEN-1:0] MEPC_REGW, SEPC_REGW, UEPC_REGW, UTVEC_REGW, STVEC_REGW, MTVEC_REGW;
-//  logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
+  //  logic [11:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
   logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW, SEDELEG_REGW, SIDELEG_REGW;
 
   logic uretM, sretM, mretM, ecallM, ebreakM, wfiM, sfencevmaM;
@@ -111,8 +112,8 @@ module privileged (
   ///////////////////////////////////////////
 
   // get bits of DELEG registers based on CAUSE
-//  assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
-//  assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
+  //  assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[3:0]];
+  //  assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[3:0]] : SEDELEG_REGW[CauseM[3:0]]; // depricated
   assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
   assign sd = CauseM[`XLEN-1] ? SIDELEG_REGW[CauseM[`LOG_XLEN-1:0]] : SEDELEG_REGW[CauseM[`LOG_XLEN-1:0]]; // depricated
   
@@ -143,15 +144,44 @@ module privileged (
 
   ///////////////////////////////////////////
   // decode privileged instructions
-  ///////////////////////////////////////////
 
-  privdec pmd(.InstrM(InstrM[31:20]), .*);
+
+  ///////////////////////////////////////////
+  //privdec pmd(.InstrM(InstrM[31:20]),.*);
+  privdec pmd(.InstrM(InstrM[31:20]), 
+              .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
+              .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, 
+              .uretM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
 
   ///////////////////////////////////////////
   // Control and Status Registers
   ///////////////////////////////////////////
-
-  csr csr(.*);
+  //csr csr(.*);
+  csr csr(.clk, .reset,
+          .FlushE, .FlushM, .FlushW,
+          .StallE, .StallM, .StallW,
+          .InstrM, .PCM, .SrcAM,
+          .CSRReadM, .CSRWriteM, .TrapM, .MTrapM, .STrapM, .UTrapM, .mretM, .sretM, .uretM,
+          .TimerIntM, .ExtIntM, .SwIntM,
+          .MTIME_CLINT, .MTIMECMP_CLINT,
+          .InstrValidM, .FRegWriteM, .LoadStallD,
+          .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, 
+          .BPPredClassNonCFIWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess,
+          .NextPrivilegeModeM, .PrivilegeModeW,
+          .CauseM, .NextFaultMtvalM, .STATUS_MPP,
+          .STATUS_SPP, .STATUS_TSR,
+          .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
+          .MEDELEG_REGW, .MIDELEG_REGW, .SEDELEG_REGW, .SIDELEG_REGW, 
+          .SATP_REGW,
+          .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
+          .STATUS_MIE, .STATUS_SIE,
+          .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW,
+          .PMPCFG_ARRAY_REGW,
+          .PMPADDR_ARRAY_REGW,
+          .SetFflagsM,
+          .FRM_REGW, 
+          .CSRReadValW,
+          .IllegalCSRAccessM);
 
   ///////////////////////////////////////////
   // Extract exceptions by name and handle them 
@@ -188,9 +218,28 @@ module privileged (
   flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM,
                   {IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
                   {IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
-  // *** it should be possible to compbine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
+  // *** it should be possible to combine some of these faults earlier to reduce module boundary crossings and save flops dh 5 july 2021
+  //trap trap(.*);
+  trap trap(.clk, .reset,
+            .InstrMisalignedFaultM, .InstrAccessFaultM, .IllegalInstrFaultM,
+            .BreakpointFaultM, .LoadMisalignedFaultM, .StoreMisalignedFaultM,
+            .LoadAccessFaultM, .StoreAccessFaultM, .EcallFaultM, .InstrPageFaultM,
+            .LoadPageFaultM, .StorePageFaultM,
+            .mretM, .sretM, .uretM,
+            .PrivilegeModeW, .NextPrivilegeModeM,
+            .MEPC_REGW, .SEPC_REGW, .UEPC_REGW, .UTVEC_REGW, .STVEC_REGW, .MTVEC_REGW,
+            .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
+            .STATUS_MIE, .STATUS_SIE,
+            .PCM,
+            .InstrMisalignedAdrM, .MemAdrM, 
+            .InstrM,
+            .InstrValidM, .CommittedM,
+            .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
+            .InterruptM,
+            .ExceptionM,
+            .PendingInterruptM,
+            .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);
 
-  trap trap(.*);
 
 endmodule
 
@@ -198,5 +247,3 @@ endmodule
 
 
 
-
-

From 2039752740a6ed3fe09d4e070f0af9f9edbe2f4c Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 13 Dec 2021 07:57:38 -0800
Subject: [PATCH 27/95] Simplified ALU and source multiplexers pass tests

---
 wally-pipelined/regression/sim-wally        | 2 +-
 wally-pipelined/regression/sim-wally-batch  | 2 +-
 wally-pipelined/src/ebu/amoalu.sv           | 2 ++
 wally-pipelined/src/ieu/comparator.sv       | 2 +-
 wally-pipelined/src/ieu/controller.sv       | 6 +++---
 wally-pipelined/testbench/common/sdModel.sv | 4 ++--
 wally-pipelined/testbench/tests.vh          | 1 +
 7 files changed, 11 insertions(+), 8 deletions(-)

diff --git a/wally-pipelined/regression/sim-wally b/wally-pipelined/regression/sim-wally
index 0c118256..d3071bd1 100755
--- a/wally-pipelined/regression/sim-wally
+++ b/wally-pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv32g arch32i"
+vsim -do "do wally-pipelined.do rv64g arch64i"
 
diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch
index 4b627b76..ff944450 100755
--- a/wally-pipelined/regression/sim-wally-batch
+++ b/wally-pipelined/regression/sim-wally-batch
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv32g arch32f
+do wally-pipelined-batch.do rv64g arch64i
 !
diff --git a/wally-pipelined/src/ebu/amoalu.sv b/wally-pipelined/src/ebu/amoalu.sv
index 45f41966..2700dbc3 100644
--- a/wally-pipelined/src/ebu/amoalu.sv
+++ b/wally-pipelined/src/ebu/amoalu.sv
@@ -25,6 +25,8 @@
 
 `include "wally-config.vh"
 
+// *** this should probably be moved into the LSU because it is instantiated in the D$
+
 module amoalu (
   input  logic [`XLEN-1:0] srca, srcb,
   input  logic [6:0]       funct,
diff --git a/wally-pipelined/src/ieu/comparator.sv b/wally-pipelined/src/ieu/comparator.sv
index 8178d338..14117274 100644
--- a/wally-pipelined/src/ieu/comparator.sv
+++ b/wally-pipelined/src/ieu/comparator.sv
@@ -37,7 +37,7 @@ module comparator #(parameter WIDTH=32) (
 
   // subtraction
   assign bbar = ~b;
-  assign {carry, diff} = a + bbar;
+  assign {carry, diff} = a + bbar + 1;
 
   // condition code flags based on add/subtract output
   assign zero = (diff == 0);
diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 90ab5af6..02e380a4 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -145,9 +145,9 @@ module controller(
                     else
                       ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
         //7'b1010011:   ControlsD = `CTRLW'b0_000_00_00_101_0_00_0_0_0_0_0_0_0_00_1; // FP
-        7'b1100011:   ControlsD = `CTRLW'b0_010_00_00_000_1_0_0_0_0_0_0_0_0_00_0; // beq
-        7'b1100111:   ControlsD = `CTRLW'b1_000_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
-        7'b1101111:   ControlsD = `CTRLW'b1_011_00_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
+        7'b1100011:   ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
+        7'b1100111:   ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
+        7'b1101111:   ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
         7'b1110011: if (Funct3D == 3'b000)
                       ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
                     else
diff --git a/wally-pipelined/testbench/common/sdModel.sv b/wally-pipelined/testbench/common/sdModel.sv
index a6c36f1f..741d741e 100644
--- a/wally-pipelined/testbench/common/sdModel.sv
+++ b/wally-pipelined/testbench/common/sdModel.sv
@@ -118,6 +118,8 @@ module    sdModel
    reg [3:0] 	  crcDat_in; 
    wire [15:0] 	  crcDat_out [3:0];
 
+   integer sdModel_file_desc;
+
    genvar 	  i;
    generate
       for(i=0; i<4; i=i+1) begin:CRC_16_gen
@@ -1050,8 +1052,6 @@ module    sdModel
       endcase // case (dataState)
    end // always @ (negedge sdClk)
 
-   integer sdModel_file_desc;
-
    initial
      begin
 	sdModel_file_desc = $fopen("sd_model.log");
diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh
index a12f9699..ec3a5315 100644
--- a/wally-pipelined/testbench/tests.vh
+++ b/wally-pipelined/testbench/tests.vh
@@ -586,6 +586,7 @@ string imperas32f[] = '{
 
   string arch64i[] = '{
     `RISCVARCHTEST,
+    "rv64i_m/I/beq-01", "47010",
     "rv64i_m/I/add-01", "9010",
     "rv64i_m/I/addi-01", "6010",
     "rv64i_m/I/addiw-01", "6010",

From 4d6d72a082aacbe0a92485d366febb1da7afd504 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Dec 2021 15:47:20 -0600
Subject: [PATCH 28/95] Fixed some typos in the dcache ptw interaction
 documentation.

---
 .../src/cache/dcache_ptw_interaction_README.txt           | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/cache/dcache_ptw_interaction_README.txt b/wally-pipelined/src/cache/dcache_ptw_interaction_README.txt
index cc7a96cc..47e2af5d 100644
--- a/wally-pipelined/src/cache/dcache_ptw_interaction_README.txt
+++ b/wally-pipelined/src/cache/dcache_ptw_interaction_README.txt
@@ -1,8 +1,8 @@
 Intractions betwen the dcache and hardware page table walker are complex.
 In particular the complications arise when a fault occurs concurrently with a memory operation.
 
-At the begining of very memory operation there are 8 combinations of three signals;
-ITBL miss, DTLB miss, and memory operation.  By looking at each combination we
+At the begining of every memory operation there are 8 combinations of three signals;
+ITBL miss, DTLB miss, and a memory operation.  By looking at each combination we
 can understand exactly the correct sequence of operations and if the operation
 should continue.
 
@@ -47,7 +47,7 @@ Dcache handles the operation.
 
 Type 3a is a memory operation with a DTLB miss.  The Dcache enters a special set of states
 designed to handle the page table walker (HTPW).  Secondly the HPTW takes control over the
-LSU via a set of multiplexors in the LSU Arbiter, driving the Dcache with addresses into the
+LSU via a set of multiplexors in the LSU Arbiter, driving the Dcache with addresses of the
 page table.  Interally to the HPTW an FSM checks each node of the Page Table and eventually
 signals either a TLB write or a TLB Fault.  In Type 3a the DTLB is written with the leaf
 page table entry and returns control of the Dcache back to the IEU.  Now the Dcache finishes
@@ -70,7 +70,7 @@ Type 4b is also an ITLB miss.  As with 4a the Dcache switches into page table wa
 until it finds a leaf or in this case a fault.  The fault is deteched and the Dcaches switches back
 to normal mode.
 
-Type 5a is a Type 4a with a current memory operation.  The Dcache first switches to walker mode
+Type 5a is a Type 4a with a current memory operation.  The Dcache first switches to walker mode.
 
 Other traps.
 A new problem has emerged.  What happens when an interrupt occurs during a page table walk?

From 81da8b8d2ab548ec321a721a9ed496eb61537377 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Dec 2021 17:16:13 -0600
Subject: [PATCH 29/95] Formating changes to cache fsms.

---
 wally-pipelined/src/cache/dcachefsm.sv | 1310 ++++++++++++------------
 wally-pipelined/src/cache/icachefsm.sv |  246 ++---
 2 files changed, 778 insertions(+), 778 deletions(-)

diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index cbfd2091..63e712f1 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -27,116 +27,116 @@
 
 module dcachefsm
   (input logic clk,
-   input logic 	      reset,
+   input logic 		  reset,
    // inputs from IEU
    input logic [1:0]  MemRWM,
    input logic [1:0]  AtomicM,
-   input logic 	      FlushDCacheM,
+   input logic 		  FlushDCacheM,
    // hazard inputs
-   input logic 	      ExceptionM,
-   input logic 	      PendingInterruptM,
-   input logic 	      StallWtoDCache,
+   input logic 		  ExceptionM,
+   input logic 		  PendingInterruptM,
+   input logic 		  StallWtoDCache,
    // mmu inputs
-   input logic 	      DTLBMissM,
-   input logic 	      ITLBMissF,
-   input logic 	      CacheableM,
-   input logic 	      DTLBWriteM,
-   input logic 	      ITLBWriteF,
-   input logic 	      WalkerInstrPageFaultF,
+   input logic 		  DTLBMissM,
+   input logic 		  ITLBMissF,
+   input logic 		  CacheableM,
+   input logic 		  DTLBWriteM,
+   input logic 		  ITLBWriteF,
+   input logic 		  WalkerInstrPageFaultF,
    // hptw inputs
-   input logic 	      SelPTW,
-   input logic 	      WalkerPageFaultM,
+   input logic 		  SelPTW,
+   input logic 		  WalkerPageFaultM,
    // Bus inputs
-   input logic 	      AHBAck, // from ahb
+   input logic 		  AHBAck, // from ahb
    // dcache internals
-   input logic 	      CacheHit,
-   input logic 	      FetchCountFlag,
-   input logic 	      VictimDirty,
-   input logic 	      FlushAdrFlag,
-   
+   input logic 		  CacheHit,
+   input logic 		  FetchCountFlag,
+   input logic 		  VictimDirty,
+   input logic 		  FlushAdrFlag,
+  
    // hazard outputs
-   output logic       DCacheStall,
-   output logic       CommittedM,
+   output logic 	  DCacheStall,
+   output logic 	  CommittedM,
    // counter outputs
-   output logic       DCacheMiss,
-   output logic       DCacheAccess,
+   output logic 	  DCacheMiss,
+   output logic 	  DCacheAccess,
    // hptw outputs
-   output logic       MemAfterIWalkDone,
+   output logic 	  MemAfterIWalkDone,
    // Bus outputs
-   output logic       AHBRead,
-   output logic       AHBWrite,
+   output logic 	  AHBRead,
+   output logic 	  AHBWrite,
 
    // dcache internals
    output logic [1:0] SelAdrM,
-   output logic       CntEn,
-   output logic       SetValid,
-   output logic       ClearValid,
-   output logic       SetDirty,
-   output logic       ClearDirty,
-   output logic       SRAMWordWriteEnableM,
-   output logic       SRAMBlockWriteEnableM,
-   output logic       CntReset,
-   output logic       SelUncached,
-   output logic       SelEvict,
-   output logic       LRUWriteEn,
-   output logic       SelFlush,
-   output logic       FlushAdrCntEn,
-   output logic       FlushWayCntEn, 
-   output logic       FlushAdrCntRst,
-   output logic       FlushWayCntRst,
-   output logic       VDWriteEnable
+   output logic 	  CntEn,
+   output logic 	  SetValid,
+   output logic 	  ClearValid,
+   output logic 	  SetDirty,
+   output logic 	  ClearDirty,
+   output logic 	  SRAMWordWriteEnableM,
+   output logic 	  SRAMBlockWriteEnableM,
+   output logic 	  CntReset,
+   output logic 	  SelUncached,
+   output logic 	  SelEvict,
+   output logic 	  LRUWriteEn,
+   output logic 	  SelFlush,
+   output logic 	  FlushAdrCntEn,
+   output logic 	  FlushWayCntEn, 
+   output logic 	  FlushAdrCntRst,
+   output logic 	  FlushWayCntRst,
+   output logic 	  VDWriteEnable
 
    );
   
-  logic 	     PreCntEn;
-  logic 	     AnyCPUReqM;
+  logic 			  PreCntEn;
+  logic 			  AnyCPUReqM;
   
-  typedef enum {STATE_READY,
+  typedef enum 		  {STATE_READY,
 
-		STATE_MISS_FETCH_WDV,
-		STATE_MISS_FETCH_DONE,
-		STATE_MISS_EVICT_DIRTY,
-		STATE_MISS_WRITE_CACHE_BLOCK,
-		STATE_MISS_READ_WORD,
-		STATE_MISS_READ_WORD_DELAY,
-		STATE_MISS_WRITE_WORD,
+					   STATE_MISS_FETCH_WDV,
+					   STATE_MISS_FETCH_DONE,
+					   STATE_MISS_EVICT_DIRTY,
+					   STATE_MISS_WRITE_CACHE_BLOCK,
+					   STATE_MISS_READ_WORD,
+					   STATE_MISS_READ_WORD_DELAY,
+					   STATE_MISS_WRITE_WORD,
 
-		STATE_PTW_READY,
-		STATE_PTW_READ_MISS_FETCH_WDV,
-		STATE_PTW_READ_MISS_FETCH_DONE,
-		STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
-		STATE_PTW_READ_MISS_EVICT_DIRTY,		
-		STATE_PTW_READ_MISS_READ_WORD,
-		STATE_PTW_READ_MISS_READ_WORD_DELAY,
-		STATE_PTW_ACCESS_AFTER_WALK,		
+					   STATE_PTW_READY,
+					   STATE_PTW_READ_MISS_FETCH_WDV,
+					   STATE_PTW_READ_MISS_FETCH_DONE,
+					   STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
+					   STATE_PTW_READ_MISS_EVICT_DIRTY,		
+					   STATE_PTW_READ_MISS_READ_WORD,
+					   STATE_PTW_READ_MISS_READ_WORD_DELAY,
+					   STATE_PTW_ACCESS_AFTER_WALK,		
 
-		STATE_UNCACHED_WRITE,
-		STATE_UNCACHED_WRITE_DONE,
-		STATE_UNCACHED_READ,
-		STATE_UNCACHED_READ_DONE,
+					   STATE_UNCACHED_WRITE,
+					   STATE_UNCACHED_WRITE_DONE,
+					   STATE_UNCACHED_READ,
+					   STATE_UNCACHED_READ_DONE,
 
-		STATE_PTW_FAULT_READY,
-		STATE_PTW_FAULT_CPU_BUSY,
-		STATE_PTW_FAULT_MISS_FETCH_WDV,
-		STATE_PTW_FAULT_MISS_FETCH_DONE,
-		STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK,
-		STATE_PTW_FAULT_MISS_READ_WORD,
-		STATE_PTW_FAULT_MISS_READ_WORD_DELAY,
-		STATE_PTW_FAULT_MISS_WRITE_WORD,
-		STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY,
-		STATE_PTW_FAULT_MISS_EVICT_DIRTY,
+					   STATE_PTW_FAULT_READY,
+					   STATE_PTW_FAULT_CPU_BUSY,
+					   STATE_PTW_FAULT_MISS_FETCH_WDV,
+					   STATE_PTW_FAULT_MISS_FETCH_DONE,
+					   STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK,
+					   STATE_PTW_FAULT_MISS_READ_WORD,
+					   STATE_PTW_FAULT_MISS_READ_WORD_DELAY,
+					   STATE_PTW_FAULT_MISS_WRITE_WORD,
+					   STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY,
+					   STATE_PTW_FAULT_MISS_EVICT_DIRTY,
 
-		STATE_PTW_FAULT_UNCACHED_WRITE,
-		STATE_PTW_FAULT_UNCACHED_WRITE_DONE,
-		STATE_PTW_FAULT_UNCACHED_READ,
-		STATE_PTW_FAULT_UNCACHED_READ_DONE,
+					   STATE_PTW_FAULT_UNCACHED_WRITE,
+					   STATE_PTW_FAULT_UNCACHED_WRITE_DONE,
+					   STATE_PTW_FAULT_UNCACHED_READ,
+					   STATE_PTW_FAULT_UNCACHED_READ_DONE,
 
-		STATE_CPU_BUSY,
-		STATE_CPU_BUSY_FINISH_AMO,
-		
-		STATE_FLUSH,
-		STATE_FLUSH_WRITE_BACK,
-		STATE_FLUSH_CLEAR_DIRTY} statetype;
+					   STATE_CPU_BUSY,
+					   STATE_CPU_BUSY_FINISH_AMO,
+  
+					   STATE_FLUSH,
+					   STATE_FLUSH_WRITE_BACK,
+					   STATE_FLUSH_CLEAR_DIRTY} statetype;
 
   (* mark_debug = "true" *) statetype CurrState, NextState;
 
@@ -181,118 +181,118 @@ module dcachefsm
     case (CurrState)
       STATE_READY: begin
 
-	CntReset = 1'b0;
-	DCacheStall = 1'b0;
-	AHBRead = 1'b0;	  
-	AHBWrite = 1'b0;
-	SelAdrM = 2'b00;
-	SRAMWordWriteEnableM = 1'b0;
-	SetDirty = 1'b0;
-	LRUWriteEn = 1'b0;
-	CommittedM = 1'b0;
+		CntReset = 1'b0;
+		DCacheStall = 1'b0;
+		AHBRead = 1'b0;	  
+		AHBWrite = 1'b0;
+		SelAdrM = 2'b00;
+		SRAMWordWriteEnableM = 1'b0;
+		SetDirty = 1'b0;
+		LRUWriteEn = 1'b0;
+		CommittedM = 1'b0;
 
 
-	// TLB Miss	
-	if(((AnyCPUReqM & DTLBMissM) | ITLBMissF) & ~(ExceptionM | PendingInterruptM)) begin
-	  // the LSU arbiter has not yet selected the PTW.
-	  // The CPU needs to be stalled until that happens.
-	  // If we set DCacheStall for 1 cycle before going to
-	  // PTW ready the CPU will stall.
-	  // The page table walker asserts it's control 1 cycle
-	  // after the TLBs miss.
-	  CommittedM = 1'b1;
-	  DCacheStall = 1'b1;
-	  NextState = STATE_PTW_READY;
-	end
+		// TLB Miss	
+		if(((AnyCPUReqM & DTLBMissM) | ITLBMissF) & ~(ExceptionM | PendingInterruptM)) begin
+		  // the LSU arbiter has not yet selected the PTW.
+		  // The CPU needs to be stalled until that happens.
+		  // If we set DCacheStall for 1 cycle before going to
+		  // PTW ready the CPU will stall.
+		  // The page table walker asserts it's control 1 cycle
+		  // after the TLBs miss.
+		  CommittedM = 1'b1;
+		  DCacheStall = 1'b1;
+		  NextState = STATE_PTW_READY;
+		end
 
-	// Flush dcache to next level of memory
-	else if(FlushDCacheM  & ~(ExceptionM | PendingInterruptM)) begin
-	  NextState = STATE_FLUSH;
-	  DCacheStall = 1'b1;
-	  SelAdrM = 2'b11;
-	  FlushAdrCntRst = 1'b1;
-	  FlushWayCntRst = 1'b1;	
-	end
-	
-	// amo hit
-	else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
-	  SelAdrM = 2'b10;
-	  DCacheStall = 1'b0;
-	  
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_CPU_BUSY_FINISH_AMO;
-	    SelAdrM = 2'b10;
-	  end
-	  else begin
-	    SRAMWordWriteEnableM = 1'b1;
-	    SetDirty = 1'b1;
-	    LRUWriteEn = 1'b1;
-	    NextState = STATE_READY;
-	  end
-	end
-	// read hit valid cached
-	else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
-	  DCacheStall = 1'b0;
-	  LRUWriteEn = 1'b1;
-	  
-	  if(StallWtoDCache) begin
-	    NextState = STATE_CPU_BUSY;
+		// Flush dcache to next level of memory
+		else if(FlushDCacheM  & ~(ExceptionM | PendingInterruptM)) begin
+		  NextState = STATE_FLUSH;
+		  DCacheStall = 1'b1;
+		  SelAdrM = 2'b11;
+		  FlushAdrCntRst = 1'b1;
+		  FlushWayCntRst = 1'b1;	
+		end
+		
+		// amo hit
+		else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		  SelAdrM = 2'b10;
+		  DCacheStall = 1'b0;
+		  
+		  if(StallWtoDCache) begin 
+			NextState = STATE_CPU_BUSY_FINISH_AMO;
+			SelAdrM = 2'b10;
+		  end
+		  else begin
+			SRAMWordWriteEnableM = 1'b1;
+			SetDirty = 1'b1;
+			LRUWriteEn = 1'b1;
+			NextState = STATE_READY;
+		  end
+		end
+		// read hit valid cached
+		else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		  DCacheStall = 1'b0;
+		  LRUWriteEn = 1'b1;
+		  
+		  if(StallWtoDCache) begin
+			NextState = STATE_CPU_BUSY;
             SelAdrM = 2'b10;
-	  end
-	  else begin
-	    NextState = STATE_READY;
-	    end
-	end
-	// write hit valid cached
-	else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
-	  SelAdrM = 2'b10;
-	  DCacheStall = 1'b0;
-	  SRAMWordWriteEnableM = 1'b1;
-	  SetDirty = 1'b1;
-	  LRUWriteEn = 1'b1;
-	  
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_CPU_BUSY;
-	    SelAdrM = 2'b10;
-	  end
-	  else begin
-	    NextState = STATE_READY;
-	  end
-	end
-	// read or write miss valid cached
-	else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
-	  NextState = STATE_MISS_FETCH_WDV;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	end
-	// uncached write
-	else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
-	  NextState = STATE_UNCACHED_WRITE;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	  AHBWrite = 1'b1;
-	end
-	// uncached read
-	else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
-	  NextState = STATE_UNCACHED_READ;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	  AHBRead = 1'b1;	  
-	end
-	// fault
-	else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
-	  NextState = STATE_READY;
-	end
-	else NextState = STATE_READY;
+		  end
+		  else begin
+			NextState = STATE_READY;
+	      end
+		end
+		// write hit valid cached
+		else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		  SelAdrM = 2'b10;
+		  DCacheStall = 1'b0;
+		  SRAMWordWriteEnableM = 1'b1;
+		  SetDirty = 1'b1;
+		  LRUWriteEn = 1'b1;
+		  
+		  if(StallWtoDCache) begin 
+			NextState = STATE_CPU_BUSY;
+			SelAdrM = 2'b10;
+		  end
+		  else begin
+			NextState = STATE_READY;
+		  end
+		end
+		// read or write miss valid cached
+		else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
+		  NextState = STATE_MISS_FETCH_WDV;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		end
+		// uncached write
+		else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		  NextState = STATE_UNCACHED_WRITE;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		  AHBWrite = 1'b1;
+		end
+		// uncached read
+		else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		  NextState = STATE_UNCACHED_READ;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		  AHBRead = 1'b1;	  
+		end
+		// fault
+		else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		  NextState = STATE_READY;
+		end
+		else NextState = STATE_READY;
       end
       
       STATE_MISS_FETCH_WDV: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBRead = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	
+		AHBRead = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		
         if (FetchCountFlag & AHBAck) begin
           NextState = STATE_MISS_FETCH_DONE;
         end else begin
@@ -301,170 +301,170 @@ module dcachefsm
       end
 
       STATE_MISS_FETCH_DONE: begin
-	DCacheStall = 1'b1;
-	SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		SelAdrM = 2'b10;
         CntReset = 1'b1;
-	CommittedM = 1'b1;
-	if(VictimDirty) begin
-	  NextState = STATE_MISS_EVICT_DIRTY;
-	end else begin
-	  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
-	end
+		CommittedM = 1'b1;
+		if(VictimDirty) begin
+		  NextState = STATE_MISS_EVICT_DIRTY;
+		end else begin
+		  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
+		end
       end
 
       STATE_MISS_WRITE_CACHE_BLOCK: begin
-	SRAMBlockWriteEnableM = 1'b1;
-	DCacheStall = 1'b1;
-	NextState = STATE_MISS_READ_WORD;
-	SelAdrM = 2'b10;
-	SetValid = 1'b1;
-	ClearDirty = 1'b1;
-	CommittedM = 1'b1;
-	//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
+		SRAMBlockWriteEnableM = 1'b1;
+		DCacheStall = 1'b1;
+		NextState = STATE_MISS_READ_WORD;
+		SelAdrM = 2'b10;
+		SetValid = 1'b1;
+		ClearDirty = 1'b1;
+		CommittedM = 1'b1;
+		//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
       end
 
       STATE_MISS_READ_WORD: begin
-	SelAdrM = 2'b10;
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write.
-	  NextState = STATE_MISS_WRITE_WORD;
-	end else begin
-	  NextState = STATE_MISS_READ_WORD_DELAY;
-	  // delay state is required as the read signal MemRWM[1] is still high when we
-	  // return to the ready state because the cache is stalling the cpu.
-	end
+		SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write.
+		  NextState = STATE_MISS_WRITE_WORD;
+		end else begin
+		  NextState = STATE_MISS_READ_WORD_DELAY;
+		  // delay state is required as the read signal MemRWM[1] is still high when we
+		  // return to the ready state because the cache is stalling the cpu.
+		end
       end
 
       STATE_MISS_READ_WORD_DELAY: begin
-	//SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	SRAMWordWriteEnableM = 1'b0;
-	SetDirty = 1'b0;
-	LRUWriteEn = 1'b0;
-	if(&MemRWM & AtomicM[1]) begin // amo write
-	  SelAdrM = 2'b10;
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_CPU_BUSY_FINISH_AMO;
-	  end
-	  else begin
-	    SRAMWordWriteEnableM = 1'b1;
-	    SetDirty = 1'b1;
-	    LRUWriteEn = 1'b1;
-	    NextState = STATE_READY;
-	  end
-	end else begin
-	  LRUWriteEn = 1'b1;
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_CPU_BUSY;
-	    SelAdrM = 2'b10;
-	  end
-	  else begin
-	    NextState = STATE_READY;
-	  end
-	end
+		//SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		SRAMWordWriteEnableM = 1'b0;
+		SetDirty = 1'b0;
+		LRUWriteEn = 1'b0;
+		if(&MemRWM & AtomicM[1]) begin // amo write
+		  SelAdrM = 2'b10;
+		  if(StallWtoDCache) begin 
+			NextState = STATE_CPU_BUSY_FINISH_AMO;
+		  end
+		  else begin
+			SRAMWordWriteEnableM = 1'b1;
+			SetDirty = 1'b1;
+			LRUWriteEn = 1'b1;
+			NextState = STATE_READY;
+		  end
+		end else begin
+		  LRUWriteEn = 1'b1;
+		  if(StallWtoDCache) begin 
+			NextState = STATE_CPU_BUSY;
+			SelAdrM = 2'b10;
+		  end
+		  else begin
+			NextState = STATE_READY;
+		  end
+		end
       end
 
       STATE_MISS_WRITE_WORD: begin
-	SRAMWordWriteEnableM = 1'b1;
-	SetDirty = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	LRUWriteEn = 1'b1;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		SRAMWordWriteEnableM = 1'b1;
+		SetDirty = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		LRUWriteEn = 1'b1;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
 
       STATE_MISS_EVICT_DIRTY: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBWrite = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	SelEvict = 1'b1;
-	if(FetchCountFlag & AHBAck) begin
-	  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
-	end else begin
-	  NextState = STATE_MISS_EVICT_DIRTY;
-	end	  
+		AHBWrite = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		SelEvict = 1'b1;
+		if(FetchCountFlag & AHBAck) begin
+		  NextState = STATE_MISS_WRITE_CACHE_BLOCK;
+		end else begin
+		  NextState = STATE_MISS_EVICT_DIRTY;
+		end	  
       end
 
       STATE_PTW_READY: begin
-	// now all output connect to PTW instead of CPU.
-	CommittedM = 1'b1;
-	SelAdrM = 2'b00;
-	DCacheStall = 1'b0;
-	LRUWriteEn = 1'b0;
-	CntReset = 1'b0;
+		// now all output connect to PTW instead of CPU.
+		CommittedM = 1'b1;
+		SelAdrM = 2'b00;
+		DCacheStall = 1'b0;
+		LRUWriteEn = 1'b0;
+		CntReset = 1'b0;
 
-	// In this branch we remove stall and go back to ready.  There is no request for memory from the
-	// datapath or the walker had a fault.
-	// types 3b, 4a, 4b, and 7c.
-	if ((DTLBMissM & WalkerPageFaultM) | // 3b
-	    (ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b
-	    (DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c
-	  NextState = STATE_READY;
-	  DCacheStall = 1'b0;
-	end
-	// in this branch we go back to ready, but there is a memory operation from
-	// the datapath so we MUST stall and replay the operation.
-	// types 3a and 5a
-	else if ((DTLBMissM & DTLBWriteM) |  // 3a
-		 (ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a
-	  NextState = STATE_READY;
-	  DCacheStall = 1'b1;
-	  SelAdrM = 2'b01;
-	end
+		// In this branch we remove stall and go back to ready.  There is no request for memory from the
+		// datapath or the walker had a fault.
+		// types 3b, 4a, 4b, and 7c.
+		if ((DTLBMissM & WalkerPageFaultM) | // 3b or 7c (can have either itlb miss or not)
+			(ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b
+			(DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c  *** BUG redundant with first condiction.
+		  NextState = STATE_READY;
+		  DCacheStall = 1'b0;
+		end
+		// in this branch we go back to ready, but there is a memory operation from
+		// the datapath so we MUST stall and replay the operation.
+		// types 3a and 5a
+		else if ((DTLBMissM & DTLBWriteM) |  // 3a
+				 (ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a
+		  NextState = STATE_READY;
+		  DCacheStall = 1'b1;
+		  SelAdrM = 2'b01;
+		end
 
-	// like 5a we want to stall and go to the ready state, but we also have to save
-	// the WalkerInstrPageFaultF so it is held until the end of the memory operation
-	// from the datapath.
-	// types 5b
-	else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b
-	  NextState = STATE_PTW_FAULT_READY;
-	  DCacheStall = 1'b1;
-	  SelAdrM = 2'b01;
-	end
+		// like 5a we want to stall and go to the ready state, but we also have to save
+		// the WalkerInstrPageFaultF so it is held until the end of the memory operation
+		// from the datapath.
+		// types 5b
+		else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b
+		  NextState = STATE_PTW_FAULT_READY;
+		  DCacheStall = 1'b1;
+		  SelAdrM = 2'b01;
+		end
 
-	// in this branch we stay in ptw_ready because we are doing an itlb walk
-	// after a dtlb walk.
-	// types 7a and 7b.
-	else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin
-	  NextState = STATE_PTW_READY;
-	  DCacheStall = 1'b0;
-	  
-	// read hit valid cached
-	end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
-	  NextState = STATE_PTW_READY;
-	  DCacheStall = 1'b0;
-	  LRUWriteEn = 1'b1;
-	end
+		// in this branch we stay in ptw_ready because we are doing an itlb walk
+		// after a dtlb walk.
+		// types 7a and 7b.
+		else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin
+		  NextState = STATE_PTW_READY;
+		  DCacheStall = 1'b0;
+		  
+		  // read hit valid cached
+		end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
+		  NextState = STATE_PTW_READY;
+		  DCacheStall = 1'b0;
+		  LRUWriteEn = 1'b1;
+		end
 
-	// read miss valid cached
-	else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin
-	  NextState = STATE_PTW_READ_MISS_FETCH_WDV;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	end
+		// read miss valid cached
+		else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin
+		  NextState = STATE_PTW_READ_MISS_FETCH_WDV;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		end
 
-	else begin
-	  NextState = STATE_PTW_READY;
-	  DCacheStall = 1'b0;
-	end
+		else begin
+		  NextState = STATE_PTW_READY;
+		  DCacheStall = 1'b0;
+		end
       end
 
       STATE_PTW_READ_MISS_FETCH_WDV: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBRead = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	
+		AHBRead = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		
         if(FetchCountFlag & AHBAck) begin
           NextState = STATE_PTW_READ_MISS_FETCH_DONE;
         end else begin
@@ -473,238 +473,238 @@ module dcachefsm
       end
 
       STATE_PTW_READ_MISS_FETCH_DONE: begin
-	DCacheStall = 1'b1;
-	SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		SelAdrM = 2'b10;
         CntReset = 1'b1;
-	CommittedM = 1'b1;
+		CommittedM = 1'b1;
         CntReset = 1'b1;
-	if(VictimDirty) begin
-	  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
-	end else begin
-	  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
-	end
+		if(VictimDirty) begin
+		  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
+		end else begin
+		  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
+		end
       end
 
       STATE_PTW_READ_MISS_EVICT_DIRTY: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBWrite = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	SelEvict = 1'b1;
-	if(FetchCountFlag & AHBAck) begin
-	  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
-	end else begin
-	  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
-	end	  
+		AHBWrite = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		SelEvict = 1'b1;
+		if(FetchCountFlag & AHBAck) begin
+		  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
+		end else begin
+		  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
+		end	  
       end
       
 
       STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin
-	SRAMBlockWriteEnableM = 1'b1;
-	DCacheStall = 1'b1;
-	NextState = STATE_PTW_READ_MISS_READ_WORD;
-	SelAdrM = 2'b10;
-	SetValid = 1'b1;
-	ClearDirty = 1'b1;
-	CommittedM = 1'b1;
-	//LRUWriteEn = 1'b1;
+		SRAMBlockWriteEnableM = 1'b1;
+		DCacheStall = 1'b1;
+		NextState = STATE_PTW_READ_MISS_READ_WORD;
+		SelAdrM = 2'b10;
+		SetValid = 1'b1;
+		ClearDirty = 1'b1;
+		CommittedM = 1'b1;
+		//LRUWriteEn = 1'b1;
       end
 
       STATE_PTW_READ_MISS_READ_WORD: begin
-	SelAdrM = 2'b10;
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
+		SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
       end
 
       STATE_PTW_READ_MISS_READ_WORD_DELAY: begin
-	SelAdrM = 2'b10;
-	NextState = STATE_PTW_READY;
-	CommittedM = 1'b1;
+		SelAdrM = 2'b10;
+		NextState = STATE_PTW_READY;
+		CommittedM = 1'b1;
       end
       
       STATE_PTW_ACCESS_AFTER_WALK: begin
-	DCacheStall = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	LRUWriteEn = 1'b1;
-	NextState = STATE_READY;
+		DCacheStall = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		LRUWriteEn = 1'b1;
+		NextState = STATE_READY;
       end
       
       STATE_CPU_BUSY: begin
-	CommittedM = 1'b1;
-	SelAdrM = 2'b00;
-	if(StallWtoDCache) begin
-	  NextState = STATE_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		CommittedM = 1'b1;
+		SelAdrM = 2'b00;
+		if(StallWtoDCache) begin
+		  NextState = STATE_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
 
       STATE_CPU_BUSY_FINISH_AMO: begin
-	CommittedM = 1'b1;
-	SelAdrM = 2'b10;
-	SRAMWordWriteEnableM = 1'b0;
-	SetDirty = 1'b0;
-	LRUWriteEn = 1'b0;
-	if(StallWtoDCache) begin
-	  NextState = STATE_CPU_BUSY_FINISH_AMO;
-	end
-	else begin
-	  SRAMWordWriteEnableM = 1'b1;
-	  SetDirty = 1'b1;
-	  LRUWriteEn = 1'b1;
-	  NextState = STATE_READY;
-	end
+		CommittedM = 1'b1;
+		SelAdrM = 2'b10;
+		SRAMWordWriteEnableM = 1'b0;
+		SetDirty = 1'b0;
+		LRUWriteEn = 1'b0;
+		if(StallWtoDCache) begin
+		  NextState = STATE_CPU_BUSY_FINISH_AMO;
+		end
+		else begin
+		  SRAMWordWriteEnableM = 1'b1;
+		  SetDirty = 1'b1;
+		  LRUWriteEn = 1'b1;
+		  NextState = STATE_READY;
+		end
       end
 
       STATE_UNCACHED_WRITE : begin
-	DCacheStall = 1'b1;	
-	AHBWrite = 1'b1;
-	CommittedM = 1'b1;
-	if(AHBAck) begin
-	  NextState = STATE_UNCACHED_WRITE_DONE;
-	end else begin
-	  NextState = STATE_UNCACHED_WRITE;
-	end
+		DCacheStall = 1'b1;	
+		AHBWrite = 1'b1;
+		CommittedM = 1'b1;
+		if(AHBAck) begin
+		  NextState = STATE_UNCACHED_WRITE_DONE;
+		end else begin
+		  NextState = STATE_UNCACHED_WRITE;
+		end
       end
 
       STATE_UNCACHED_READ: begin
-	DCacheStall = 1'b1;	
-	AHBRead = 1'b1;
-	CommittedM = 1'b1;
-	if(AHBAck) begin
-	  NextState = STATE_UNCACHED_READ_DONE;
-	end else begin
-	  NextState = STATE_UNCACHED_READ;
-	end
+		DCacheStall = 1'b1;	
+		AHBRead = 1'b1;
+		CommittedM = 1'b1;
+		if(AHBAck) begin
+		  NextState = STATE_UNCACHED_READ_DONE;
+		end else begin
+		  NextState = STATE_UNCACHED_READ;
+		end
       end
       
       STATE_UNCACHED_WRITE_DONE: begin
-	CommittedM = 1'b1;
-	SelAdrM = 2'b00;
-	if(StallWtoDCache) begin
-	  NextState = STATE_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		CommittedM = 1'b1;
+		SelAdrM = 2'b00;
+		if(StallWtoDCache) begin
+		  NextState = STATE_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
 
       STATE_UNCACHED_READ_DONE: begin
-	CommittedM = 1'b1;
-	SelUncached = 1'b1;
-	SelAdrM = 2'b00;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end 
+		CommittedM = 1'b1;
+		SelUncached = 1'b1;
+		SelAdrM = 2'b00;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end 
       end
 
 
       // itlb => instruction page fault states with memory request.
       STATE_PTW_FAULT_READY: begin
-	DCacheStall = 1'b0;
-	LRUWriteEn = 1'b0;
-	SelAdrM = 2'b00;
-	MemAfterIWalkDone = 1'b0;
-	SetDirty = 1'b0;
-	LRUWriteEn = 1'b0;
-	CntReset = 1'b0;
-	AHBWrite = 1'b0;
-	AHBRead = 1'b0;
-	CommittedM = 1'b1;
-	NextState = STATE_READY;
-	
-	
-	// read hit valid cached
-	if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
-	  DCacheStall = 1'b0;
-	  LRUWriteEn = 1'b1;
-	  
-	  if(StallWtoDCache) begin
-	    NextState = STATE_PTW_FAULT_CPU_BUSY;
+		DCacheStall = 1'b0;
+		LRUWriteEn = 1'b0;
+		SelAdrM = 2'b00;
+		MemAfterIWalkDone = 1'b0;
+		SetDirty = 1'b0;
+		LRUWriteEn = 1'b0;
+		CntReset = 1'b0;
+		AHBWrite = 1'b0;
+		AHBRead = 1'b0;
+		CommittedM = 1'b1;
+		NextState = STATE_READY;
+		
+		
+		// read hit valid cached
+		if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
+		  DCacheStall = 1'b0;
+		  LRUWriteEn = 1'b1;
+		  
+		  if(StallWtoDCache) begin
+			NextState = STATE_PTW_FAULT_CPU_BUSY;
             SelAdrM = 2'b10;
-	  end
-	  else begin
-	    MemAfterIWalkDone = 1'b1;
-	    NextState = STATE_READY;
-	  end
-	end
-	
-	// write hit valid cached
-	else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin
-	  SelAdrM = 2'b10;
-	  DCacheStall = 1'b0;
-	  SRAMWordWriteEnableM = 1'b1;
-	  SetDirty = 1'b1;
-	  LRUWriteEn = 1'b1;
-	  
-	  if(StallWtoDCache) begin 
-	    NextState = STATE_PTW_FAULT_CPU_BUSY;
-	    SelAdrM = 2'b10;
-	  end
-	  else begin
-	    MemAfterIWalkDone = 1'b1;
-	    NextState = STATE_READY;
-	  end
-	end
-	// read or write miss valid cached
-	else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin
-	  NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	end
-	// uncached write
-	else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	  AHBWrite = 1'b1;
-	end
-	// uncached read
-	else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_READ;
-	  CntReset = 1'b1;
-	  DCacheStall = 1'b1;
-	  AHBRead = 1'b1;	  
-	  MemAfterIWalkDone = 1'b0;
-	end
-	// fault
-	else  begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	end
+		  end
+		  else begin
+			MemAfterIWalkDone = 1'b1;
+			NextState = STATE_READY;
+		  end
+		end
+		
+		// write hit valid cached
+		else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin
+		  SelAdrM = 2'b10;
+		  DCacheStall = 1'b0;
+		  SRAMWordWriteEnableM = 1'b1;
+		  SetDirty = 1'b1;
+		  LRUWriteEn = 1'b1;
+		  
+		  if(StallWtoDCache) begin 
+			NextState = STATE_PTW_FAULT_CPU_BUSY;
+			SelAdrM = 2'b10;
+		  end
+		  else begin
+			MemAfterIWalkDone = 1'b1;
+			NextState = STATE_READY;
+		  end
+		end
+		// read or write miss valid cached
+		else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin
+		  NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		end
+		// uncached write
+		else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		  AHBWrite = 1'b1;
+		end
+		// uncached read
+		else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_READ;
+		  CntReset = 1'b1;
+		  DCacheStall = 1'b1;
+		  AHBRead = 1'b1;	  
+		  MemAfterIWalkDone = 1'b0;
+		end
+		// fault
+		else  begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		end
       end
       
       STATE_PTW_FAULT_CPU_BUSY: begin
-	CommittedM = 1'b1;
-	if(StallWtoDCache) begin
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  MemAfterIWalkDone = 1'b0;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	  SelAdrM = 2'b00;
-	end
+		CommittedM = 1'b1;
+		if(StallWtoDCache) begin
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  MemAfterIWalkDone = 1'b0;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		  SelAdrM = 2'b00;
+		end
       end
 
       STATE_PTW_FAULT_MISS_FETCH_WDV: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBRead = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	
+		AHBRead = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		
         if(FetchCountFlag & AHBAck) begin
           NextState = STATE_PTW_FAULT_MISS_FETCH_DONE;
         end else begin
@@ -713,201 +713,201 @@ module dcachefsm
       end
 
       STATE_PTW_FAULT_MISS_FETCH_DONE: begin
-	DCacheStall = 1'b1;
-	SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		SelAdrM = 2'b10;
         CntReset = 1'b1;
-	CommittedM = 1'b1;
-	if(VictimDirty) begin
-	  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
-	end else begin
-	  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
-	end
+		CommittedM = 1'b1;
+		if(VictimDirty) begin
+		  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
+		end else begin
+		  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
+		end
       end
 
       STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK: begin
-	SRAMBlockWriteEnableM = 1'b1;
-	DCacheStall = 1'b1;
-	NextState = STATE_PTW_FAULT_MISS_READ_WORD;
-	SelAdrM = 2'b10;
-	SetValid = 1'b1;
-	ClearDirty = 1'b1;
-	CommittedM = 1'b1;
-	//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
+		SRAMBlockWriteEnableM = 1'b1;
+		DCacheStall = 1'b1;
+		NextState = STATE_PTW_FAULT_MISS_READ_WORD;
+		SelAdrM = 2'b10;
+		SetValid = 1'b1;
+		ClearDirty = 1'b1;
+		CommittedM = 1'b1;
+		//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
       end
 
       STATE_PTW_FAULT_MISS_READ_WORD: begin
-	SelAdrM = 2'b10;
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	if(MemRWM[1]) begin
-	  NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY;
-	  // delay state is required as the read signal MemRWM[1] is still high when we
-	  // return to the ready state because the cache is stalling the cpu.
-	end else begin
-	  NextState = STATE_PTW_FAULT_MISS_WRITE_WORD;
-	end
+		SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		if(MemRWM[1]) begin
+		  NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY;
+		  // delay state is required as the read signal MemRWM[1] is still high when we
+		  // return to the ready state because the cache is stalling the cpu.
+		end else begin
+		  NextState = STATE_PTW_FAULT_MISS_WRITE_WORD;
+		end
       end
 
       STATE_PTW_FAULT_MISS_READ_WORD_DELAY: begin
-	CommittedM = 1'b1;
-	LRUWriteEn = 1'b1;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	  MemAfterIWalkDone = 1'b0;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	  SelAdrM = 2'b00;
-	end
+		CommittedM = 1'b1;
+		LRUWriteEn = 1'b1;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		  MemAfterIWalkDone = 1'b0;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		  SelAdrM = 2'b00;
+		end
       end
 
       STATE_PTW_FAULT_MISS_WRITE_WORD: begin
-	SRAMWordWriteEnableM = 1'b1;
-	SetDirty = 1'b1;
-	SelAdrM = 2'b10;
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	LRUWriteEn = 1'b1;
-	NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY;
+		SRAMWordWriteEnableM = 1'b1;
+		SetDirty = 1'b1;
+		SelAdrM = 2'b10;
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		LRUWriteEn = 1'b1;
+		NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY;
       end
 
       STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY: begin
-	CommittedM = 1'b1;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  MemAfterIWalkDone = 1'b0;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	  SelAdrM = 2'b00;
-	end
+		CommittedM = 1'b1;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  MemAfterIWalkDone = 1'b0;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		  SelAdrM = 2'b00;
+		end
       end
 
       STATE_PTW_FAULT_MISS_EVICT_DIRTY: begin
-	DCacheStall = 1'b1;
+		DCacheStall = 1'b1;
         PreCntEn = 1'b1;
-	AHBWrite = 1'b1;
-	SelAdrM = 2'b10;
-	CommittedM = 1'b1;
-	SelEvict = 1'b1;
-	if(FetchCountFlag & AHBAck) begin
-	  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
-	end else begin
-	  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
-	end	  
+		AHBWrite = 1'b1;
+		SelAdrM = 2'b10;
+		CommittedM = 1'b1;
+		SelEvict = 1'b1;
+		if(FetchCountFlag & AHBAck) begin
+		  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
+		end else begin
+		  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
+		end	  
       end
 
 
       STATE_PTW_FAULT_UNCACHED_WRITE : begin
-	DCacheStall = 1'b1;	
-	AHBWrite = 1'b1;
-	CommittedM = 1'b1;
-	if(AHBAck) begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE;
-	end else begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
-	end
+		DCacheStall = 1'b1;	
+		AHBWrite = 1'b1;
+		CommittedM = 1'b1;
+		if(AHBAck) begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE;
+		end else begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
+		end
       end
 
       STATE_PTW_FAULT_UNCACHED_READ : begin
-	DCacheStall = 1'b1;	
-	AHBRead = 1'b1;
-	CommittedM = 1'b1;
-	if(AHBAck) begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE;
-	end else begin
-	  NextState = STATE_PTW_FAULT_UNCACHED_READ;
-	end
+		DCacheStall = 1'b1;	
+		AHBRead = 1'b1;
+		CommittedM = 1'b1;
+		if(AHBAck) begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE;
+		end else begin
+		  NextState = STATE_PTW_FAULT_UNCACHED_READ;
+		end
       end
       
       STATE_PTW_FAULT_UNCACHED_WRITE_DONE: begin
-	CommittedM = 1'b1;
-	if(StallWtoDCache) begin
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  MemAfterIWalkDone = 1'b0;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	  SelAdrM = 2'b00;
-	end
+		CommittedM = 1'b1;
+		if(StallWtoDCache) begin
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  MemAfterIWalkDone = 1'b0;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		  SelAdrM = 2'b00;
+		end
       end
 
       STATE_PTW_FAULT_UNCACHED_READ_DONE: begin
-	CommittedM = 1'b1;
-	SelUncached = 1'b1;
-	if(StallWtoDCache) begin 
-	  NextState = STATE_PTW_FAULT_CPU_BUSY;
-	  SelAdrM = 2'b10;
-	end
-	else begin
-	  MemAfterIWalkDone = 1'b1;
-	  NextState = STATE_READY;
-	end 
+		CommittedM = 1'b1;
+		SelUncached = 1'b1;
+		if(StallWtoDCache) begin 
+		  NextState = STATE_PTW_FAULT_CPU_BUSY;
+		  SelAdrM = 2'b10;
+		end
+		else begin
+		  MemAfterIWalkDone = 1'b1;
+		  NextState = STATE_READY;
+		end 
       end
 
       STATE_FLUSH: begin
-	DCacheStall = 1'b1;
-	CommittedM = 1'b1;
-	SelAdrM = 2'b11;
-	SelFlush = 1'b1;
-	FlushAdrCntEn = 1'b1;
-	FlushWayCntEn = 1'b1;
-	CntReset = 1'b1;
-	if(VictimDirty) begin
-	  NextState = STATE_FLUSH_WRITE_BACK;
-	  FlushAdrCntEn = 1'b0;
-	  FlushWayCntEn = 1'b0;
-	end else if (FlushAdrFlag) begin
-	  NextState = STATE_READY;
-	  DCacheStall = 1'b0;
-	  FlushAdrCntEn = 1'b0;
-	  FlushWayCntEn = 1'b0;	
-	end else begin
-	  NextState = STATE_FLUSH;
-	end
+		DCacheStall = 1'b1;
+		CommittedM = 1'b1;
+		SelAdrM = 2'b11;
+		SelFlush = 1'b1;
+		FlushAdrCntEn = 1'b1;
+		FlushWayCntEn = 1'b1;
+		CntReset = 1'b1;
+		if(VictimDirty) begin
+		  NextState = STATE_FLUSH_WRITE_BACK;
+		  FlushAdrCntEn = 1'b0;
+		  FlushWayCntEn = 1'b0;
+		end else if (FlushAdrFlag) begin
+		  NextState = STATE_READY;
+		  DCacheStall = 1'b0;
+		  FlushAdrCntEn = 1'b0;
+		  FlushWayCntEn = 1'b0;	
+		end else begin
+		  NextState = STATE_FLUSH;
+		end
       end
 
       STATE_FLUSH_WRITE_BACK: begin
-	DCacheStall = 1'b1;
-	AHBWrite = 1'b1;
-	SelAdrM = 2'b11;
-	CommittedM = 1'b1;
-	SelFlush = 1'b1;
+		DCacheStall = 1'b1;
+		AHBWrite = 1'b1;
+		SelAdrM = 2'b11;
+		CommittedM = 1'b1;
+		SelFlush = 1'b1;
         PreCntEn = 1'b1;
-	if(FetchCountFlag & AHBAck) begin
-	  NextState = STATE_FLUSH_CLEAR_DIRTY;
-	end else begin
-	  NextState = STATE_FLUSH_WRITE_BACK;
-	end	  
+		if(FetchCountFlag & AHBAck) begin
+		  NextState = STATE_FLUSH_CLEAR_DIRTY;
+		end else begin
+		  NextState = STATE_FLUSH_WRITE_BACK;
+		end	  
       end
 
       STATE_FLUSH_CLEAR_DIRTY: begin
-	DCacheStall = 1'b1;
-	ClearDirty = 1'b1;
-	VDWriteEnable = 1'b1;
-	SelFlush = 1'b1;
-	SelAdrM = 2'b11;
-	FlushAdrCntEn = 1'b0;
-	FlushWayCntEn = 1'b0;	
-	if(FlushAdrFlag) begin
-	  NextState = STATE_READY;
-	  DCacheStall = 1'b0;
-	  SelAdrM = 2'b00;
-	end else begin
-	  NextState = STATE_FLUSH;
-	  FlushAdrCntEn = 1'b1;
-	  FlushWayCntEn = 1'b1;	
-	end
+		DCacheStall = 1'b1;
+		ClearDirty = 1'b1;
+		VDWriteEnable = 1'b1;
+		SelFlush = 1'b1;
+		SelAdrM = 2'b11;
+		FlushAdrCntEn = 1'b0;
+		FlushWayCntEn = 1'b0;	
+		if(FlushAdrFlag) begin
+		  NextState = STATE_READY;
+		  DCacheStall = 1'b0;
+		  SelAdrM = 2'b00;
+		end else begin
+		  NextState = STATE_FLUSH;
+		  FlushAdrCntEn = 1'b1;
+		  FlushWayCntEn = 1'b1;	
+		end
       end
 
       default: begin
-	NextState = STATE_READY;
+		NextState = STATE_READY;
       end
     endcase
   end
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 433328ab..33080d9f 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -27,95 +27,95 @@
 
 module icachefsm
   (// Inputs from pipeline
-   input logic 	      clk, reset,
+   input logic 		  clk, reset,
 
-   input logic 	      StallF,
+   input logic 		  StallF,
 
    // inputs from mmu
-   input logic 	      ITLBMissF,
-   input logic 	      ITLBWriteF,
-   input logic 	      WalkerInstrPageFaultF,
+   input logic 		  ITLBMissF,
+   input logic 		  ITLBWriteF,
+   input logic 		  WalkerInstrPageFaultF,
 
-   input logic ExceptionM, PendingInterruptM,
+   input logic 		  ExceptionM, PendingInterruptM,
 
    // BUS interface
-   input logic 	      InstrAckF,
+   input logic 		  InstrAckF,
 
    // icache internal inputs
-   input logic 	      hit,
-   input logic 	      FetchCountFlag,
-   input logic 	      spill,
+   input logic 		  hit,
+   input logic 		  FetchCountFlag,
+   input logic 		  spill,
 
    // icache internal outputs
-   output logic       ICacheReadEn,
+   output logic 	  ICacheReadEn,
    // Load data into the cache
-   output logic       ICacheMemWriteEnable,
+   output logic 	  ICacheMemWriteEnable,
 
    // Outputs to pipeline control stuff
-   output logic       ICacheStallF,
+   output logic 	  ICacheStallF,
 
    // Bus interface outputs
-   output logic       InstrReadF,
+   output logic 	  InstrReadF,
 
    // icache internal outputs
-   output logic       spillSave,
-   output logic       CntEn,
-   output logic       CntReset,
+   output logic 	  spillSave,
+   output logic 	  CntEn,
+   output logic 	  CntReset,
    output logic [1:0] SelAdr,
-   output logic       LRUWriteEn
+   output logic 	  LRUWriteEn
    );
 
   // FSM states
-  typedef enum {STATE_READY,
-		STATE_HIT_SPILL, // spill, block 0 hit
-		STATE_HIT_SPILL_MISS_FETCH_WDV, // block 1 miss, issue read to AHB and wait data.
-		STATE_HIT_SPILL_MISS_FETCH_DONE, // write data into SRAM/LUT
-		STATE_HIT_SPILL_MERGE,   // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
+  typedef enum 		  {STATE_READY,
+					   STATE_HIT_SPILL, // spill, block 0 hit
+					   STATE_HIT_SPILL_MISS_FETCH_WDV, // block 1 miss, issue read to AHB and wait data.
+					   STATE_HIT_SPILL_MISS_FETCH_DONE, // write data into SRAM/LUT
+					   STATE_HIT_SPILL_MERGE,   // Read block 0 of CPU access, should be able to optimize into STATE_HIT_SPILL.
 
-		// a challenge is the spill signal gets us out of the ready state and moves us to
-		// 1 of the 2 spill branches.  However the original fsm design had us return to
-		// the ready state when the spill + hits/misses were fully resolved.  The problem
-		// is the spill signal is based on PCPF so when we return to READY to check if the
-		// cache has a hit it still expresses spill.  We can fix in 1 of two ways.
-		// 1. we can add 1 extra state at the end of each spill branch to returns the instruction
-		// to the CPU advancing the CPU and icache to the next instruction.
-		// 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
-		// to the READY state.
-		// The first first option is more robust and increases the number of states by 2.  The
-		// second option is seams like it should work, but I worry there is a hidden interaction 
-		// between CPU stalling and that register.
-		// Picking option 1.
+					   // a challenge is the spill signal gets us out of the ready state and moves us to
+					   // 1 of the 2 spill branches.  However the original fsm design had us return to
+					   // the ready state when the spill + hits/misses were fully resolved.  The problem
+					   // is the spill signal is based on PCPF so when we return to READY to check if the
+					   // cache has a hit it still expresses spill.  We can fix in 1 of two ways.
+					   // 1. we can add 1 extra state at the end of each spill branch to returns the instruction
+					   // to the CPU advancing the CPU and icache to the next instruction.
+					   // 2. We can assert a signal which is delayed 1 cycle to suppress the spill when we get
+					   // to the READY state.
+					   // The first first option is more robust and increases the number of states by 2.  The
+					   // second option is seams like it should work, but I worry there is a hidden interaction 
+					   // between CPU stalling and that register.
+					   // Picking option 1.
 
-		STATE_HIT_SPILL_FINAL, // this state replicates STATE_READY's replay of the
-		// spill access but does nto consider spill.  It also does not do another operation.
+					   STATE_HIT_SPILL_FINAL, // this state replicates STATE_READY's replay of the
+					   // spill access but does nto consider spill.  It also does not do another operation.
   
-		STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
-		STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
-		STATE_MISS_READ, // read block 1 from SRAM/LUT
-		STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT  		
+					   STATE_MISS_FETCH_WDV, // aligned miss, issue read to AHB and wait for data.
+					   STATE_MISS_FETCH_DONE, // write data into SRAM/LUT
+					   STATE_MISS_READ, // read block 1 from SRAM/LUT
+					   STATE_MISS_READ_DELAY, // read block 1 from SRAM/LUT  		
 
-		STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait
-		STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT
-		STATE_MISS_SPILL_READ1, // read block 0 from SRAM/LUT
-		STATE_MISS_SPILL_2, // return to ready if hit or do second block update.
-		STATE_MISS_SPILL_2_START, // return to ready if hit or do second block update.  
-		STATE_MISS_SPILL_MISS_FETCH_WDV, // miss on block 1, issue read to AHB and wait
-		STATE_MISS_SPILL_MISS_FETCH_DONE, // write data to SRAM/LUT
-		STATE_MISS_SPILL_MERGE, // read block 0 of CPU access,
+					   STATE_MISS_SPILL_FETCH_WDV, // spill, miss on block 0, issue read to AHB and wait
+					   STATE_MISS_SPILL_FETCH_DONE, // write data into SRAM/LUT
+					   STATE_MISS_SPILL_READ1, // read block 0 from SRAM/LUT
+					   STATE_MISS_SPILL_2, // return to ready if hit or do second block update.
+					   STATE_MISS_SPILL_2_START, // return to ready if hit or do second block update.  
+					   STATE_MISS_SPILL_MISS_FETCH_WDV, // miss on block 1, issue read to AHB and wait
+					   STATE_MISS_SPILL_MISS_FETCH_DONE, // write data to SRAM/LUT
+					   STATE_MISS_SPILL_MERGE, // read block 0 of CPU access,
 
-		STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the
-		// spill access but does nto consider spill.  It also does not do another operation.
+					   STATE_MISS_SPILL_FINAL, // this state replicates STATE_READY's replay of the
+					   // spill access but does nto consider spill.  It also does not do another operation.
 
-		STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address?
-		STATE_TLB_MISS,
-		STATE_TLB_MISS_DONE,
+					   STATE_INVALIDATE, // *** not sure if invalidate or evict? invalidate by cache block or address?
+					   STATE_TLB_MISS,
+					   STATE_TLB_MISS_DONE,
 
-		STATE_CPU_BUSY,
-		STATE_CPU_BUSY_SPILL		
-		} statetype;
+					   STATE_CPU_BUSY,
+					   STATE_CPU_BUSY_SPILL		
+					   } statetype;
   
   (* mark_debug = "true" *)  statetype CurrState, NextState;
-  logic 		       PreCntEn;
+  logic 			  PreCntEn;
 
   // the FSM is always runing, do not stall.
   always_ff @(posedge clk)
@@ -141,18 +141,18 @@ module icachefsm
           NextState = STATE_TLB_MISS;
         end else if (hit & ~spill) begin
           ICacheStallF = 1'b0;
-	  LRUWriteEn = 1'b1;
-	  if(StallF) begin
-	    NextState = STATE_CPU_BUSY;
-	    SelAdr = 2'b01;
-	  end else begin
+		  LRUWriteEn = 1'b1;
+		  if(StallF) begin
+			NextState = STATE_CPU_BUSY;
+			SelAdr = 2'b01;
+		  end else begin
             NextState = STATE_READY;
-	  end
+		  end
         end else if (hit & spill) begin
           spillSave = 1'b1;
           SelAdr = 2'b10;
           LRUWriteEn = 1'b1;
-	  NextState = STATE_HIT_SPILL;
+		  NextState = STATE_HIT_SPILL;
         end else if (~hit & ~spill) begin
           CntReset = 1'b1;
           NextState = STATE_MISS_FETCH_WDV;
@@ -161,12 +161,12 @@ module icachefsm
           SelAdr = 2'b01;
           NextState = STATE_MISS_SPILL_FETCH_WDV;
         end else begin
-	  if(StallF) begin
-	    NextState = STATE_CPU_BUSY;
-	    SelAdr = 2'b01;
-	  end else begin
+		  if(StallF) begin
+			NextState = STATE_CPU_BUSY;
+			SelAdr = 2'b01;
+		  end else begin
             NextState = STATE_READY;
-	  end
+		  end
         end
       end
       // branch 1,  hit spill and 2, miss spill hit
@@ -204,15 +204,15 @@ module icachefsm
         ICacheReadEn = 1'b1;
         SelAdr = 2'b00;
         ICacheStallF = 1'b0;
-	LRUWriteEn = 1'b1;
-	
-	if(StallF) begin
-	  NextState = STATE_CPU_BUSY_SPILL;
-	  SelAdr = 2'b10;
-	end else begin
+		LRUWriteEn = 1'b1;
+		
+		if(StallF) begin
+		  NextState = STATE_CPU_BUSY_SPILL;
+		  SelAdr = 2'b10;
+		end else begin
           NextState = STATE_READY;
-	end
-	
+		end
+		
       end
       // branch 3 miss no spill
       STATE_MISS_FETCH_WDV: begin
@@ -238,15 +238,15 @@ module icachefsm
       STATE_MISS_READ_DELAY: begin
         //SelAdr = 2'b01;
         ICacheReadEn = 1'b1;
-	ICacheStallF = 1'b0;
-	LRUWriteEn = 1'b1;
-	if(StallF) begin
-	  SelAdr = 2'b01;
-	  NextState = STATE_CPU_BUSY;
-	  SelAdr = 2'b01;
-	end else begin
+		ICacheStallF = 1'b0;
+		LRUWriteEn = 1'b1;
+		if(StallF) begin
+		  SelAdr = 2'b01;
+		  NextState = STATE_CPU_BUSY;
+		  SelAdr = 2'b01;
+		end else begin
           NextState = STATE_READY;
-	end
+		end
       end
       // branch 4 miss spill hit, and 5 miss spill miss
       STATE_MISS_SPILL_FETCH_WDV: begin
@@ -267,7 +267,7 @@ module icachefsm
       STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
         SelAdr = 2'b01;	 // there is a 1 cycle delay after setting the address before the date arrives.
         ICacheReadEn = 1'b1;
-	LRUWriteEn = 1'b1;
+		LRUWriteEn = 1'b1;
         NextState = STATE_MISS_SPILL_2;
       end
       STATE_MISS_SPILL_2: begin
@@ -284,13 +284,13 @@ module icachefsm
           ICacheReadEn = 1'b1;
           SelAdr = 2'b00;
           ICacheStallF = 1'b0;
-	  LRUWriteEn = 1'b1;
-	  if(StallF) begin
-	    NextState = STATE_CPU_BUSY;
-	    SelAdr = 2'b01;
-	  end else begin
+		  LRUWriteEn = 1'b1;
+		  if(StallF) begin
+			NextState = STATE_CPU_BUSY;
+			SelAdr = 2'b01;
+		  end else begin
             NextState = STATE_READY;
-	  end
+		  end
         end
       end
       STATE_MISS_SPILL_MISS_FETCH_WDV: begin
@@ -317,13 +317,13 @@ module icachefsm
         ICacheReadEn = 1'b1;
         SelAdr = 2'b00;
         ICacheStallF = 1'b0;	
-	LRUWriteEn = 1'b1;
-	if(StallF) begin
-	  NextState = STATE_CPU_BUSY_SPILL;
-	  SelAdr = 2'b10;
-	end else begin
+		LRUWriteEn = 1'b1;
+		if(StallF) begin
+		  NextState = STATE_CPU_BUSY_SPILL;
+		  SelAdr = 2'b10;
+		end else begin
           NextState = STATE_READY;
-	end
+		end
       end
       STATE_TLB_MISS: begin
         if (WalkerInstrPageFaultF) begin
@@ -336,33 +336,33 @@ module icachefsm
         end
       end
       STATE_TLB_MISS_DONE: begin
-	SelAdr = 2'b01;
+		SelAdr = 2'b01;
         NextState = STATE_READY;
       end
       STATE_CPU_BUSY: begin
-	ICacheStallF = 1'b0;
-	if (ITLBMissF) begin
+		ICacheStallF = 1'b0;
+		if (ITLBMissF) begin
           NextState = STATE_TLB_MISS;
-	end else if(StallF) begin
-	  NextState = STATE_CPU_BUSY;
-	  SelAdr = 2'b01;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		end else if(StallF) begin
+		  NextState = STATE_CPU_BUSY;
+		  SelAdr = 2'b01;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
       STATE_CPU_BUSY_SPILL: begin
-	ICacheStallF = 1'b0;
-	ICacheReadEn = 1'b1;
-	if (ITLBMissF) begin
+		ICacheStallF = 1'b0;
+		ICacheReadEn = 1'b1;
+		if (ITLBMissF) begin
           NextState = STATE_TLB_MISS;
-	end else if(StallF) begin
-	  NextState = STATE_CPU_BUSY_SPILL;
-	  SelAdr = 2'b10;
-	end
-	else begin
-	  NextState = STATE_READY;
-	end
+		end else if(StallF) begin
+		  NextState = STATE_CPU_BUSY_SPILL;
+		  SelAdr = 2'b10;
+		end
+		else begin
+		  NextState = STATE_READY;
+		end
       end
       default: begin
         SelAdr = 2'b01;
@@ -374,8 +374,8 @@ module icachefsm
 
   assign CntEn = PreCntEn & InstrAckF;
   assign InstrReadF = (CurrState == STATE_HIT_SPILL_MISS_FETCH_WDV) ||
-		      (CurrState == STATE_MISS_FETCH_WDV) ||
-		      (CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
-		      (CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
+					  (CurrState == STATE_MISS_FETCH_WDV) ||
+					  (CurrState == STATE_MISS_SPILL_FETCH_WDV) ||
+					  (CurrState == STATE_MISS_SPILL_MISS_FETCH_WDV);
   
 endmodule

From 30941c073add4af6844b0d913fcc30f3d913290b Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Dec 2021 18:23:43 -0600
Subject: [PATCH 30/95] Possible fix for icache and ptw interlock deadlock
 issue.

---
 wally-pipelined/src/cache/icachefsm.sv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 33080d9f..b104de4e 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -331,8 +331,10 @@ module icachefsm
           ICacheStallF = 1'b0;
         end else if (ITLBWriteF) begin
           NextState = STATE_TLB_MISS_DONE;
+          ICacheStallF = 1'b1;		  
         end else begin
           NextState = STATE_TLB_MISS;
+		  ICacheStallF = 1'b0;
         end
       end
       STATE_TLB_MISS_DONE: begin

From af9f97454dfa3f98ab900b043bfd0d0b966aa859 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Dec 2021 18:26:54 -0600
Subject: [PATCH 31/95] Cleaned up fpga synthesis script.

---
 addins/riscv-isa-sim                       |   2 +-
 fpga/constraints/constraints.xdc           |  33 -------
 fpga/generator/wally.tcl                   | 101 +--------------------
 fpga/generator/xlnx_ddr4.tcl               |   2 +-
 wally-pipelined/src/cache/icachefsm.sv     |   2 +
 wally-pipelined/src/uncore/uartPC16550D.sv |   6 +-
 6 files changed, 10 insertions(+), 136 deletions(-)

diff --git a/addins/riscv-isa-sim b/addins/riscv-isa-sim
index ddcfa6cc..d22b2801 160000
--- a/addins/riscv-isa-sim
+++ b/addins/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit ddcfa6cc3d80818140a459e590296c3079c5a3ec
+Subproject commit d22b280198e74b871e04fc0ddb622fb825fdae49
diff --git a/fpga/constraints/constraints.xdc b/fpga/constraints/constraints.xdc
index 716136ec..49afd9c5 100644
--- a/fpga/constraints/constraints.xdc
+++ b/fpga/constraints/constraints.xdc
@@ -3,41 +3,8 @@
 # mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
 # This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
 
-# generate 1 clock for the slow speed SD Card hardware. However we need to time at the mmcm_clkout1
-# clock speed.
-
-#create_generated_clock -name r_fd_Q -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/toggle_flip_flop/i_CLK] -divide_by 50 [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/toggle_flip_flop/r_fd_Q]
-
-#create_clock -period 4.000 [get_ports default_250mhz_clk1_0_p]
-
-# need to create a clock for mmcm_clkout1. In the gui flow this was auto generated somehow.
-# turns out this clock is auto generated but has a different name. wtf
-# 10 Mhz
-#create_clock -name mmcm_clkout1 -period 100 [get_pins xlnx_ddr4_c0/addn_ui_clkout1]
-
-#create_generated_clock -name mmcm_clkout1 -source [get_pins xlnx_ddr4_c0/c0_sys_clk_p] -edges {1 2 3} -edge_shift {0.000 48.000 96.000} [get_pins xlnx_ddr4_c0/addn_ui_clkout1]
-
-#create_generated_clock -name mmcm_clkout1 xlnx_ddr4_c0/addn_ui_clkout1
-#create_generated_clock -name mmcm_clkout1 mmcm_clkout1 
-
 create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 [get_pins wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
 
-
-
-#create_generated_clock -name mmcm_clkout1_Gen -source [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -divide_by 1 -add -master_clock mmcm_clkout1 [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
-
-#create_generated_clock -name CLKDiv64_Gen -source [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I1] -divide_by 1 -add -master_clock mmcm_clkout1_Gen [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
-
-
-
-#create_generated_clock -name mmcm_clkout1_Gen_slow -source [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -divide_by 8 -add -master_clock mmcm_clkout1 [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
-
-#create_generated_clock -name CLKDiv64_Gen_slow -source [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I1] -divide_by 8 -add -master_clock mmcm_clkout1_Gen_slow [get_pins wrapper_i/wallypipelinedsocwra_0/inst/wallypipelinedsoc/uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
-
-#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks mmcm_clkout1_Gen] -group [get_clocks -include_generated_clocks CLKDiv64_Gen]
-#set_clock_groups -logically_exclusive -group [get_clocks -include_generated_clocks mmcm_clkout1_Gen] -group [get_clocks -include_generated_clocks CLKDiv64_Gen_slow]
-
-
 ##### GPI ####
 set_property PACKAGE_PIN BB24 [get_ports {GPI[0]}]
 set_property PACKAGE_PIN BF22 [get_ports {GPI[1]}]
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index b9f55c0e..26b3babf 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -19,111 +19,18 @@ read_verilog  {../src/fpgaTop.v}
 
 set_property include_dirs {../../wally-pipelined/config/fpga ../../wally-pipelined/config/shared} [current_fileset]
 
-# contrainsts generated by the IP blocks
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc
-#set_property PROCESSING_ORDER EARLY [get_files  IP/xlnx_ahblite_axi_bridge.gen/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge_ooc.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_ooc.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_1/par/xlnx_ddr4_phy_ooc.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0_board.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_2/bd_1ba7_ilmb_0.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_3/bd_1ba7_dlmb_0.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_1/bd_1ba7_rst_0_0.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_6/bd_1ba7_lmb_bram_I_0_ooc.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_9/bd_1ba7_second_lmb_bram_I_0_ooc.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_10/bd_1ba7_iomodule_0_0_board.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc
-#set_property PROCESSING_ORDER EARLY [get_files  IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/bd_1ba7_ooc.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_board.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc
-#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/xlnx_ddr4_board.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/par/xlnx_ddr4.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_board.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xdc]
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
-
-
-
 add_files -fileset constrs_1 -norecurse ../constraints/constraints.xdc
 set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints.xdc]
 
-# implementation only
-#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc
-#set_property PROCESSING_ORDER LATE [get_files IP/xlnx_axi_clock_converter.gen/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter_clocks.xdc]
-
-
-
-
-
-
-
-
-
-
-
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/bd_0/ip/ip_0/bd_1ba7_microblaze_I_0_ooc_debug.xdc
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ahblite_axi_bridge.runs/xlnx_ahblite_axi_bridge_synth_1/dont_touch.xdc
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_proc_sys_reset.runs/xlnx_proc_sys_reset_synth_1/dont_touch.xdc
-
-
-
-#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/.Xil/xlnx_axi_clock_converter_propImpl.xdc
-#add_files -fileset constrs_1 -norecurse IP/xlnx_axi_clock_converter.runs/xlnx_axi_clock_converter_synth_1/dont_touch.xdc
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.runs/xlnx_ddr4_synth_1/.Xil/xlnx_ddr4_propImpl.xdc
-#add_files -fileset constrs_1 -norecurse IP/xlnx_ddr4.runs/xlnx_ddr4_synth_1/dont_touch.xdc
-
-# constraints for wally top level
-
 # define top level
 set_property top fpgaTop [current_fileset]
 
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_ddr4.gen/sources_1/ip/xlnx_ddr4/ip_0/xlnx_ddr4_microblaze_mcs_ooc.xdc]
-#set_property PROCESSING_ORDER EARLY [get_files IP/xlnx_proc_sys_reset.gen/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset_ooc.xdc]
-
 
 update_compile_order -fileset sources_1
-# this line is wrong vvv
-#update_compile_order -fileset constrs_1
 # This is important as the ddr4 IP contains the generate clock constraint which the user constraints depend on.
+exec mkdir -p reports/
+exec rm -rf reports/*
+
 report_compile_order -constraints > reports/compile_order.rpt
 
 # this is elaboration not synthesis.
@@ -137,8 +44,6 @@ launch_runs synth_1 -jobs 4
 wait_on_run synth_1
 open_run synth_1
 
-exec mkdir -p reports/
-exec rm -rf reports/*
 
 check_timing -verbose                                                   -file reports/check_timing.rpt
 report_timing -max_paths 10 -nworst 10 -delay_type max -sort_by slack   -file reports/timing_WORST_10.rpt
diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl
index 5602ca50..0b5e1a7e 100644
--- a/fpga/generator/xlnx_ddr4.tcl
+++ b/fpga/generator/xlnx_ddr4.tcl
@@ -41,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
 			CONFIG.Reference_Clock {Differential} \
 			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {10} \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {23} \
 			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
 			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
 			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 33080d9f..b104de4e 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -331,8 +331,10 @@ module icachefsm
           ICacheStallF = 1'b0;
         end else if (ITLBWriteF) begin
           NextState = STATE_TLB_MISS_DONE;
+          ICacheStallF = 1'b1;		  
         end else begin
           NextState = STATE_TLB_MISS;
+		  ICacheStallF = 1'b0;
         end
       end
       STATE_TLB_MISS_DONE: begin
diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv
index c6f3d5c1..09d89a2c 100644
--- a/wally-pipelined/src/uncore/uartPC16550D.sv
+++ b/wally-pipelined/src/uncore/uartPC16550D.sv
@@ -138,7 +138,7 @@ module uartPC16550D(
       LSR <= #1 8'b01100000;
       MSR <= #1 4'b0;
       if (`FPGA) begin
-	DLL <= #1 8'd11;
+	DLL <= #1 8'd25;
 	DLM <= #1 8'b0;
       end else begin
 	DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
@@ -154,8 +154,8 @@ module uartPC16550D(
           3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section
           3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
  -----/\----- EXCLUDED -----/\----- */
-	  // *** BUG FIX ME for now for the divider to be 11.  Our clock is 10 Mhz.  10Mhz /(11 * 16) = 56818 baud, which is close enough to 57600 baud
-          3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
+	  // *** BUG FIX ME for now for the divider to be 11.  Our clock is 23 Mhz.  23Mhz /(25 * 16) = 57600 baud, which is close enough to 57600 baud
+          3'b000: if (DLAB) DLL <= #1 8'd25; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
           3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
 
           3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing

From ca404746ecefa03c0d6b344f9c00dfe117f2660c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Dec 2021 18:30:10 -0600
Subject: [PATCH 32/95] Updated .gitignore file to hide fpga outputs.

---
 .gitignore | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/.gitignore b/.gitignore
index b88dfa3e..cd827ed9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -38,3 +38,8 @@ wally-pipelined/regression/slack-notifier/slack-webhook-url.txt
 wally-pipelined/regression/logs
 fpga/generator/IP
 fpga/generator/vivado.*
+fpga/generator/.Xil/*
+fpga/generator/WallyFPGA*
+fpga/generator/reports/
+fpga/generator/*.log
+fpga/generator/*.jou

From 997a733a97310f9e77646ea12d98fc461d9695ec Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 13 Dec 2021 18:36:00 -0600
Subject: [PATCH 33/95] Added patch file for the qemu modifications. Added
 instructions for building and installing qemu.

---
 .../linux-testgen/qemu-build-instructions.md  |  10 +
 .../linux-testgen/wallyVirtIO.patch           | 542 ++++++++++++++++++
 2 files changed, 552 insertions(+)
 create mode 100644 wally-pipelined/linux-testgen/qemu-build-instructions.md
 create mode 100644 wally-pipelined/linux-testgen/wallyVirtIO.patch

diff --git a/wally-pipelined/linux-testgen/qemu-build-instructions.md b/wally-pipelined/linux-testgen/qemu-build-instructions.md
new file mode 100644
index 00000000..8347417b
--- /dev/null
+++ b/wally-pipelined/linux-testgen/qemu-build-instructions.md
@@ -0,0 +1,10 @@
+cd <some directory to download qemu>
+git clone https://github.com/qemu/qemu
+cd qemu
+git checkout dbdc621be937d9efe3e4dff994e54e8eea051f7a
+git apply wallyVirtIO.patch # located in riscv-wally/wally-pipelined/linux-testgen/wallyVirtIO.patch
+sudo apt install ninja-build # or your equivalent
+sudo apt install libglib2.0-dev # or your equivalent
+sudo apt install libpixman-1-dev libcairo2-dev libpango1.0-dev libjpeg8-dev libgif-dev
+./configure --target-list=riscv64-softmmu
+make --jobs
diff --git a/wally-pipelined/linux-testgen/wallyVirtIO.patch b/wally-pipelined/linux-testgen/wallyVirtIO.patch
new file mode 100644
index 00000000..76a1d240
--- /dev/null
+++ b/wally-pipelined/linux-testgen/wallyVirtIO.patch
@@ -0,0 +1,542 @@
+diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+index 4a3cd2599a..39b46e3122 100644
+--- a/hw/riscv/virt.c
++++ b/hw/riscv/virt.c
+@@ -20,6 +20,7 @@
+ 
+ #include "qemu/osdep.h"
+ #include "qemu/units.h"
++#include "qemu/log.h"
+ #include "qemu/error-report.h"
+ #include "qapi/error.h"
+ #include "hw/boards.h"
+@@ -44,19 +45,10 @@
+ #include "hw/display/ramfb.h"
+ 
+ static const MemMapEntry virt_memmap[] = {
+-    [VIRT_DEBUG] =       {        0x0,         0x100 },
+     [VIRT_MROM] =        {     0x1000,        0xf000 },
+-    [VIRT_TEST] =        {   0x100000,        0x1000 },
+-    [VIRT_RTC] =         {   0x101000,        0x1000 },
+     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
+-    [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
+     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+     [VIRT_UART0] =       { 0x10000000,         0x100 },
+-    [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+-    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
+-    [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
+-    [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
+-    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
+     [VIRT_DRAM] =        { 0x80000000,           0x0 },
+ };
+ 
+@@ -67,139 +59,23 @@ static const MemMapEntry virt_memmap[] = {
+ /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
+ #define VIRT64_HIGH_PCIE_MMIO_SIZE  (16 * GiB)
+ 
+-static MemMapEntry virt_high_pcie_memmap;
+-
+ #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
+ 
+-static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
+-                                       const char *name,
+-                                       const char *alias_prop_name)
+-{
+-    /*
+-     * Create a single flash device.  We use the same parameters as
+-     * the flash devices on the ARM virt board.
+-     */
+-    DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
+-
+-    qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
+-    qdev_prop_set_uint8(dev, "width", 4);
+-    qdev_prop_set_uint8(dev, "device-width", 2);
+-    qdev_prop_set_bit(dev, "big-endian", false);
+-    qdev_prop_set_uint16(dev, "id0", 0x89);
+-    qdev_prop_set_uint16(dev, "id1", 0x18);
+-    qdev_prop_set_uint16(dev, "id2", 0x00);
+-    qdev_prop_set_uint16(dev, "id3", 0x00);
+-    qdev_prop_set_string(dev, "name", name);
+-
+-    object_property_add_child(OBJECT(s), name, OBJECT(dev));
+-    object_property_add_alias(OBJECT(s), alias_prop_name,
+-                              OBJECT(dev), "drive");
+-
+-    return PFLASH_CFI01(dev);
+-}
+-
+-static void virt_flash_create(RISCVVirtState *s)
+-{
+-    s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
+-    s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
+-}
+-
+-static void virt_flash_map1(PFlashCFI01 *flash,
+-                            hwaddr base, hwaddr size,
+-                            MemoryRegion *sysmem)
+-{
+-    DeviceState *dev = DEVICE(flash);
+-
+-    assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
+-    assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
+-    qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
+-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+-
+-    memory_region_add_subregion(sysmem, base,
+-                                sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
+-                                                       0));
+-}
+-
+-static void virt_flash_map(RISCVVirtState *s,
+-                           MemoryRegion *sysmem)
+-{
+-    hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
+-    hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
+-
+-    virt_flash_map1(s->flash[0], flashbase, flashsize,
+-                    sysmem);
+-    virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
+-                    sysmem);
+-}
+-
+-static void create_pcie_irq_map(void *fdt, char *nodename,
+-                                uint32_t plic_phandle)
+-{
+-    int pin, dev;
+-    uint32_t
+-        full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
+-    uint32_t *irq_map = full_irq_map;
+-
+-    /* This code creates a standard swizzle of interrupts such that
+-     * each device's first interrupt is based on it's PCI_SLOT number.
+-     * (See pci_swizzle_map_irq_fn())
+-     *
+-     * We only need one entry per interrupt in the table (not one per
+-     * possible slot) seeing the interrupt-map-mask will allow the table
+-     * to wrap to any number of devices.
+-     */
+-    for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
+-        int devfn = dev * 0x8;
+-
+-        for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
+-            int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
+-            int i = 0;
+-
+-            irq_map[i] = cpu_to_be32(devfn << 8);
+-
+-            i += FDT_PCI_ADDR_CELLS;
+-            irq_map[i] = cpu_to_be32(pin + 1);
+-
+-            i += FDT_PCI_INT_CELLS;
+-            irq_map[i++] = cpu_to_be32(plic_phandle);
+-
+-            i += FDT_PLIC_ADDR_CELLS;
+-            irq_map[i] = cpu_to_be32(irq_nr);
+-
+-            irq_map += FDT_INT_MAP_WIDTH;
+-        }
+-    }
+-
+-    qemu_fdt_setprop(fdt, nodename, "interrupt-map",
+-                     full_irq_map, sizeof(full_irq_map));
+-
+-    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
+-                           0x1800, 0, 0, 0x7);
+-}
+-
+ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
+ {
+     void *fdt;
+-    int i, cpu, socket;
++    //int i, cpu, socket;
++    int cpu, socket;
+     MachineState *mc = MACHINE(s);
+     uint64_t addr, size;
+     uint32_t *clint_cells, *plic_cells;
+     unsigned long clint_addr, plic_addr;
+     uint32_t plic_phandle[MAX_NODES];
+-    uint32_t cpu_phandle, intc_phandle, test_phandle;
++    uint32_t cpu_phandle, intc_phandle;
+     uint32_t phandle = 1, plic_mmio_phandle = 1;
+-    uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
+     char *mem_name, *cpu_name, *core_name, *intc_name;
+     char *name, *clint_name, *plic_name, *clust_name;
+-    hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
+-    hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
+-    static const char * const clint_compat[2] = {
+-        "sifive,clint0", "riscv,clint0"
+-    };
+-    static const char * const plic_compat[2] = {
+-        "sifive,plic-1.0.0", "riscv,plic0"
+-    };
+ 
+     if (mc->dtb) {
+         fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
+@@ -305,8 +181,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+             (memmap[VIRT_CLINT].size * socket);
+         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+         qemu_fdt_add_subnode(fdt, clint_name);
+-        qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
+-            (char **)&clint_compat, ARRAY_SIZE(clint_compat));
++        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
+             0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
+         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
+@@ -322,8 +197,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+             "#address-cells", FDT_PLIC_ADDR_CELLS);
+         qemu_fdt_setprop_cell(fdt, plic_name,
+             "#interrupt-cells", FDT_PLIC_INT_CELLS);
+-        qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
+-            (char **)&plic_compat, ARRAY_SIZE(plic_compat));
++        qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
+         qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
+         qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
+             plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+@@ -342,95 +216,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+     for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+         if (socket == 0) {
+             plic_mmio_phandle = plic_phandle[socket];
+-            plic_virtio_phandle = plic_phandle[socket];
+-            plic_pcie_phandle = plic_phandle[socket];
+-        }
+-        if (socket == 1) {
+-            plic_virtio_phandle = plic_phandle[socket];
+-            plic_pcie_phandle = plic_phandle[socket];
+-        }
+-        if (socket == 2) {
+-            plic_pcie_phandle = plic_phandle[socket];
+         }
+     }
+ 
+     riscv_socket_fdt_write_distance_matrix(mc, fdt);
+ 
+-    for (i = 0; i < VIRTIO_COUNT; i++) {
+-        name = g_strdup_printf("/soc/virtio_mmio@%lx",
+-            (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
+-        qemu_fdt_add_subnode(fdt, name);
+-        qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
+-        qemu_fdt_setprop_cells(fdt, name, "reg",
+-            0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
+-            0x0, memmap[VIRT_VIRTIO].size);
+-        qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
+-            plic_virtio_phandle);
+-        qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
+-        g_free(name);
+-    }
+-
+-    name = g_strdup_printf("/soc/pci@%lx",
+-        (long) memmap[VIRT_PCIE_ECAM].base);
+-    qemu_fdt_add_subnode(fdt, name);
+-    qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
+-    qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
+-    qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
+-    qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
+-    qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
+-    qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
+-    qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
+-        memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
+-    qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
+-    qemu_fdt_setprop_cells(fdt, name, "reg", 0,
+-        memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
+-    qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
+-        1, FDT_PCI_RANGE_IOPORT, 2, 0,
+-        2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
+-        1, FDT_PCI_RANGE_MMIO,
+-        2, memmap[VIRT_PCIE_MMIO].base,
+-        2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
+-        1, FDT_PCI_RANGE_MMIO_64BIT,
+-        2, virt_high_pcie_memmap.base,
+-        2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
+-
+-    create_pcie_irq_map(fdt, name, plic_pcie_phandle);
+-    g_free(name);
+-
+-    test_phandle = phandle++;
+-    name = g_strdup_printf("/soc/test@%lx",
+-        (long)memmap[VIRT_TEST].base);
+-    qemu_fdt_add_subnode(fdt, name);
+-    {
+-        static const char * const compat[3] = {
+-            "sifive,test1", "sifive,test0", "syscon"
+-        };
+-        qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
+-                                      ARRAY_SIZE(compat));
+-    }
+-    qemu_fdt_setprop_cells(fdt, name, "reg",
+-        0x0, memmap[VIRT_TEST].base,
+-        0x0, memmap[VIRT_TEST].size);
+-    qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
+-    test_phandle = qemu_fdt_get_phandle(fdt, name);
+-    g_free(name);
+-
+-    name = g_strdup_printf("/soc/reboot");
+-    qemu_fdt_add_subnode(fdt, name);
+-    qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
+-    qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
+-    qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
+-    qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
+-    g_free(name);
+-
+-    name = g_strdup_printf("/soc/poweroff");
+-    qemu_fdt_add_subnode(fdt, name);
+-    qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
+-    qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
+-    qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
+-    qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
+-    g_free(name);
+-
+     name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
+     qemu_fdt_add_subnode(fdt, name);
+     qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
+@@ -445,102 +235,12 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
+     g_free(name);
+ 
+-    name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
+-    qemu_fdt_add_subnode(fdt, name);
+-    qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
+-    qemu_fdt_setprop_cells(fdt, name, "reg",
+-        0x0, memmap[VIRT_RTC].base,
+-        0x0, memmap[VIRT_RTC].size);
+-    qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
+-    qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
+-    g_free(name);
+-
+-    name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
+-    qemu_fdt_add_subnode(mc->fdt, name);
+-    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
+-    qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
+-                                 2, flashbase, 2, flashsize,
+-                                 2, flashbase + flashsize, 2, flashsize);
+-    qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
+-    g_free(name);
+-
+ update_bootargs:
+     if (cmdline) {
+         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+     }
+ }
+ 
+-static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
+-                                          hwaddr ecam_base, hwaddr ecam_size,
+-                                          hwaddr mmio_base, hwaddr mmio_size,
+-                                          hwaddr high_mmio_base,
+-                                          hwaddr high_mmio_size,
+-                                          hwaddr pio_base,
+-                                          DeviceState *plic)
+-{
+-    DeviceState *dev;
+-    MemoryRegion *ecam_alias, *ecam_reg;
+-    MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
+-    qemu_irq irq;
+-    int i;
+-
+-    dev = qdev_new(TYPE_GPEX_HOST);
+-
+-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+-
+-    ecam_alias = g_new0(MemoryRegion, 1);
+-    ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+-    memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
+-                             ecam_reg, 0, ecam_size);
+-    memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
+-
+-    mmio_alias = g_new0(MemoryRegion, 1);
+-    mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+-    memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
+-                             mmio_reg, mmio_base, mmio_size);
+-    memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
+-
+-    /* Map high MMIO space */
+-    high_mmio_alias = g_new0(MemoryRegion, 1);
+-    memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
+-                             mmio_reg, high_mmio_base, high_mmio_size);
+-    memory_region_add_subregion(get_system_memory(), high_mmio_base,
+-                                high_mmio_alias);
+-
+-    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
+-
+-    for (i = 0; i < GPEX_NUM_IRQS; i++) {
+-        irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
+-
+-        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
+-        gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
+-    }
+-
+-    return dev;
+-}
+-
+-static FWCfgState *create_fw_cfg(const MachineState *mc)
+-{
+-    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+-    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+-    FWCfgState *fw_cfg;
+-    char *nodename;
+-
+-    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+-                                  &address_space_memory);
+-    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+-
+-    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+-    qemu_fdt_add_subnode(mc->fdt, nodename);
+-    qemu_fdt_setprop_string(mc->fdt, nodename,
+-                            "compatible", "qemu,fw-cfg-mmio");
+-    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+-                                 2, base, 2, size);
+-    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+-    g_free(nodename);
+-    return fw_cfg;
+-}
+-
+ static void virt_machine_init(MachineState *machine)
+ {
+     const MemMapEntry *memmap = virt_memmap;
+@@ -554,7 +254,7 @@ static void virt_machine_init(MachineState *machine)
+     target_ulong firmware_end_addr, kernel_start_addr;
+     uint32_t fdt_load_addr;
+     uint64_t kernel_entry;
+-    DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
++    DeviceState *mmio_plic;
+     int i, j, base_hartid, hart_count;
+ 
+     /* Check socket count limit */
+@@ -565,7 +265,7 @@ static void virt_machine_init(MachineState *machine)
+     }
+ 
+     /* Initialize sockets */
+-    mmio_plic = virtio_plic = pcie_plic = NULL;
++    mmio_plic = NULL;
+     for (i = 0; i < riscv_socket_count(machine); i++) {
+         if (!riscv_socket_check_hartids(machine, i)) {
+             error_report("discontinuous hartids in socket%d", i);
+@@ -634,15 +334,6 @@ static void virt_machine_init(MachineState *machine)
+         /* Try to use different PLIC instance based device type */
+         if (i == 0) {
+             mmio_plic = s->plic[i];
+-            virtio_plic = s->plic[i];
+-            pcie_plic = s->plic[i];
+-        }
+-        if (i == 1) {
+-            virtio_plic = s->plic[i];
+-            pcie_plic = s->plic[i];
+-        }
+-        if (i == 2) {
+-            pcie_plic = s->plic[i];
+         }
+     }
+ 
+@@ -654,13 +345,6 @@ static void virt_machine_init(MachineState *machine)
+             error_report("Limiting RAM size to 10 GiB");
+         }
+ #endif
+-        virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
+-        virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
+-    } else {
+-        virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
+-        virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
+-        virt_high_pcie_memmap.base =
+-            ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
+     }
+ 
+     /* register system main memory (actual RAM) */
+@@ -681,10 +365,12 @@ static void virt_machine_init(MachineState *machine)
+ 
+     if (riscv_is_32bit(&s->soc[0])) {
+         firmware_end_addr = riscv_find_and_load_firmware(machine,
+-                                    RISCV32_BIOS_BIN, start_addr, NULL);
++                                    "opensbi-riscv32-generic-fw_dynamic.bin",
++                                    start_addr, NULL);
+     } else {
+         firmware_end_addr = riscv_find_and_load_firmware(machine,
+-                                    RISCV64_BIOS_BIN, start_addr, NULL);
++                                    "opensbi-riscv64-generic-fw_dynamic.bin",
++                                    start_addr, NULL);
+     }
+ 
+     if (machine->kernel_filename) {
+@@ -712,21 +398,6 @@ static void virt_machine_init(MachineState *machine)
+         kernel_entry = 0;
+     }
+ 
+-    if (drive_get(IF_PFLASH, 0, 0)) {
+-        /*
+-         * Pflash was supplied, let's overwrite the address we jump to after
+-         * reset to the base of the flash.
+-         */
+-        start_addr = virt_memmap[VIRT_FLASH].base;
+-    }
+-
+-    /*
+-     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+-     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+-     */
+-    s->fw_cfg = create_fw_cfg(machine);
+-    rom_set_fw(s->fw_cfg);
+-
+     /* Compute the fdt load address in dram */
+     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+                                    machine->ram_size, machine->fdt);
+@@ -736,41 +407,10 @@ static void virt_machine_init(MachineState *machine)
+                               virt_memmap[VIRT_MROM].size, kernel_entry,
+                               fdt_load_addr, machine->fdt);
+ 
+-    /* SiFive Test MMIO device */
+-    sifive_test_create(memmap[VIRT_TEST].base);
+-
+-    /* VirtIO MMIO devices */
+-    for (i = 0; i < VIRTIO_COUNT; i++) {
+-        sysbus_create_simple("virtio-mmio",
+-            memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
+-            qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
+-    }
+-
+-    gpex_pcie_init(system_memory,
+-                   memmap[VIRT_PCIE_ECAM].base,
+-                   memmap[VIRT_PCIE_ECAM].size,
+-                   memmap[VIRT_PCIE_MMIO].base,
+-                   memmap[VIRT_PCIE_MMIO].size,
+-                   virt_high_pcie_memmap.base,
+-                   virt_high_pcie_memmap.size,
+-                   memmap[VIRT_PCIE_PIO].base,
+-                   DEVICE(pcie_plic));
+-
+-    serial_mm_init(system_memory, memmap[VIRT_UART0].base,
++   serial_mm_init(system_memory, memmap[VIRT_UART0].base,
+         0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
+         serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ 
+-    sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
+-        qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
+-
+-    virt_flash_create(s);
+-
+-    for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
+-        /* Map legacy -drive if=pflash to machine properties */
+-        pflash_cfi01_legacy_drive(s->flash[i],
+-                                  drive_get(IF_PFLASH, 0, i));
+-    }
+-    virt_flash_map(s, system_memory);
+ }
+ 
+ static void virt_machine_instance_init(Object *obj)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index 991a6bb760..401028b8d9 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -269,6 +269,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
++    
+     if (riscv_has_ext(env, RVH)) {
+         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
+     }

From 2d242300932fb18e59eed1b667f7e214b6b37c0f Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 14 Dec 2021 11:15:47 -0800
Subject: [PATCH 34/95] ALU and datapath cleanup

---
 wally-pipelined/src/ieu/alu.sv      | 85 +++++++++++++++--------------
 wally-pipelined/src/ieu/datapath.sv | 30 ++++------
 wally-pipelined/testbench/tests.vh  |  1 -
 3 files changed, 55 insertions(+), 61 deletions(-)

diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index 2ed6c75d..e2dd7eef 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -26,67 +26,68 @@
 `include "wally-config.vh"
 
 module alu #(parameter WIDTH=32) (
-  input  logic [WIDTH-1:0] a, b,
+  input  logic [WIDTH-1:0] A, B,
   input  logic [2:0]       ALUControl,
   input  logic [2:0]       Funct3,
-  output logic [WIDTH-1:0] result,
-  output logic [WIDTH-1:0] sum);
+  output logic [WIDTH-1:0] Result,
+  output logic [WIDTH-1:0] Sum);
 
-  logic [WIDTH-1:0] condinvb, sumtrunc, shift, slt, sltu, bor;
-  logic        right; //, arith, w64;
-  logic        carry, neg;
-  logic        lt, ltu;
-  logic        overflow;
+  logic [WIDTH-1:0] CondInvB, SumTrunc, Shift, SLT, SLTU, bor;
+  logic        Right;
+  logic        Carry, Neg;
+  logic        LT, LTU;
+  logic        Overflow;
   logic        W64, SubArith, ALUOp;
+  logic [2:0]  ALUFunct;
 
+  // Extract control signals
+  // W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
+  // SubArith indicates subtraction
+  // ALUOp = 0 for address generation addition or 1 for regular ALU
   assign {W64, SubArith, ALUOp} = ALUControl;
+
   // addition
-  // *** make sure condinvb is only applied when it should be (sub, slt/sltu)
-  assign condinvb = SubArith ? ~b : b;
-  assign {carry, sum} = a + condinvb + {{(WIDTH-1){1'b0}}, SubArith};
+  assign CondInvB = SubArith ? ~B : B;
+  assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
   // support W-type RV64I ADDW/SUBW/ADDIW that sign-extend 32-bit result to 64 bits
   generate
     if (WIDTH==64)
-      assign sumtrunc = W64 ? {{32{sum[31]}}, sum[31:0]} : sum;
+      assign SumTrunc = W64 ? {{32{Sum[31]}}, Sum[31:0]} : Sum;
     else
-      assign sumtrunc = sum;
+      assign SumTrunc = Sum;
   endgenerate
   
-  // shifts
- // assign arith = alucontrol[3]; // sra
- // assign w64 = alucontrol[4];
-  assign right = (Funct3[2:0] == 3'b101); // sra or srl
-  shifter sh(a, b[5:0], right, SubArith, W64, shift);
-  
-  // OR optionally passes zero when ALUControl[3] is set, supporting lui
-  // *** not needed anymore; simplify control
-  //assign bor = alucontrol[3] ? b : a|b;
+  // Shifts
+  // assign arith = alucontrol[3]; // sra
+  // assign w64 = alucontrol[4];
+  assign Right = (Funct3[2:0] == 3'b101); // sra or srl
+  shifter sh(A, B[5:0], Right, SubArith, W64, Shift);
   
   // condition code flags based on add/subtract output
-  assign neg  = sum[WIDTH-1];
-  // overflow occurs when the numbers being added have the same sign 
+  // Overflow occurs when the numbers being added have the same sign 
   // and the result has the opposite sign
-  assign overflow = (a[WIDTH-1] ~^ condinvb[WIDTH-1]) & (a[WIDTH-1] ^ sum[WIDTH-1]);
-  assign lt = neg ^ overflow;
-  assign ltu = ~carry;
+  assign Overflow = (A[WIDTH-1] ~^ CondInvB[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
+  assign Neg  = Sum[WIDTH-1];
+  assign LT = Neg ^ Overflow;
+  assign LTU = ~Carry;
  
-  // slt
-  assign slt = {{(WIDTH-1){1'b0}}, lt};
-  assign sltu = {{(WIDTH-1){1'b0}}, ltu};
+  // SLT
+  assign SLT = {{(WIDTH-1){1'b0}}, LT};
+  assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
  
+  // Select appropriate ALU Result
+  assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
   always_comb
-    if (~ALUOp) result = sumtrunc;
-    else 
-      case (Funct3)
-        3'b000: result = sumtrunc;       // add or sub
-        3'b001: result = shift;     // sll
-        3'b010: result = slt;       // slt
-        3'b011: result = sltu;      // sltu
-        3'b100: result = a ^ b;     // xor
-        3'b101: result = shift;     // sra or srl
-        3'b110: result = a | b;     // or 
-        3'b111: result = a & b;     // and
-      endcase
+    case (ALUFunct)
+      3'b000: Result = SumTrunc;  // add or sub
+      3'b001: Result = Shift;     // sll
+      3'b010: Result = SLT;       // slt
+      3'b011: Result = SLTU;      // sltu
+      3'b100: Result = A ^ B;     // xor
+      3'b101: Result = Shift;     // sra or srl
+      3'b110: Result = A | B;     // or 
+      3'b111: Result = A & B;     // and
+    endcase
 endmodule
 
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index b0645f81..83c1f918 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -93,9 +93,7 @@ module datapath (
   assign Rs1D      = InstrD[19:15];
   assign Rs2D      = InstrD[24:20];
   assign RdD       = InstrD[11:7];
-
-  //Mux for writting floating point 
-  
+  // *** can FWriteIntW be merged with RegWriteW
   regfile regf(clk, reset, {RegWriteW | FWriteIntW}, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
   extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
  
@@ -103,9 +101,9 @@ module datapath (
   flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E);
   flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, RD2D, RD2E);
   flopenrc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ~StallE, ExtImmD, ExtImmE);
-  flopenrc #(5)    Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
-  flopenrc #(5)    Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
-  flopenrc #(5)    RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
+  flopenrc #(5)     Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
+  flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
+  flopenrc #(5)     RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
 	
   mux3  #(`XLEN)  faemux(RD1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);
   mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
@@ -114,35 +112,31 @@ module datapath (
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
   alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUPreResultE, AddressE);
   comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
-  mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
-  mux2 #(`XLEN) aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE);
+  mux2 #(`XLEN)   altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
+  mux2 #(`XLEN)   aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE);
 
   // Memory stage pipeline register
   flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
   flopenrc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ~StallM, ALUResultE, ALUResultM);
   assign MemAdrE = AddressE;   // *** clean up this naming
   assign PCTargetE = AddressE; // *** clean up this naming
-  flopenrc #(`XLEN) AddressNReg(clk, reset, FlushM, ~StallM, MemAdrE, MemAdrM);
+  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, MemAdrE, MemAdrM);
   flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
-  flopenrc #(5)    RdMEg(clk, reset, FlushM, ~StallM, RdE, RdM);	
-  mux2  #(`XLEN)   resultmuxM(ALUResultM, FIntResM, FWriteIntM, ResultM);
+  flopenrc #(5)     RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);	
+  mux2  #(`XLEN)    resultmuxM(ALUResultM, FIntResM, FWriteIntM, ResultM);
   
   // Writeback stage pipeline register and logic
   flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW);
-  flopenrc #(5)    RdWEg(clk, reset, FlushW, ~StallW, RdM, RdW);
+  flopenrc #(5)     RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
+  flopen #(`XLEN)   ReadDataWReg(.clk, .en(~StallW), .d(ReadDataM), .q(ReadDataW));
 
   // handle Store Conditional result if atomic extension supported
   generate
     if (`A_SUPPORTED)
-      assign SCResultW = SquashSCW ? {{(`XLEN-1){1'b0}}, 1'b1} : {{(`XLEN-1){1'b0}}, 1'b0};
+      assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
     else 
       assign SCResultW = 0;
   endgenerate
 
-  flopen #(`XLEN) ReadDataWReg(.clk(clk),
-			      .en(~StallW),
-			      .d(ReadDataM),
-			      .q(ReadDataW));
-
   mux5  #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);	 
 endmodule
diff --git a/wally-pipelined/testbench/tests.vh b/wally-pipelined/testbench/tests.vh
index ec3a5315..a12f9699 100644
--- a/wally-pipelined/testbench/tests.vh
+++ b/wally-pipelined/testbench/tests.vh
@@ -586,7 +586,6 @@ string imperas32f[] = '{
 
   string arch64i[] = '{
     `RISCVARCHTEST,
-    "rv64i_m/I/beq-01", "47010",
     "rv64i_m/I/add-01", "9010",
     "rv64i_m/I/addi-01", "6010",
     "rv64i_m/I/addiw-01", "6010",

From 8dcf2c65f2dbffe99a961787b77e209f2847a596 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 14 Dec 2021 11:22:00 -0800
Subject: [PATCH 35/95] renamed rv32/64g to rv32/64gc in configuration

---
 wally-pipelined/config/{rv32g => rv32gc}/BTBPredictor.txt    | 0
 wally-pipelined/config/{rv32g => rv32gc}/twoBitPredictor.txt | 0
 wally-pipelined/config/{rv32g => rv32gc}/wally-config.vh     | 0
 wally-pipelined/config/{rv64g => rv64gc}/BTBPredictor.txt    | 0
 wally-pipelined/config/{rv64g => rv64gc}/twoBitPredictor.txt | 0
 wally-pipelined/config/{rv64g => rv64gc}/wally-config.vh     | 0
 wally-pipelined/regression/lint-wally                        | 2 +-
 wally-pipelined/regression/regression-wally.py               | 4 ++--
 wally-pipelined/regression/sim-fp64-batch                    | 2 +-
 wally-pipelined/regression/wally-fp64.do                     | 2 +-
 10 files changed, 5 insertions(+), 5 deletions(-)
 rename wally-pipelined/config/{rv32g => rv32gc}/BTBPredictor.txt (100%)
 rename wally-pipelined/config/{rv32g => rv32gc}/twoBitPredictor.txt (100%)
 rename wally-pipelined/config/{rv32g => rv32gc}/wally-config.vh (100%)
 rename wally-pipelined/config/{rv64g => rv64gc}/BTBPredictor.txt (100%)
 rename wally-pipelined/config/{rv64g => rv64gc}/twoBitPredictor.txt (100%)
 rename wally-pipelined/config/{rv64g => rv64gc}/wally-config.vh (100%)

diff --git a/wally-pipelined/config/rv32g/BTBPredictor.txt b/wally-pipelined/config/rv32gc/BTBPredictor.txt
similarity index 100%
rename from wally-pipelined/config/rv32g/BTBPredictor.txt
rename to wally-pipelined/config/rv32gc/BTBPredictor.txt
diff --git a/wally-pipelined/config/rv32g/twoBitPredictor.txt b/wally-pipelined/config/rv32gc/twoBitPredictor.txt
similarity index 100%
rename from wally-pipelined/config/rv32g/twoBitPredictor.txt
rename to wally-pipelined/config/rv32gc/twoBitPredictor.txt
diff --git a/wally-pipelined/config/rv32g/wally-config.vh b/wally-pipelined/config/rv32gc/wally-config.vh
similarity index 100%
rename from wally-pipelined/config/rv32g/wally-config.vh
rename to wally-pipelined/config/rv32gc/wally-config.vh
diff --git a/wally-pipelined/config/rv64g/BTBPredictor.txt b/wally-pipelined/config/rv64gc/BTBPredictor.txt
similarity index 100%
rename from wally-pipelined/config/rv64g/BTBPredictor.txt
rename to wally-pipelined/config/rv64gc/BTBPredictor.txt
diff --git a/wally-pipelined/config/rv64g/twoBitPredictor.txt b/wally-pipelined/config/rv64gc/twoBitPredictor.txt
similarity index 100%
rename from wally-pipelined/config/rv64g/twoBitPredictor.txt
rename to wally-pipelined/config/rv64gc/twoBitPredictor.txt
diff --git a/wally-pipelined/config/rv64g/wally-config.vh b/wally-pipelined/config/rv64gc/wally-config.vh
similarity index 100%
rename from wally-pipelined/config/rv64g/wally-config.vh
rename to wally-pipelined/config/rv64gc/wally-config.vh
diff --git a/wally-pipelined/regression/lint-wally b/wally-pipelined/regression/lint-wally
index a61624aa..23f239c1 100755
--- a/wally-pipelined/regression/lint-wally
+++ b/wally-pipelined/regression/lint-wally
@@ -5,7 +5,7 @@ export PATH=$PATH:/usr/local/bin/
 verilator=`which verilator`
 
 basepath=$(dirname $0)/..
-for config in rv64g rv32g; do
+for config in rv64gc rv32gc; do
     echo "$config linting..."
     if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then
         echo "Exiting after $config lint due to errors or warnings"
diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py
index a0591d6a..4c78e1a8 100755
--- a/wally-pipelined/regression/regression-wally.py
+++ b/wally-pipelined/regression/regression-wally.py
@@ -53,7 +53,7 @@ tests64 = ["wally64i", "arch64i", "arch64priv", "arch64c",  "arch64m", "imperas6
 for test in tests64:
   tc = TestCase(
         name=test,
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64g "+test+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv64gc "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
 #tests32 = ["arch32i", "arch32priv", "arch32c",  "arch32m", "arch32f", "imperas32i", "imperas32p", "imperas32mmu", "imperas32f", "imperas32m", "imperas32a",  "imperas32c"]
@@ -61,7 +61,7 @@ tests32 = ["wally32i", "arch32i", "arch32priv", "arch32c",  "arch32m", "imperas3
 for test in tests32:
   tc = TestCase(
         name=test,
-        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32g "+test+"\n!",
+        cmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do rv32gc "+test+"\n!",
         grepstr="All tests ran without failures")
   configs.append(tc)
 
diff --git a/wally-pipelined/regression/sim-fp64-batch b/wally-pipelined/regression/sim-fp64-batch
index 693bfeb2..226d0586 100755
--- a/wally-pipelined/regression/sim-fp64-batch
+++ b/wally-pipelined/regression/sim-fp64-batch
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-fp64-batch.do rv64g imperas64d
+do wally-fp64-batch.do rv64gc imperas64d
 !
diff --git a/wally-pipelined/regression/wally-fp64.do b/wally-pipelined/regression/wally-fp64.do
index c131ff16..96c6d61f 100644
--- a/wally-pipelined/regression/wally-fp64.do
+++ b/wally-pipelined/regression/wally-fp64.do
@@ -37,7 +37,7 @@ vlib work
 #}
 # start and run simulation
 # remove +acc flag for faster sim during regressions if there is no need to access internal signals
-vlog +incdir+../config/rv64g +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv   ../src/*/*.sv -suppress 2583
+vlog +incdir+../config/rv64gc +incdir+../config/shared ../testbench/testbench-f64.sv ../testbench/common/*.sv   ../src/*/*.sv -suppress 2583
 vopt +acc work.testbench -G TEST=imperas64d -o workopt 
 vsim workopt
 

From 9886ed3028e4e92084ddae0381db93a15655f94f Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 14 Dec 2021 14:46:29 -0600
Subject: [PATCH 36/95] Comments for dcache and icache refactoring.

---
 wally-pipelined/src/ifu/ifu.sv |  5 +++++
 wally-pipelined/src/lsu/lsu.sv | 10 +++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index c0bfaaf8..b5455352 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -115,6 +115,7 @@ module ifu (
   endgenerate
 
   assign PCFExt = {2'b00, PCF};
+  //
   mmu #(.TLB_ENTRIES(`ITLB_ENTRIES), .IMMU(1))
   immu(.PAdr(PCFExt[`PA_BITS-1:0]),
        .VAdr(PCF),
@@ -158,6 +159,10 @@ module ifu (
   //assign InstrReadF = ~StallD; // *** & ICacheMissF; add later
   // assign InstrReadF = 1; // *** & ICacheMissF; add later
 
+  // conditional
+  // 1. dtim // controlled by `MEM_IROM
+  // 2. cache // `MEM_ICACHE
+  // 3. wire pass-through
   icache icache(.clk, .reset, .StallF, .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
   .InstrPAdrF, .InstrReadF, .CompressedF, .ICacheStallF, .ITLBMissF, .ITLBWriteF, .FinalInstrRawF,
 
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 75ae4ccd..01fcb733 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -128,7 +128,9 @@ module lsu
   logic 		       MemAfterIWalkDone;
 
   assign AnyCPUReqM = (|MemRWM)  | (|AtomicM);
-  
+
+  // *** add generate to conditionally create hptw, lsuArb, and mmu
+  // based on `MEM_VIRTMEM
   hptw hptw(.clk(clk),
 	    .reset(reset),
 	    .SATP_REGW(SATP_REGW),
@@ -210,6 +212,7 @@ module lsu
        ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
 
 
+  // Move generate from lrsc to outside this module.
   assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
   lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
             .SquashSCW, .MemRWMtoDCache);
@@ -219,6 +222,7 @@ module lsu
   
 
   // Specify which type of page fault is occurring
+  // *** `MEM_VIRTMEM
   assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWMtoLRSC[1];
   assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0];
 
@@ -235,6 +239,10 @@ module lsu
   assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1];
   assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0];
 
+  // conditional
+  // 1. dtim // controlled by `MEM_DTIM
+  // 2. cache `MEM_DCACHE
+  // 3. wire pass-through
   dcache dcache(.clk(clk),
 		.reset(reset),
 		.StallWtoDCache(StallWtoDCache),

From ecce1e62ee472dbad732b6d65ddcf91cf719a295 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 14 Dec 2021 13:05:32 -0800
Subject: [PATCH 37/95] changed ideal memory to MEM_DTIM and MEM_ITIM

---
 wally-pipelined/config/buildroot/wally-config.vh     | 5 +++--
 wally-pipelined/config/busybear/wally-config.vh      | 3 ++-
 wally-pipelined/config/coremark/wally-config.vh      | 8 ++++----
 wally-pipelined/config/coremark_bare/wally-config.vh | 6 +++---
 wally-pipelined/config/fpga/wally-config.vh          | 5 +++--
 wally-pipelined/config/rv32gc/wally-config.vh        | 5 +++--
 wally-pipelined/config/rv32ic/wally-config.vh        | 5 +++--
 wally-pipelined/config/rv64BP/wally-config.vh        | 5 +++--
 wally-pipelined/config/rv64gc/wally-config.vh        | 7 ++++---
 wally-pipelined/config/rv64ic/wally-config.vh        | 5 +++--
 wally-pipelined/regression/sim-wally                 | 2 +-
 11 files changed, 32 insertions(+), 24 deletions(-)

diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh
index d2b532b2..9ec59f62 100644
--- a/wally-pipelined/config/buildroot/wally-config.vh
+++ b/wally-pipelined/config/buildroot/wally-config.vh
@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index b248c58a..e969f1b0 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -48,8 +48,9 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh
index ceb546ff..b02a4a7f 100644
--- a/wally-pipelined/config/coremark/wally-config.vh
+++ b/wally-pipelined/config/coremark/wally-config.vh
@@ -43,16 +43,16 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define DESIGN_COMPILER 0
 
-
 // Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
-`define MEM_VIRTMEM 0
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define MEM_VIRTMEM 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh
index 0adca26b..ddde51f0 100644
--- a/wally-pipelined/config/coremark_bare/wally-config.vh
+++ b/wally-pipelined/config/coremark_bare/wally-config.vh
@@ -44,16 +44,16 @@
 `define ZICOUNTERS_SUPPORTED 1
 `define DESIGN_COMPILER 0
 
-
 // Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/fpga/wally-config.vh b/wally-pipelined/config/fpga/wally-config.vh
index 87204543..909125f8 100644
--- a/wally-pipelined/config/fpga/wally-config.vh
+++ b/wally-pipelined/config/fpga/wally-config.vh
@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv32gc/wally-config.vh b/wally-pipelined/config/rv32gc/wally-config.vh
index 00698120..7f4b1064 100644
--- a/wally-pipelined/config/rv32gc/wally-config.vh
+++ b/wally-pipelined/config/rv32gc/wally-config.vh
@@ -46,11 +46,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh
index b4841773..1c62f513 100644
--- a/wally-pipelined/config/rv32ic/wally-config.vh
+++ b/wally-pipelined/config/rv32ic/wally-config.vh
@@ -46,11 +46,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh
index 24690158..8105f1a4 100644
--- a/wally-pipelined/config/rv64BP/wally-config.vh
+++ b/wally-pipelined/config/rv64BP/wally-config.vh
@@ -48,11 +48,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv64gc/wally-config.vh b/wally-pipelined/config/rv64gc/wally-config.vh
index d8378ab9..b4563132 100644
--- a/wally-pipelined/config/rv64gc/wally-config.vh
+++ b/wally-pipelined/config/rv64gc/wally-config.vh
@@ -43,15 +43,16 @@
 `define COUNTERS 32
 `define ZICOUNTERS_SUPPORTED 1
 
-// Microarchitectural Features
+/// Microarchitectural Features
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index afd2e8d6..31fcc0f2 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -47,11 +47,12 @@
 `define UARCH_PIPELINED 1
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
 `define MEM_DTIM 1
+`define MEM_DCACHE 1
+`define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
diff --git a/wally-pipelined/regression/sim-wally b/wally-pipelined/regression/sim-wally
index d3071bd1..422fb77e 100755
--- a/wally-pipelined/regression/sim-wally
+++ b/wally-pipelined/regression/sim-wally
@@ -1,2 +1,2 @@
-vsim -do "do wally-pipelined.do rv64g arch64i"
+vsim -do "do wally-pipelined.do rv64gc arch64i"
 

From 865d5ce0b16e7c7171040379f5706e1dc86f24d5 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 14 Dec 2021 13:43:06 -0800
Subject: [PATCH 38/95] Renamed dtim->ram and boottim ->bootrom

---
 .../config/buildroot/wally-config.vh          |   12 +-
 .../config/busybear/wally-config.vh           |   18 +-
 .../config/coremark/wally-config.vh           |   12 +-
 .../config/coremark_bare/wally-config.vh      |   12 +-
 wally-pipelined/config/fpga/wally-config.vh   |   12 +-
 .../config/old/rv32icfd/BTBPredictor.txt      | 1024 -----------------
 .../config/old/rv32icfd/twoBitPredictor.txt   | 1024 -----------------
 .../config/old/rv32icfd/wally-config.vh       |  126 --
 .../config/old/rv64icfd/BTBPredictor.txt      | 1024 -----------------
 .../config/old/rv64icfd/twoBitPredictor.txt   | 1024 -----------------
 .../config/old/rv64icfd/wally-config.vh       |  128 ---
 .../config/old/rv64imc/BTBPredictor.txt       | 1024 -----------------
 .../config/old/rv64imc/twoBitPredictor.txt    | 1024 -----------------
 .../config/old/rv64imc/wally-config.vh        |  122 --
 wally-pipelined/config/rv32gc/wally-config.vh |   12 +-
 wally-pipelined/config/rv32ic/wally-config.vh |   12 +-
 wally-pipelined/config/rv64BP/wally-config.vh |   12 +-
 wally-pipelined/config/rv64gc/wally-config.vh |   12 +-
 wally-pipelined/config/rv64ic/wally-config.vh |   12 +-
 wally-pipelined/regression/fpga-wave.do       |   38 +-
 wally-pipelined/regression/sim-wally-batch    |    2 +-
 wally-pipelined/regression/wally-coremark.do  |    6 +-
 .../regression/wally-pipelined-fpga.do        |   14 +-
 wally-pipelined/regression/wave-all.do        |   28 +-
 .../regression/wave-dos/ahb-muldiv.do         |    6 +-
 .../regression/wave-dos/ahb-waves.do          |    6 +-
 .../regression/wave-dos/cache-waves.do        |    2 +-
 .../regression/wave-dos/default-waves.do      |    2 +-
 .../regression/wave-dos/peripheral-waves.do   |    2 +-
 wally-pipelined/src/ifu/ifu.sv                |    2 +-
 wally-pipelined/src/lsu/lsu.sv                |    2 +-
 wally-pipelined/src/mmu/adrdecs.sv            |    4 +-
 .../src/uncore/{dtim.sv => ram.sv}            |   50 +-
 wally-pipelined/src/uncore/uncore.sv          |   54 +-
 .../testbench/testbench-coremark.sv           |    4 +-
 .../testbench/testbench-coremark_bare.sv      |    6 +-
 wally-pipelined/testbench/testbench-fpga.sv   |   26 +-
 wally-pipelined/testbench/testbench-linux.sv  |   18 +-
 .../testbench/testbench-privileged.sv         |   12 +-
 wally-pipelined/testbench/testbench.sv        |   22 +-
 40 files changed, 216 insertions(+), 6736 deletions(-)
 delete mode 100644 wally-pipelined/config/old/rv32icfd/BTBPredictor.txt
 delete mode 100644 wally-pipelined/config/old/rv32icfd/twoBitPredictor.txt
 delete mode 100644 wally-pipelined/config/old/rv32icfd/wally-config.vh
 delete mode 100644 wally-pipelined/config/old/rv64icfd/BTBPredictor.txt
 delete mode 100644 wally-pipelined/config/old/rv64icfd/twoBitPredictor.txt
 delete mode 100644 wally-pipelined/config/old/rv64icfd/wally-config.vh
 delete mode 100644 wally-pipelined/config/old/rv64imc/BTBPredictor.txt
 delete mode 100644 wally-pipelined/config/old/rv64imc/twoBitPredictor.txt
 delete mode 100644 wally-pipelined/config/old/rv64imc/wally-config.vh
 rename wally-pipelined/src/uncore/{dtim.sv => ram.sv} (81%)

diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh
index 9ec59f62..1bf19b54 100644
--- a/wally-pipelined/config/buildroot/wally-config.vh
+++ b/wally-pipelined/config/buildroot/wally-config.vh
@@ -81,12 +81,12 @@
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   56'h00001000 
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h07FFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h07FFFFFF
 `define EXT_MEM_SUPPORTED 1'b0
 `define EXT_MEM_BASE       56'h80000000
 `define EXT_MEM_RANGE      56'h07FFFFFF
diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh
index e969f1b0..fc2868ec 100644
--- a/wally-pipelined/config/busybear/wally-config.vh
+++ b/wally-pipelined/config/busybear/wally-config.vh
@@ -53,7 +53,7 @@
 `define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
+`define VECTORED_INTERRUPTS_SUPPORTED 1 
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
@@ -83,14 +83,14 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIM_SUPPORTED 1'b1
-//`define BOOTTIM_BASE   56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-//`define BOOTTIM_RANGE  56'h00003FFF
-`define BOOTTIM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h07FFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+//`define BOOTROM_BASE   56'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+//`define BOOTROM_RANGE  56'h00003FFF
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h07FFFFFF
 `define EXT_MEM_SUPPORTED 1'b0
 `define EXT_MEM_BASE       56'h80000000
 `define EXT_MEM_RANGE      56'h07FFFFFF
diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh
index b02a4a7f..f26b6d2a 100644
--- a/wally-pipelined/config/coremark/wally-config.vh
+++ b/wally-pipelined/config/coremark/wally-config.vh
@@ -85,12 +85,12 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   34'h00001000 
-`define BOOTTIM_RANGE  34'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       34'h80000000
-`define TIM_RANGE      34'h07FFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       34'h80000000
+`define RAM_RANGE      34'h07FFFFFF
 `define EXT_MEM_SUPPORTED 1'b0
 `define EXT_MEM_BASE       56'h80000000
 `define EXT_MEM_RANGE      56'h07FFFFFF
diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh
index ddde51f0..c357af64 100644
--- a/wally-pipelined/config/coremark_bare/wally-config.vh
+++ b/wally-pipelined/config/coremark_bare/wally-config.vh
@@ -85,12 +85,12 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   56'h00001000 
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h07FFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h07FFFFFF
 `define CLINT_SUPPORTED 1'b1
 `define CLINT_BASE  56'h02000000
 `define CLINT_RANGE 56'h0000FFFF
diff --git a/wally-pipelined/config/fpga/wally-config.vh b/wally-pipelined/config/fpga/wally-config.vh
index 909125f8..2e6b0494 100644
--- a/wally-pipelined/config/fpga/wally-config.vh
+++ b/wally-pipelined/config/fpga/wally-config.vh
@@ -81,13 +81,13 @@
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   56'h00001000 
-`define BOOTTIM_RANGE  56'h00000FFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 
+`define BOOTROM_RANGE  56'h00000FFF
 
-`define TIM_SUPPORTED 1'b0
-`define TIM_BASE       56'h100000000
-`define TIM_RANGE      56'h07FFFFFF
+`define RAM_SUPPORTED 1'b0
+`define RAM_BASE       56'h100000000
+`define RAM_RANGE      56'h07FFFFFF
 
 `define EXT_MEM_SUPPORTED 1'b1
 `define EXT_MEM_BASE       56'h80000000
diff --git a/wally-pipelined/config/old/rv32icfd/BTBPredictor.txt b/wally-pipelined/config/old/rv32icfd/BTBPredictor.txt
deleted file mode 100644
index fd3eedff..00000000
--- a/wally-pipelined/config/old/rv32icfd/BTBPredictor.txt
+++ /dev/null
@@ -1,1024 +0,0 @@
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
-000000000000000000000000000000000000
diff --git a/wally-pipelined/config/old/rv32icfd/twoBitPredictor.txt b/wally-pipelined/config/old/rv32icfd/twoBitPredictor.txt
deleted file mode 100644
index ff57bd47..00000000
--- a/wally-pipelined/config/old/rv32icfd/twoBitPredictor.txt
+++ /dev/null
@@ -1,1024 +0,0 @@
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
diff --git a/wally-pipelined/config/old/rv32icfd/wally-config.vh b/wally-pipelined/config/old/rv32icfd/wally-config.vh
deleted file mode 100644
index 0924c864..00000000
--- a/wally-pipelined/config/old/rv32icfd/wally-config.vh
+++ /dev/null
@@ -1,126 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-
-`define QEMU 0
-`define BUILDROOT 0
-`define BUSYBEAR 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 32
-
-`define MISA (32'h00000104 | 1 << 5 | 1 << 20 | 1 << 18 | 1 << 12)
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
-`define MEM_DTIM 1
-`define MEM_ICACHE 1
-`define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 2048
-`define DCACHE_BLOCKLENINBITS 256
-`define DCACHE_REPLBITS 3
-`define ICACHE_NUMWAYS 1
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_BLOCKLENINBITS 256
-
-// Integer Divider Configuration
-// DIV_BITSPERCYCLE must be 1, 2, or 4
-`define DIV_BITSPERCYCLE 4
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 16
-
-// Address space
-`define RESET_VECTOR 32'h80000000
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   34'h00001000 
-`define BOOTTIM_RANGE  34'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       34'h80000000
-`define TIM_RANGE      34'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  34'h02000000
-`define CLINT_RANGE 34'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   34'h10012000
-`define GPIO_RANGE  34'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   34'h10000000
-`define UART_RANGE  34'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   34'h0C000000
-`define PLIC_RANGE  34'h03FFFFFF
-`define SDC_SUPPORTED 1'b1
-`define SDC_BASE   34'h00012100
-`define SDC_RANGE  34'h0000001F
-
-// Bus Interface width
-`define AHBW 32
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 4
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 4
-
-`define TWO_BIT_PRELOAD "../config/rv32icfd/twoBitPredictor.txt"
-`define BTB_PRELOAD "../config/rv32icfd/BTBPredictor.txt"
-`define BPRED_ENABLED 1
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
-`define TESTSBP 0
diff --git a/wally-pipelined/config/old/rv64icfd/BTBPredictor.txt b/wally-pipelined/config/old/rv64icfd/BTBPredictor.txt
deleted file mode 100644
index b761147c..00000000
--- a/wally-pipelined/config/old/rv64icfd/BTBPredictor.txt
+++ /dev/null
@@ -1,1024 +0,0 @@
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
diff --git a/wally-pipelined/config/old/rv64icfd/twoBitPredictor.txt b/wally-pipelined/config/old/rv64icfd/twoBitPredictor.txt
deleted file mode 100644
index ff57bd47..00000000
--- a/wally-pipelined/config/old/rv64icfd/twoBitPredictor.txt
+++ /dev/null
@@ -1,1024 +0,0 @@
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
diff --git a/wally-pipelined/config/old/rv64icfd/wally-config.vh b/wally-pipelined/config/old/rv64icfd/wally-config.vh
deleted file mode 100644
index 6d60c754..00000000
--- a/wally-pipelined/config/old/rv64icfd/wally-config.vh
+++ /dev/null
@@ -1,128 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: Brett Mathis
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-// include shared configuration
-`include "wally-shared.vh"
-//  `include "../shared/wally-shared.vh"
-
-`define QEMU 0
-`define BUILDROOT 0
-`define BUSYBEAR 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-// MISA RISC-V configuration per specification
-`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
-`define MEM_DTIM 1
-`define MEM_ICACHE 1
-`define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 4096
-`define DCACHE_BLOCKLENINBITS 256
-`define DCACHE_REPLBITS 3
-`define ICACHE_NUMWAYS 4
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_BLOCKLENINBITS 256
-
-// Integer Divider Configuration
-// DIV_BITSPERCYCLE must be 1, 2, or 4
-`define DIV_BITSPERCYCLE 4
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 64
-
-// Address space
-`define RESET_VECTOR 64'h80000000
-
-// Peripheral Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   56'h00001000 
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   56'h10012000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-`define SDC_SUPPORTED 1'b1
-`define SDC_BASE   56'h00012100
-`define SDC_RANGE  56'h0000001F
-
-// Bus Interface width
-`define AHBW 64
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 1
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 4
-// comment out the following if >=32 sources
-`define PLIC_NUM_SRC_LT_32
-`define PLIC_GPIO_ID 3
-`define PLIC_UART_ID 4
-
-`define TWO_BIT_PRELOAD "../config/rv64icfd/twoBitPredictor.txt"
-`define BTB_PRELOAD "../config/rv64icfd/BTBPredictor.txt"
-
-`define BPRED_ENABLED 1
-`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
-`define TESTSBP 0
diff --git a/wally-pipelined/config/old/rv64imc/BTBPredictor.txt b/wally-pipelined/config/old/rv64imc/BTBPredictor.txt
deleted file mode 100644
index b761147c..00000000
--- a/wally-pipelined/config/old/rv64imc/BTBPredictor.txt
+++ /dev/null
@@ -1,1024 +0,0 @@
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
-00000000000000000000000000000000000000000000000000000000000000000000
diff --git a/wally-pipelined/config/old/rv64imc/twoBitPredictor.txt b/wally-pipelined/config/old/rv64imc/twoBitPredictor.txt
deleted file mode 100644
index ff57bd47..00000000
--- a/wally-pipelined/config/old/rv64imc/twoBitPredictor.txt
+++ /dev/null
@@ -1,1024 +0,0 @@
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
-00
diff --git a/wally-pipelined/config/old/rv64imc/wally-config.vh b/wally-pipelined/config/old/rv64imc/wally-config.vh
deleted file mode 100644
index f9240825..00000000
--- a/wally-pipelined/config/old/rv64imc/wally-config.vh
+++ /dev/null
@@ -1,122 +0,0 @@
-//////////////////////////////////////////
-// wally-config.vh
-//
-// Written: David_Harris@hmc.edu 4 January 2021
-// Modified: 
-//
-// Purpose: Specify which features are configured
-//          Macros to determine which modes are supported based on MISA
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-`include "wally-shared.vh"
-
-`define QEMU 0
-`define BUILDROOT 0
-`define BUSYBEAR 0
-
-// RV32 or RV64: XLEN = 32 or 64
-`define XLEN 64
-
-// MISA RISC-V configuration per specification
-`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
-`define ZICSR_SUPPORTED 1
-`define ZIFENCEI_SUPPORTED 1
-`define COUNTERS 32
-`define ZICOUNTERS_SUPPORTED 1
-
-// Microarchitectural Features
-`define UARCH_PIPELINED 1
-`define UARCH_SUPERSCALR 0
-`define UARCH_SINGLECYCLE 0
-`define MEM_DCACHE 1
-`define MEM_DTIM 1
-`define MEM_ICACHE 1
-`define MEM_VIRTMEM 1
-`define VECTORED_INTERRUPTS_SUPPORTED 1
-
-// TLB configuration.  Entries should be a power of 2
-`define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
-
-// Cache configuration.  Sizes should be a power of two
-// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
-`define DCACHE_NUMWAYS 4
-`define DCACHE_WAYSIZEINBYTES 2048
-`define DCACHE_BLOCKLENINBITS 256
-`define DCACHE_REPLBITS 3
-`define ICACHE_NUMWAYS 1
-`define ICACHE_WAYSIZEINBYTES 4096
-`define ICACHE_BLOCKLENINBITS 256
-
-// Integer Divider Configuration
-// DIV_BITSPERCYCLE must be 1, 2, or 4
-`define DIV_BITSPERCYCLE 4
-
-// Legal number of PMP entries are 0, 16, or 64
-`define PMP_ENTRIES 64
-
-// Address space
-`define RESET_VECTOR 64'h0000000080000000
-
-// Bus Interface width
-`define AHBW 64
-
-// Peripheral Physiccal Addresses
-// Peripheral memory space extends from BASE to BASE+RANGE
-// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   56'h00001000 
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h07FFFFFF
-`define CLINT_SUPPORTED 1'b1
-`define CLINT_BASE  56'h02000000
-`define CLINT_RANGE 56'h0000FFFF
-`define GPIO_SUPPORTED 1'b1
-`define GPIO_BASE   56'h10012000
-`define GPIO_RANGE  56'h000000FF
-`define UART_SUPPORTED 1'b1
-`define UART_BASE   56'h10000000
-`define UART_RANGE  56'h00000007
-`define PLIC_SUPPORTED 1'b1
-`define PLIC_BASE   56'h0C000000
-`define PLIC_RANGE  56'h03FFFFFF
-`define SDC_SUPPORTED 1'b1
-`define SDC_BASE   56'h00012100
-`define SDC_RANGE  56'h0000001F
-
-// Test modes
-
-// Tie GPIO outputs back to inputs
-`define GPIO_LOOPBACK_TEST 0
-
-// Hardware configuration
-`define UART_PRESCALE 1
-
-// Interrupt configuration
-`define PLIC_NUM_SRC 53
-`define PLIC_UART_ID 4
-
-`define TWO_BIT_PRELOAD "../config/rv64imc/twoBitPredictor.txt"
-`define BTB_PRELOAD "../config/rv64imc/BTBPredictor.txt"
-`define BPRED_ENABLED 1
-`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
-`define TESTSBP 0
diff --git a/wally-pipelined/config/rv32gc/wally-config.vh b/wally-pipelined/config/rv32gc/wally-config.vh
index 7f4b1064..bcc42ec5 100644
--- a/wally-pipelined/config/rv32gc/wally-config.vh
+++ b/wally-pipelined/config/rv32gc/wally-config.vh
@@ -80,12 +80,12 @@
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   34'h00001000 
-`define BOOTTIM_RANGE  34'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       34'h80000000
-`define TIM_RANGE      34'h07FFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       34'h80000000
+`define RAM_RANGE      34'h07FFFFFF
 `define EXT_MEM_SUPPORTED 1'b0
 `define EXT_MEM_BASE       34'h80000000
 `define EXT_MEM_RANGE      34'h07FFFFFF
diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh
index 1c62f513..b393119d 100644
--- a/wally-pipelined/config/rv32ic/wally-config.vh
+++ b/wally-pipelined/config/rv32ic/wally-config.vh
@@ -80,12 +80,12 @@
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   34'h00001000 
-`define BOOTTIM_RANGE  34'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       34'h80000000
-`define TIM_RANGE      34'h07FFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   34'h00001000 
+`define BOOTROM_RANGE  34'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       34'h80000000
+`define RAM_RANGE      34'h07FFFFFF
 `define EXT_MEM_SUPPORTED 1'b0
 `define EXT_MEM_BASE       34'h80000000
 `define EXT_MEM_RANGE      34'h07FFFFFF
diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh
index 8105f1a4..7a310bdf 100644
--- a/wally-pipelined/config/rv64BP/wally-config.vh
+++ b/wally-pipelined/config/rv64BP/wally-config.vh
@@ -85,12 +85,12 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   56'h00001000 
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h07FFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h07FFFFFF
 `define EXT_MEM_SUPPORTED 1'b0
 `define EXT_MEM_BASE       56'h80000000
 `define EXT_MEM_RANGE      56'h07FFFFFF
diff --git a/wally-pipelined/config/rv64gc/wally-config.vh b/wally-pipelined/config/rv64gc/wally-config.vh
index b4563132..599d6d96 100644
--- a/wally-pipelined/config/rv64gc/wally-config.vh
+++ b/wally-pipelined/config/rv64gc/wally-config.vh
@@ -86,12 +86,12 @@
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
 // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h7FFFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h7FFFFFFF
 `define EXT_MEM_SUPPORTED 1'b0
 `define EXT_MEM_BASE       56'h80000000
 `define EXT_MEM_RANGE      56'h07FFFFFF
diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh
index 31fcc0f2..d02fa871 100644
--- a/wally-pipelined/config/rv64ic/wally-config.vh
+++ b/wally-pipelined/config/rv64ic/wally-config.vh
@@ -86,12 +86,12 @@
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
 // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
-`define BOOTTIM_SUPPORTED 1'b1
-`define BOOTTIM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
-`define BOOTTIM_RANGE  56'h00000FFF
-`define TIM_SUPPORTED 1'b1
-`define TIM_BASE       56'h80000000
-`define TIM_RANGE      56'h7FFFFFFF
+`define BOOTROM_SUPPORTED 1'b1
+`define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
+`define BOOTROM_RANGE  56'h00000FFF
+`define RAM_SUPPORTED 1'b1
+`define RAM_BASE       56'h80000000
+`define RAM_RANGE      56'h7FFFFFFF
 `define EXT_MEM_SUPPORTED 1'b0
 `define EXT_MEM_BASE       56'h80000000
 `define EXT_MEM_RANGE      56'h07FFFFFF
diff --git a/wally-pipelined/regression/fpga-wave.do b/wally-pipelined/regression/fpga-wave.do
index b41f7954..a5916df3 100644
--- a/wally-pipelined/regression/fpga-wave.do
+++ b/wally-pipelined/regression/fpga-wave.do
@@ -550,31 +550,31 @@ add wave -noupdate -group SDC -group {Instruction Counter control} /testbench/du
 add wave -noupdate -group SDC -group {Instruction Counter control} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_IC_RST
 add wave -noupdate -group SDC -group {Instruction Counter control} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/w_IC_UP_DOWN
 add wave -noupdate -group SDC -group {Instruction Counter control} /testbench/dut/wallypipelinedsoc/uncore/sdc/SDC/sd_top/r_IC_OUT
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HADDR
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/A
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HWADDR
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HSELTim
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HREADYTim
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/HRESPTim
-add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootdtim/bootdtim/initTrans
+add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HADDR
+add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/A
+add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HWADDR
+add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HSELTim
+add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HREADYTim
+add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/HRESPTim
+add wave -noupdate -group boottim /testbench/dut/wallypipelinedsoc/uncore/bootram/bootram/initTrans
 add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HSELRegions
 add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HSELDDR4
-add wave -noupdate /testbench/dtim/HSELTim
+add wave -noupdate /testbench/ram/HSELTim
 add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HRDATAEXT
 add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HREADYEXT
 add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HRESPEXT
 add wave -noupdate /testbench/dut/wallypipelinedsoc/uncore/HSELEXT
-add wave -noupdate /testbench/dtim/HCLK
-add wave -noupdate /testbench/dtim/HRESETn
-add wave -noupdate /testbench/dtim/HSELTim
-add wave -noupdate /testbench/dtim/HADDR
-add wave -noupdate /testbench/dtim/HWRITE
-add wave -noupdate /testbench/dtim/HREADY
-add wave -noupdate /testbench/dtim/HTRANS
-add wave -noupdate /testbench/dtim/HWDATA
-add wave -noupdate /testbench/dtim/HREADTim
-add wave -noupdate /testbench/dtim/HRESPTim
-add wave -noupdate /testbench/dtim/HREADYTim
+add wave -noupdate /testbench/ram/HCLK
+add wave -noupdate /testbench/ram/HRESETn
+add wave -noupdate /testbench/ram/HSELTim
+add wave -noupdate /testbench/ram/HADDR
+add wave -noupdate /testbench/ram/HWRITE
+add wave -noupdate /testbench/ram/HREADY
+add wave -noupdate /testbench/ram/HTRANS
+add wave -noupdate /testbench/ram/HWDATA
+add wave -noupdate /testbench/ram/HREADTim
+add wave -noupdate /testbench/ram/HRESPTim
+add wave -noupdate /testbench/ram/HREADYTim
 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 6} {1090427 ns} 1} {{Cursor 3} {1157417 ns} 1} {{Cursor 4} {2324620 ns} 0}
 quietly wave cursor active 3
diff --git a/wally-pipelined/regression/sim-wally-batch b/wally-pipelined/regression/sim-wally-batch
index ff944450..f46f9b1f 100755
--- a/wally-pipelined/regression/sim-wally-batch
+++ b/wally-pipelined/regression/sim-wally-batch
@@ -1,3 +1,3 @@
 vsim -c <<!
-do wally-pipelined-batch.do rv64g arch64i
+do wally-pipelined-batch.do rv64gc arch64i
 !
diff --git a/wally-pipelined/regression/wally-coremark.do b/wally-pipelined/regression/wally-coremark.do
index b403016a..c606a4f3 100644
--- a/wally-pipelined/regression/wally-coremark.do
+++ b/wally-pipelined/regression/wally-coremark.do
@@ -35,7 +35,7 @@ vlog +incdir+../config/coremark_bare +incdir+../config/shared ../testbench/testb
 vopt +acc work.testbench -o workopt 
 vsim workopt
 
-mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/dtim/dtim/RAM
+mem load -startaddress 268435456 -endaddress 268566527 -filltype value -fillradix hex -filldata 0 /testbench/dut/uncore/ram/ram/RAM
 
 view wave
 
@@ -79,7 +79,7 @@ add wave /testbench/InstrWName
 #add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
 #add wave /testbench/dut/hart/ieu/dp/PCSrcE
 add wave -divider Regfile_signals
-#add wave /testbench/dut/uncore/dtim/memwrite
+#add wave /testbench/dut/uncore/ram/memwrite
 #add wave -hex /testbench/dut/uncore/HADDR
 #add wave -hex /testbench/dut/uncore/HWDATA
 #add wave -divider
@@ -92,7 +92,7 @@ add wave -hex -r /testbench/dut/hart/ieu/dp/regf/*
 add wave -divider Regfile_itself
 add wave -hex -r /testbench/dut/hart/ieu/dp/regf/rf
 add wave -divider RAM
-#add wave -hex -r /testbench/dut/uncore/dtim/RAM
+#add wave -hex -r /testbench/dut/uncore/ram/RAM
 add wave -divider Misc
 add wave -divider
 #add wave -hex -r /testbench/*
diff --git a/wally-pipelined/regression/wally-pipelined-fpga.do b/wally-pipelined/regression/wally-pipelined-fpga.do
index 2455a6e2..e39da4da 100644
--- a/wally-pipelined/regression/wally-pipelined-fpga.do
+++ b/wally-pipelined/regression/wally-pipelined-fpga.do
@@ -42,13 +42,13 @@ vsim workopt -fsmdebug
 
 do fpga-wave.do
 add log -r /*
-#add wave /testbench/dtim/RAM[268435456]
-#add wave /testbench/dtim/RAM[268435457]
-#add wave /testbench/dtim/RAM[268435458]
-#add wave /testbench/dtim/RAM[268435459]
-#add wave /testbench/dtim/RAM[268435460]
-#add wave /testbench/dtim/RAM[268435461]
-#xadd wave /testbench/dtim/RAM[268435462]
+#add wave /testbench/ram/RAM[268435456]
+#add wave /testbench/ram/RAM[268435457]
+#add wave /testbench/ram/RAM[268435458]
+#add wave /testbench/ram/RAM[268435459]
+#add wave /testbench/ram/RAM[268435460]
+#add wave /testbench/ram/RAM[268435461]
+#xadd wave /testbench/ram/RAM[268435462]
 
 -- Run the Simulation 
 #run 1000
diff --git a/wally-pipelined/regression/wave-all.do b/wally-pipelined/regression/wave-all.do
index 98e04c47..e7bf6067 100644
--- a/wally-pipelined/regression/wave-all.do
+++ b/wally-pipelined/regression/wave-all.do
@@ -41,7 +41,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE
 add wave -noupdate /testbench/dut/hart/ieu/dp/PCSrcE
 add wave -noupdate -divider <NULL>
 add wave -noupdate /testbench/InstrMName
-add wave -noupdate /testbench/dut/uncore/dtim/memwrite
+add wave -noupdate /testbench/dut/uncore/ram/memwrite
 add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HADDR
 add wave -noupdate -radix hexadecimal /testbench/dut/uncore/HWDATA
 add wave -noupdate -divider <NULL>
@@ -1388,19 +1388,19 @@ add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/ByteM
 add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/HalfwordM
 add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/WriteDataSubwordDuplicated
 add wave -noupdate -radix hexadecimal /testbench/dut/uncore/sww/ByteMaskM
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HCLK
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HRESETn
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/MemRWtim
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HADDR
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HWDATA
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HSELTim
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HREADTim
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HRESPTim
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HREADYTim
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/entry
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/memread
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/memwrite
-add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/busycount
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HCLK
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HRESETn
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/MemRWtim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HADDR
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HWDATA
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HSELTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HREADTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HRESPTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/HREADYTim
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/entry
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/memread
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/memwrite
+add wave -noupdate -radix hexadecimal /testbench/dut/uncore/ram/busycount
 add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HCLK
 add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/HRESETn
 add wave -noupdate -radix hexadecimal /testbench/dut/uncore/clint/MemRWclint
diff --git a/wally-pipelined/regression/wave-dos/ahb-muldiv.do b/wally-pipelined/regression/wave-dos/ahb-muldiv.do
index dedf0ba5..d9e6449c 100644
--- a/wally-pipelined/regression/wave-dos/ahb-muldiv.do
+++ b/wally-pipelined/regression/wave-dos/ahb-muldiv.do
@@ -52,7 +52,7 @@ add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCM
 add wave -hex /testbench/dut/hart/ifu/InstrM
 add wave /testbench/InstrMName
-add wave /testbench/dut/uncore/dtim/memwrite
+add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
 add wave -hex /testbench/dut/uncore/HWDATA
 add wave -divider
@@ -70,7 +70,7 @@ add wave -hex /testbench/dut/hart/ebu/HWDATA
 add wave -hex /testbench/dut/hart/ebu/CaptureDataM
 add wave -divider
 
-add wave -hex /testbench/dut/uncore/dtim/*
+add wave -hex /testbench/dut/uncore/ram/*
 add wave -divider
 
 add wave -hex /testbench/dut/hart/ifu/PCW
@@ -82,7 +82,7 @@ add wave -hex /testbench/dut/hart/ieu/dp/ResultW
 add wave -hex /testbench/dut/hart/ieu/dp/RdW
 add wave -divider
 
-add wave -hex /testbench/dut/uncore/dtim/*
+add wave -hex /testbench/dut/uncore/ram/*
 add wave -divider
 
 # appearance
diff --git a/wally-pipelined/regression/wave-dos/ahb-waves.do b/wally-pipelined/regression/wave-dos/ahb-waves.do
index add1ab22..b5c244e3 100644
--- a/wally-pipelined/regression/wave-dos/ahb-waves.do
+++ b/wally-pipelined/regression/wave-dos/ahb-waves.do
@@ -40,7 +40,7 @@ add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCM
 add wave -hex /testbench/dut/hart/ifu/InstrM
 add wave /testbench/InstrMName
-add wave /testbench/dut/uncore/dtim/memwrite
+add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
 add wave -hex /testbench/dut/uncore/HWDATA
 add wave -divider
@@ -58,7 +58,7 @@ add wave -hex /testbench/dut/hart/ebu/HWDATA
 add wave -hex /testbench/dut/hart/ebu/CaptureDataM
 add wave -divider
 
-add wave -hex /testbench/dut/uncore/dtim/*
+add wave -hex /testbench/dut/uncore/ram/*
 add wave -divider
 
 add wave -hex /testbench/dut/hart/ifu/PCW
@@ -70,7 +70,7 @@ add wave -hex /testbench/dut/hart/ieu/dp/ResultW
 add wave -hex /testbench/dut/hart/ieu/dp/RdW
 add wave -divider
 
-add wave -hex /testbench/dut/uncore/dtim/*
+add wave -hex /testbench/dut/uncore/ram/*
 add wave -divider
 
 add wave -hex -r /testbench/*
diff --git a/wally-pipelined/regression/wave-dos/cache-waves.do b/wally-pipelined/regression/wave-dos/cache-waves.do
index f8d98d3d..5a81f4fc 100644
--- a/wally-pipelined/regression/wave-dos/cache-waves.do
+++ b/wally-pipelined/regression/wave-dos/cache-waves.do
@@ -36,7 +36,7 @@ add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCM
 add wave -hex /testbench/dut/hart/ifu/InstrM
 add wave /testbench/InstrMName
-add wave /testbench/dut/uncore/dtim/memwrite
+add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
 add wave -hex /testbench/dut/uncore/HWDATA
 add wave -divider
diff --git a/wally-pipelined/regression/wave-dos/default-waves.do b/wally-pipelined/regression/wave-dos/default-waves.do
index 7c164958..f03b2ccb 100644
--- a/wally-pipelined/regression/wave-dos/default-waves.do
+++ b/wally-pipelined/regression/wave-dos/default-waves.do
@@ -37,7 +37,7 @@ add wave -divider
 add wave -hex /testbench/dut/hart/ifu/PCM
 add wave -hex /testbench/dut/hart/ifu/InstrM
 add wave /testbench/InstrMName
-add wave /testbench/dut/uncore/dtim/memwrite
+add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/uncore/HADDR
 add wave -hex /testbench/dut/uncore/HWDATA
 add wave -divider
diff --git a/wally-pipelined/regression/wave-dos/peripheral-waves.do b/wally-pipelined/regression/wave-dos/peripheral-waves.do
index f5382c3b..9cef7a69 100644
--- a/wally-pipelined/regression/wave-dos/peripheral-waves.do
+++ b/wally-pipelined/regression/wave-dos/peripheral-waves.do
@@ -45,7 +45,7 @@ add wave -hex /testbench/dut/hart/ifu/PCM
 add wave -hex /testbench/dut/hart/ifu/InstrM
 add wave -hex /testbench/dut/hart/ieu/c/InstrValidM
 add wave /testbench/InstrMName
-add wave /testbench/dut/uncore/dtim/memwrite
+add wave /testbench/dut/uncore/ram/memwrite
 add wave -hex /testbench/dut/hart/WriteDataM
 add wave -hex /testbench/dut/hart/lsu/dcache/MemPAdrM
 add wave -hex /testbench/dut/hart/lsu/dcache/WriteDataM
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index b5455352..09322609 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -160,7 +160,7 @@ module ifu (
   // assign InstrReadF = 1; // *** & ICacheMissF; add later
 
   // conditional
-  // 1. dtim // controlled by `MEM_IROM
+  // 1. ram // controlled by `MEM_IROM
   // 2. cache // `MEM_ICACHE
   // 3. wire pass-through
   icache icache(.clk, .reset, .StallF, .ExceptionM, .PendingInterruptM, .InstrInF, .InstrAckF,
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 01fcb733..791e4d4a 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -240,7 +240,7 @@ module lsu
   assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0];
 
   // conditional
-  // 1. dtim // controlled by `MEM_DTIM
+  // 1. ram // controlled by `MEM_DTIM
   // 2. cache `MEM_DCACHE
   // 3. wire pass-through
   dcache dcache(.clk(clk),
diff --git a/wally-pipelined/src/mmu/adrdecs.sv b/wally-pipelined/src/mmu/adrdecs.sv
index fe67977c..35d96b6f 100644
--- a/wally-pipelined/src/mmu/adrdecs.sv
+++ b/wally-pipelined/src/mmu/adrdecs.sv
@@ -36,8 +36,8 @@ module adrdecs (
  // Determine which region of physical memory (if any) is being accessed
  // *** eventually uncomment Access signals
   adrdec ddr4dec(PhysicalAddress, `EXT_MEM_BASE, `EXT_MEM_RANGE, `EXT_MEM_SUPPORTED, AccessRWX, Size, 4'b1111, SelRegions[7]);  
-  adrdec boottimdec(PhysicalAddress, `BOOTTIM_BASE, `BOOTTIM_RANGE, `BOOTTIM_SUPPORTED, /*1'b1*/AccessRX, Size, 4'b1111, SelRegions[6]);
-  adrdec timdec(PhysicalAddress, `TIM_BASE, `TIM_RANGE, `TIM_SUPPORTED, /*1'b1*/AccessRWX, Size, 4'b1111, SelRegions[5]);
+  adrdec boottimdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, /*1'b1*/AccessRX, Size, 4'b1111, SelRegions[6]);
+  adrdec timdec(PhysicalAddress, `RAM_BASE, `RAM_RANGE, `RAM_SUPPORTED, /*1'b1*/AccessRWX, Size, 4'b1111, SelRegions[5]);
 
   adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, 4'b1111, SelRegions[4]);
   adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]);
diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/ram.sv
similarity index 81%
rename from wally-pipelined/src/uncore/dtim.sv
rename to wally-pipelined/src/uncore/ram.sv
index 31d8fec5..a537daf7 100644
--- a/wally-pipelined/src/uncore/dtim.sv
+++ b/wally-pipelined/src/uncore/ram.sv
@@ -1,10 +1,10 @@
 ///////////////////////////////////////////
-// dtim.sv
+// ram.sv
 //
 // Written: David_Harris@hmc.edu 9 January 2021
 // Modified: 
 //
-// Purpose: Data tightly integrated memory
+// Purpose: On-chip RAM, external to hart
 // 
 // A component of the Wally configurable RISC-V project.
 // 
@@ -25,16 +25,16 @@
 
 `include "wally-config.vh"
 
-module dtim #(parameter BASE=0, RANGE = 65535) (
+module ram #(parameter BASE=0, RANGE = 65535) (
   input  logic             HCLK, HRESETn, 
-  input  logic             HSELTim,
+  input  logic             HSELRam,
   input  logic [31:0]      HADDR,
   input  logic             HWRITE,
   input  logic             HREADY,
   input  logic [1:0]       HTRANS,
   input  logic [`XLEN-1:0] HWDATA,
-  output logic [`XLEN-1:0] HREADTim,
-  output logic             HRESPTim, HREADYTim
+  output logic [`XLEN-1:0] HREADRam,
+  output logic             HRESPRam, HREADYRam
 );
 
   localparam MemStartAddr = BASE>>(1+`XLEN/32);
@@ -42,9 +42,9 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
   
   logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
   logic [31:0] HWADDR, A;
-  logic [`XLEN-1:0] HREADTim0;
+  logic [`XLEN-1:0] HREADRam0;
 
-  logic        prevHREADYTim, risingHREADYTim;
+  logic        prevHREADYRam, risingHREADYRam;
   logic        initTrans;
   logic        memwrite;
   logic [3:0]  busycount;
@@ -100,37 +100,37 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
     end // if (FPGA)
   endgenerate
 
-  assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);
+  assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
 
   // *** this seems like a weird way to use reset
-  flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELTim &  HWRITE, memwrite);
+  flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELRam &  HWRITE, memwrite);
   flopenr #(32)   haddrreg(HCLK, 1'b0, initTrans | ~HRESETn, HADDR, A);
 
   // busy FSM to extend READY signal
   always_ff @(posedge HCLK, negedge HRESETn) 
     if (~HRESETn) begin
       busycount <= 0;
-      HREADYTim <= #1 0;
+      HREADYRam <= #1 0;
     end else begin
       if (initTrans) begin
         busycount <= 0;
-        HREADYTim <= #1 0;
-      end else if (~HREADYTim) begin
-        if (busycount == 0) begin // TIM latency, for testing purposes.  *** test with different values such as 2
-          HREADYTim <= #1 1;
+        HREADYRam <= #1 0;
+      end else if (~HREADYRam) begin
+        if (busycount == 0) begin // Ram latency, for testing purposes.  *** test with different values such as 2
+          HREADYRam <= #1 1;
         end else begin
           busycount <= busycount + 1;
         end
       end
     end
-  assign HRESPTim = 0; // OK
+  assign HRESPRam = 0; // OK
   
   // Rising HREADY edge detector
-  //   Indicates when dtim is finishing up
+  //   Indicates when ram is finishing up
   //   Needed because HREADY may go high for other reasons,
   //   and we only want to write data when finishing up.
-  flopr #(1) prevhreadytimreg(HCLK,~HRESETn,HREADYTim,prevHREADYTim);
-  assign risingHREADYTim = HREADYTim & ~prevHREADYTim;
+  flopr #(1) prevhreadyRamreg(HCLK,~HRESETn,HREADYRam,prevHREADYRam);
+  assign risingHREADYRam = HREADYRam & ~prevHREADYRam;
 
   // Model memory read and write
 /* -----\/----- EXCLUDED -----\/-----
@@ -148,22 +148,22 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
     if (`XLEN == 64)  begin
       always_ff @(posedge HCLK) begin
         HWADDR <= #1 A;
-        HREADTim0 <= #1 RAM[A[31:3]];
-	if (memwrite & risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA;
+        HREADRam0 <= #1 RAM[A[31:3]];
+	if (memwrite & risingHREADYRam) RAM[HWADDR[31:3]] <= #1 HWDATA;
       end
     end else begin 
       always_ff @(posedge HCLK) begin
         HWADDR <= #1 A;  
-        HREADTim0 <= #1 RAM[A[31:2]];
-        if (memwrite & risingHREADYTim) RAM[HWADDR[31:2]] <= #1 HWDATA;
+        HREADRam0 <= #1 RAM[A[31:2]];
+        if (memwrite & risingHREADYRam) RAM[HWADDR[31:2]] <= #1 HWDATA;
       end
     end
   endgenerate
   /* verilator lint_on WIDTH */
 
-  //assign HREADTim = HREADYTim ? HREADTim0 : `XLEN'bz;
+  //assign HREADRam = HREADYRam ? HREADRam0 : `XLEN'bz;
   // *** Ross Thompson: removed tristate as fpga synthesis removes.
-  assign HREADTim = HREADTim0;
+  assign HREADRam = HREADRam0;
   
 endmodule
 
diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index 97057b23..eee9e285 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -63,15 +63,15 @@ module uncore (
 );
   
   logic [`XLEN-1:0] HWDATA;
-  logic [`XLEN-1:0] HREADTim, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART, HREADSDC;
+  logic [`XLEN-1:0] HREADRam, HREADCLINT, HREADPLIC, HREADGPIO, HREADUART, HREADSDC;
 
   logic [8:0]      HSELRegions;
-  logic            HSELTim, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC;
-  logic            HSELEXTD, HSELTimD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD;
-  logic            HRESPTim, HRESPCLINT, HRESPPLIC, HRESPGPIO, HRESPUART, HRESPSDC;
-  logic            HREADYTim, HREADYCLINT, HREADYPLIC, HREADYGPIO, HREADYUART, HRESPSDCD;
-  logic [`XLEN-1:0] HREADBootTim; 
-  logic            HSELBootTim, HSELBootTimD, HRESPBootTim, HREADYBootTim, HREADYSDC;
+  logic            HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC;
+  logic            HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD;
+  logic            HRESPRam, HRESPCLINT, HRESPPLIC, HRESPGPIO, HRESPUART, HRESPSDC;
+  logic            HREADYRam, HREADYCLINT, HREADYPLIC, HREADYGPIO, HREADYUART, HRESPSDCD;
+  logic [`XLEN-1:0] HREADBootRom; 
+  logic            HSELBootRom, HSELBootRomD, HRESPBootRom, HREADYBootRom, HREADYSDC;
   logic            HSELNoneD;
   logic            UARTIntr,GPIOIntr;
   logic 	   SDCIntM;
@@ -82,7 +82,7 @@ module uncore (
   adrdecs adrdecs({{(`PA_BITS-32){1'b0}}, HADDR}, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions);
 
   // unswizzle HSEL signals
-  assign {HSELEXT, HSELBootTim, HSELTim, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
+  assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0];
 
   // subword accesses: converts HWDATAIN to HWDATA
   subwordwrite sww(
@@ -91,25 +91,25 @@ module uncore (
     .HWDATAIN, .HWDATA);
 
   generate
-    // tightly integrated memory
-    if (`TIM_SUPPORTED) begin : dtim
-      dtim #(
-        .BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (
+    // on-chip RAM outside hart
+    if (`RAM_SUPPORTED) begin : ram
+      ram #(
+        .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
         .HCLK, .HRESETn, 
-        .HSELTim, .HADDR,
+        .HSELRam, .HADDR,
         .HWRITE, .HREADY,
-        .HTRANS, .HWDATA, .HREADTim,
-        .HRESPTim, .HREADYTim);
+        .HTRANS, .HWDATA, .HREADRam,
+        .HRESPRam, .HREADYRam);
     end
 
-    if (`BOOTTIM_SUPPORTED) begin : bootdtim
-      dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE))
-      bootdtim(
+    if (`BOOTROM_SUPPORTED) begin : bootrom
+      ram #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
+      bootrom(
         .HCLK, .HRESETn, 
-        .HSELTim(HSELBootTim), .HADDR,
+        .HSELRam(HSELBootRom), .HADDR,
         .HWRITE, .HREADY, .HTRANS,
         .HWDATA,
-        .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim));
+        .HREADRam(HREADBootRom), .HRESPRam(HRESPBootRom), .HREADYRam(HREADYBootRom));
     end
 
     // memory-mapped I/O peripherals
@@ -184,35 +184,35 @@ module uncore (
 
   // mux could also include external memory  
   // AHB Read Multiplexer
-  assign HRDATA = ({`XLEN{HSELTimD}} & HREADTim) |
+  assign HRDATA = ({`XLEN{HSELRamD}} & HREADRam) |
 		  ({`XLEN{HSELEXTD}} & HRDATAEXT) |   
                   ({`XLEN{HSELCLINTD}} & HREADCLINT) |
                   ({`XLEN{HSELPLICD}} & HREADPLIC) | 
                   ({`XLEN{HSELGPIOD}} & HREADGPIO) |
-                  ({`XLEN{HSELBootTimD}} & HREADBootTim) |
+                  ({`XLEN{HSELBootRomD}} & HREADBootRom) |
                   ({`XLEN{HSELUARTD}} & HREADUART) |
                   ({`XLEN{HSELSDCD}} & HREADSDC);
 
-  assign HRESP = HSELTimD & HRESPTim |
+  assign HRESP = HSELRamD & HRESPRam |
 		 HSELEXTD & HRESPEXT |
                  HSELCLINTD & HRESPCLINT |
                  HSELPLICD & HRESPPLIC |
                  HSELGPIOD & HRESPGPIO | 
-                 HSELBootTimD & HRESPBootTim |
+                 HSELBootRomD & HRESPBootRom |
                  HSELUARTD & HRESPUART |
                  HSELSDC & HRESPSDC;		 
 
-  assign HREADY = HSELTimD & HREADYTim |
+  assign HREADY = HSELRamD & HREADYRam |
 		  HSELEXTD & HREADYEXT |		  
                   HSELCLINTD & HREADYCLINT |
                   HSELPLICD & HREADYPLIC |
                   HSELGPIOD & HREADYGPIO | 
-                  HSELBootTimD & HREADYBootTim |
+                  HSELBootRomD & HREADYBootRom |
                   HSELUARTD & HREADYUART |
                   HSELSDCD & HREADYSDC |		  
                   HSELNoneD; // don't lock up the bus if no region is being accessed
 
   // Address Decoder Delay (figure 4-2 in spec)
-  flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootTimD, HSELTimD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
+  flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD});
 endmodule
 
diff --git a/wally-pipelined/testbench/testbench-coremark.sv b/wally-pipelined/testbench/testbench-coremark.sv
index 8f6683d3..22062f0c 100644
--- a/wally-pipelined/testbench/testbench-coremark.sv
+++ b/wally-pipelined/testbench/testbench-coremark.sv
@@ -87,9 +87,9 @@ module testbench();
       totalerrors = 0;
       // read test vectors into memory
       memfilename = tests[0];
-      $readmemh(memfilename, dut.uncore.dtim.RAM);
+      $readmemh(memfilename, dut.uncore.ram.RAM);
       for(j=18710; j < 65535; j = j+1)
-        dut.uncore.dtim.RAM[j] = 64'b0;
+        dut.uncore.ram.RAM[j] = 64'b0;
       reset = 1; # 22; reset = 0;
     end
   // generate clock to sequence tests
diff --git a/wally-pipelined/testbench/testbench-coremark_bare.sv b/wally-pipelined/testbench/testbench-coremark_bare.sv
index 33378cc3..32cd0f90 100644
--- a/wally-pipelined/testbench/testbench-coremark_bare.sv
+++ b/wally-pipelined/testbench/testbench-coremark_bare.sv
@@ -103,12 +103,12 @@ module testbench();
       totalerrors = 0;
       // read test vectors into memory
       memfilename = tests[0];
-      $readmemh(memfilename, dut.uncore.dtim.dtim.RAM);
+      $readmemh(memfilename, dut.uncore.ram.ram.RAM);
       //for(j=268437955; j < 268566528; j = j+1)
-        //dut.uncore.dtim.RAM[j] = 64'b0;
+        //dut.uncore.ram.RAM[j] = 64'b0;
 //      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.addr";
 //      ProgramAddrMapFile = "../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.objdump.lab";
-        //dut.uncore.dtim.RAM[268437713]=64'b1;
+        //dut.uncore.ram.RAM[268437713]=64'b1;
     reset_ext = 1; # 22; reset_ext = 0;
     end
   // generate clock to sequence tests
diff --git a/wally-pipelined/testbench/testbench-fpga.sv b/wally-pipelined/testbench/testbench-fpga.sv
index b10eb8fd..17f2a1d3 100644
--- a/wally-pipelined/testbench/testbench-fpga.sv
+++ b/wally-pipelined/testbench/testbench-fpga.sv
@@ -595,8 +595,8 @@ string tests32f[] = '{
   assign GPIOPinsIn = 0;
   assign UARTSin = 1;
  
-  dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) 
-  dtim (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELTim(HSELEXT), 
+  ram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) 
+  ram (.HCLK, .HRESETn, .HADDR, .HWRITE, .HTRANS, .HWDATA, .HSELTim(HSELEXT), 
         .HREADTim(HRDATAEXT), .HREADYTim(HREADYEXT), .HRESPTim(HRESPEXT));
  
 
@@ -613,8 +613,8 @@ string tests32f[] = '{
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // initialize tests
-  localparam integer 	   MemStartAddr = `TIM_BASE>>(1+`XLEN/32);
-  localparam integer 	   MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32);
+  localparam integer 	   MemStartAddr = `RAM_BASE>>(1+`XLEN/32);
+  localparam integer 	   MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32);
 
   initial
     begin
@@ -633,7 +633,7 @@ string tests32f[] = '{
 /* -----\/----- EXCLUDED -----\/-----
       if (`TESTSBP) begin
 	for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
-	  dtim.RAM[i] = meminit;
+	  ram.RAM[i] = meminit;
 	end
       end
  -----/\----- EXCLUDED -----/\----- */
@@ -642,8 +642,8 @@ string tests32f[] = '{
       //romfilename = {"../../testsBP/fpga-test-sdc/bin/fpga-test-sdc.hex"};
       romfilename = {"../../tests/testsBP/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
       sdcfilename = {"../src/sdc/tb/ramdisk2.hex"};      
-      $readmemh(memfilename, dtim.RAM);
-      $readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootdtim.bootdtim.RAM);
+      $readmemh(memfilename, ram.RAM);
+      $readmemh(romfilename, dut.wallypipelinedsoc.uncore.bootram.bootram.RAM);
       $readmemh(sdcfilename, sdcard.FLASHmem);
       ProgramAddrMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.addr"};
       ProgramLabelMapFile = {"../../imperas-riscv-tests/work/rv64BP/fpga-test-sdc.objdump.lab"};
@@ -699,18 +699,18 @@ string tests32f[] = '{
         // Check errors
         errors = (i == SIGNATURESIZE+1); // error if file is empty
         i = 0;
-        testadr = (`TIM_BASE+tests[test+1].atohex())/(`XLEN/8);
+        testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8);
         /* verilator lint_off INFINITELOOP */
         while (signature[i] !== 'bx) begin
           //$display("signature[%h] = %h", i, signature[i]);
-          if (signature[i] !== dtim.RAM[testadr+i] &&
+          if (signature[i] !== ram.RAM[testadr+i] &&
 	      (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
             if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
               // report errors unless they are garbage at the end of the sim
               // kind of hacky test for garbage right now
               errors = errors+1;
               $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", 
-                    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dtim.RAM[testadr+i], signature[i]);
+                    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], ram.RAM[testadr+i], signature[i]);
               $stop;//***debug
             end
           end
@@ -732,7 +732,7 @@ string tests32f[] = '{
         end
         else begin
           memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-          $readmemh(memfilename, dtim.RAM);
+          $readmemh(memfilename, ram.RAM);
           $display("Read memfile %s", memfilename);
 	  ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
 	  ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
@@ -795,7 +795,7 @@ module riscvassertions();
     assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $warning("Multiple Instruction Cache ways not yet implemented");
     assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
     assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
-    assert (`TIM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");
+    assert (`RAM_RANGE >= 56'h07FFFFFF) else $error("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
   end
 endmodule
 
@@ -828,7 +828,7 @@ module DCacheFlushFSM
   logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
   genvar adr;
 
-  logic [`XLEN-1:0] ShadowRAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)];
+  logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
   
   generate
     for(index = 0; index < numlines; index++) begin
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index 82e69720..b09b19aa 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -311,22 +311,22 @@ module testbench();
     force dut.hart.priv.SwIntM = 0;
     force dut.hart.priv.TimerIntM = 0;
     force dut.hart.priv.ExtIntM = 0;    
-    $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootdtim.bootdtim.RAM, 'h1000 >> 3);
+    $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootrom.bootrom.RAM, 'h1000 >> 3);
     $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
     $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
     ProgramAddrMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.addr"};
     ProgramLabelMapFile = {`LINUX_TEST_VECTORS,"vmlinux.objdump.lab"};
     if (CHECKPOINT==0) begin // normal
-      $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.dtim.dtim.RAM);
+      $readmemh({`LINUX_TEST_VECTORS,"ram.txt"}, dut.uncore.ram.ram.RAM);
       traceFileM = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
       traceFileE = $fopen({`LINUX_TEST_VECTORS,"all.txt"}, "r");
       InstrCountW = '0;
     end else begin // checkpoint
       $sformat(checkpointDir,"checkpoint%0d/",CHECKPOINT);
       checkpointDir = {`LINUX_TEST_VECTORS,checkpointDir};
-      //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.dtim.dtim.RAM);
+      //$readmemh({checkpointDir,"ram.txt"}, dut.uncore.ram.ram.RAM);
       ramFile = $fopen({checkpointDir,"ram.bin"}, "rb");
-      readResult = $fread(dut.uncore.dtim.dtim.RAM,ramFile);
+      readResult = $fread(dut.uncore.ram.ram.RAM,ramFile);
       $fclose(ramFile);
       traceFileE = $fopen({checkpointDir,"all.txt"}, "r");
       traceFileM = $fopen({checkpointDir,"all.txt"}, "r");
@@ -449,7 +449,7 @@ module testbench();
           force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
         else \
           release dut.hart.ieu.dp.ReadDataM; \
-        if(textM.substr(0,5) == "rdtime") begin \
+        if(textM.substr(0,5) == "rrame") begin \
           //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
           force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
         end \
@@ -547,7 +547,7 @@ module testbench();
       #1;
       // override on special conditions
       if(~dut.hart.StallW) begin
-        if(textW.substr(0,5) == "rdtime") begin
+        if(textW.substr(0,5) == "rrame") begin
           //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
           release dut.uncore.clint.clint.MTIME;
         end 
@@ -651,7 +651,7 @@ module testbench();
   // Address Translator
   // ------------------
    /**
-   * Walk the page table stored in dtim according to sv39 logic and translate a
+   * Walk the page table stored in ram according to sv39 logic and translate a
    * virtual address to a physical address.
    *
    * See section 4.3.2 of the RISC-V Privileged specification for a full
@@ -681,9 +681,9 @@ module testbench();
         BaseAdr = SATP[43:0] << 12;
         for (i = 2; i >= 0; i--) begin
           PAdr = BaseAdr + (VPN[i] << 3);
-          // dtim.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
+          // ram.RAM is 64-bit addressed. PAdr specifies a byte. We right shift
           // by 3 (the PTE size) to get the requested 64-bit PTE.
-          PTE = dut.uncore.dtim.dtim.RAM[PAdr >> 3];
+          PTE = dut.uncore.ram.ram.RAM[PAdr >> 3];
           PTE_R = PTE[1];
           PTE_X = PTE[3];
           if (PTE_R || PTE_X) begin
diff --git a/wally-pipelined/testbench/testbench-privileged.sv b/wally-pipelined/testbench/testbench-privileged.sv
index f3f68e0c..ba87a490 100644
--- a/wally-pipelined/testbench/testbench-privileged.sv
+++ b/wally-pipelined/testbench/testbench-privileged.sv
@@ -119,7 +119,7 @@ module testbench();
       end
       // read test vectors into memory
       memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-      $readmemh(memfilename, dut.uncore.dtim.RAM);
+      $readmemh(memfilename, dut.uncore.ram.RAM);
       ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
       $display("Read memfile %s", memfilename);
@@ -162,19 +162,19 @@ module testbench();
         i = 0;
         errors = 0;
         if (`XLEN == 32)
-          testadr = (`TIM_BASE+tests[test+1].atohex())/4;
+          testadr = (`RAM_BASE+tests[test+1].atohex())/4;
         else
-          testadr = (`TIM_BASE+tests[test+1].atohex())/8;
+          testadr = (`RAM_BASE+tests[test+1].atohex())/8;
         /* verilator lint_off INFINITELOOP */
         while (signature[i] !== 'bx) begin
           //$display("signature[%h] = %h", i, signature[i]);
-          if (signature[i] !== dut.uncore.dtim.RAM[testadr+i]) begin
+          if (signature[i] !== dut.uncore.ram.RAM[testadr+i]) begin
             if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
               // report errors unless they are garbage at the end of the sim
               // kind of hacky test for garbage right now
               errors = errors+1;
               $display("  Error on test %s result %d: adr = %h sim = %h, signature = %h", 
-                    tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
+                    tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.ram.RAM[testadr+i], signature[i]);
             end
           end
           i = i + 1;
@@ -193,7 +193,7 @@ module testbench();
         end
         else begin
           memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
-          $readmemh(memfilename, dut.uncore.dtim.RAM);
+          $readmemh(memfilename, dut.uncore.ram.RAM);
           $display("Read memfile %s", memfilename);
     ProgramAddrMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.addr"};
     ProgramLabelMapFile = {"../../imperas-riscv-tests/work/", tests[test], ".elf.objdump.lab"};
diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv
index 703b8aae..7301f454 100644
--- a/wally-pipelined/testbench/testbench.sv
+++ b/wally-pipelined/testbench/testbench.sv
@@ -146,7 +146,7 @@ logic [3:0] dummy;
   assign HRESPEXT = 0;
   assign HRDATAEXT = 0;
 
-  wallypipelinedsoc dut(.clk, .reset_ext, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+  wallypipelinedsoc dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
                         .HCLK, .HRESETn, .HADDR, .HWDATA, .HWRITE, .HSIZE, .HBURST, .HPROT,
                         .HTRANS, .HMASTLOCK, .HREADY, .GPIOPinsIn, .GPIOPinsOut, .GPIOPinsEn,
                         .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
@@ -159,8 +159,8 @@ logic [3:0] dummy;
                 InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
 
   // initialize tests
-  localparam integer 	   MemStartAddr = `TIM_BASE>>(1+`XLEN/32);
-  localparam integer 	   MemEndAddr = (`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32);
+  localparam integer 	   MemStartAddr = `RAM_BASE>>(1+`XLEN/32);
+  localparam integer 	   MemEndAddr = (`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32);
 
   initial
     begin
@@ -178,7 +178,7 @@ logic [3:0] dummy;
       // *** broken because DTIM also drives RAM
       if (`TESTSBP) begin
 	for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
-	  dut.uncore.dtim.dtim.RAM[i] = meminit;
+	  dut.uncore.ram.ram.RAM[i] = meminit;
 	end
       end
       // read test vectors into memory
@@ -187,7 +187,7 @@ logic [3:0] dummy;
         pathname = tvpaths[0];
       else pathname = tvpaths[1]; */
       memfilename = {pathname, tests[test], ".elf.memfile"};
-      $readmemh(memfilename, dut.uncore.dtim.dtim.RAM);
+      $readmemh(memfilename, dut.uncore.ram.ram.RAM);
       ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
       ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
       $display("Read memfile %s", memfilename);
@@ -234,18 +234,18 @@ logic [3:0] dummy;
         // Check errors
         errors = (i == SIGNATURESIZE+1); // error if file is empty
         i = 0;
-        testadr = (`TIM_BASE+tests[test+1].atohex())/(`XLEN/8);
+        testadr = (`RAM_BASE+tests[test+1].atohex())/(`XLEN/8);
         /* verilator lint_off INFINITELOOP */
         while (signature[i] !== 'bx) begin
           //$display("signature[%h] = %h", i, signature[i]);
-          if (signature[i] !== dut.uncore.dtim.dtim.RAM[testadr+i] &&
+          if (signature[i] !== dut.uncore.ram.ram.RAM[testadr+i] &&
 	      (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
             if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
               // report errors unless they are garbage at the end of the sim
               // kind of hacky test for garbage right now
               errors = errors+1;
               $display("  Error on test %s result %d: adr = %h sim (D$) %h sim (TIM) = %h, signature = %h", 
-                    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.dtim.dtim.RAM[testadr+i], signature[i]);
+                    tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], dut.uncore.ram.ram.RAM[testadr+i], signature[i]);
               $stop;//***debug
             end
           end
@@ -268,7 +268,7 @@ logic [3:0] dummy;
         else begin
             //pathname = tvpaths[tests[0]];
             memfilename = {pathname, tests[test], ".elf.memfile"};
-            $readmemh(memfilename, dut.uncore.dtim.dtim.RAM);
+            $readmemh(memfilename, dut.uncore.ram.ram.RAM);
             ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
             ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
             $display("Read memfile %s", memfilename);
@@ -332,7 +332,7 @@ module riscvassertions;
     assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
     assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2");
     assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2");
-    assert (`TIM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if TIM_RANGE is less than 56'h07FFFFFF");
+    assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF");
   end
 endmodule
 
@@ -365,7 +365,7 @@ module DCacheFlushFSM
   logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
   genvar adr;
 
-  logic [`XLEN-1:0] ShadowRAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)];
+  logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
   
   generate
     for(index = 0; index < numlines; index++) begin

From 21b13fc237d36674a4ed8e6afacc70971c58e333 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 15 Dec 2021 10:24:29 -0600
Subject: [PATCH 39/95] Reverted 23Mhz to 10Mhz. The flash card can't work at
 that speed. added icache debugging signals.

---
 fpga/constraints/debug2.xdc | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index 917c2b6d..f026114b 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -447,3 +447,23 @@ set_property port_width 24 [get_debug_ports u_ila_0/probe99]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
 connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache/controller/CurrState[23]}]]
 
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe100]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe100]
+connect_debug_port u_ila_0/probe100 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/InstrInF[0]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[1]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[2]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[3]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[4]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[5]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[6]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[7]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[8]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[9]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[10]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[11]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[12]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[13]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[14]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[15]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[16]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[17]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[18]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[19]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[20]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[21]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[22]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[23]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[24]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[25]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[26]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[27]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[28]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[29]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[30]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[31]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[32]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[33]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[34]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[35]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[36]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[37]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[38]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[39]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[40]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[41]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[42]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[43]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[44]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[45]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[46]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[47]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[48]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[49]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[50]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[51]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[52]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[53]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[54]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[55]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[56]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[57]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[58]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[59]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[60]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[61]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[62]} {wallypipelinedsoc/hart/ifu/icache/InstrInF[63]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe101]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe101]
+connect_debug_port u_ila_0/probe101 [get_nets [list wallypipelinedsoc/hart/ifu/icache/InstrAckF ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe102]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe102]
+connect_debug_port u_ila_0/probe102 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[0]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[1]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[2]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[3]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[4]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[5]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[6]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[7]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[8]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[9]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[10]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[11]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[12]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[13]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[14]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[15]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[16]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[17]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[18]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[19]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[20]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[21]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[22]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[23]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[24]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[25]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[26]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[27]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[28]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[29]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[30]} {wallypipelinedsoc/hart/ifu/icache/InstrPAdrF[31]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe103]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
+connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/icache/InstrReadF ]]

From 6d2a4b835424a496a341ebbfa79258c98e300fbc Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Wed, 15 Dec 2021 10:25:08 -0600
Subject: [PATCH 40/95] Oups missed files in the last commit.

---
 fpga/generator/xlnx_ddr4.tcl               |   2 +-
 wally-pipelined/src/cache/icache.sv        |  10 +-
 wally-pipelined/src/uncore/uartPC16550D.sv | 162 ++++++++++-----------
 3 files changed, 87 insertions(+), 87 deletions(-)

diff --git a/fpga/generator/xlnx_ddr4.tcl b/fpga/generator/xlnx_ddr4.tcl
index 0b5e1a7e..5602ca50 100644
--- a/fpga/generator/xlnx_ddr4.tcl
+++ b/fpga/generator/xlnx_ddr4.tcl
@@ -41,7 +41,7 @@ set_property -dict [list CONFIG.C0.ControllerType {DDR4_SDRAM} \
 			CONFIG.C0.DDR4_CLKOUT0_DIVIDE {6} \
 			CONFIG.Reference_Clock {Differential} \
 			CONFIG.ADDN_UI_CLKOUT1.INSERT_VIP {0} \
-			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {23} \
+			CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {10} \
 			CONFIG.ADDN_UI_CLKOUT2.INSERT_VIP {0} \
 			CONFIG.ADDN_UI_CLKOUT2_FREQ_HZ {208} \
 			CONFIG.ADDN_UI_CLKOUT3.INSERT_VIP {0} \
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 7df4c4b8..372aeaec 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -36,11 +36,11 @@ module icache
    input logic ExceptionM, PendingInterruptM,
    
    // Data read in from the ebu unit
-   input logic [`XLEN-1:0]     InstrInF,
-   input logic 		       InstrAckF,
+   (* mark_debug = "true" *) input logic [`XLEN-1:0]     InstrInF,
+   (* mark_debug = "true" *) input logic 		       InstrAckF,
    // Read requested from the ebu unit
-   output logic [`PA_BITS-1:0] InstrPAdrF,
-   output logic 	       InstrReadF,
+   (* mark_debug = "true" *) output logic [`PA_BITS-1:0] InstrPAdrF,
+   (* mark_debug = "true" *) output logic 	       InstrReadF,
    // High if the instruction currently in the fetch stage is compressed
    output logic 	       CompressedF,
    // High if the icache is requesting a stall
@@ -52,7 +52,7 @@ module icache
    
    // The raw (not decompressed) instruction that was requested
    // If this instruction is compressed, upper 16 bits may be the next 16 bits or may be zeros
-   output logic [31:0] 	       FinalInstrRawF
+   (* mark_debug = "true" *) output logic [31:0] 	       FinalInstrRawF
    );
 
   // Configuration parameters
diff --git a/wally-pipelined/src/uncore/uartPC16550D.sv b/wally-pipelined/src/uncore/uartPC16550D.sv
index 09d89a2c..1f44c67e 100644
--- a/wally-pipelined/src/uncore/uartPC16550D.sv
+++ b/wally-pipelined/src/uncore/uartPC16550D.sv
@@ -31,90 +31,90 @@
 ///////////////////////////////////////////
 
 `include "wally-config.vh"
-  /* verilator lint_off UNOPTFLAT */
+/* verilator lint_off UNOPTFLAT */
 
 module uartPC16550D(
-  // Processor Interface
-  input  logic       HCLK, HRESETn,
-  input  logic [2:0] A,
-  input  logic [7:0] Din,
-  output logic [7:0] Dout,
-  input  logic       MEMRb, MEMWb, 
-  output logic       INTR, TXRDYb, RXRDYb,
-  // Clocks
-  output  logic      BAUDOUTb,
-  input   logic      RCLK,
-  // E1A Driver
-  input  logic       SIN, DSRb, DCDb, CTSb, RIb,
-  output logic       SOUT, RTSb, DTRb, OUT1b, OUT2b
-);
+	// Processor Interface
+	input logic 	   HCLK, HRESETn,
+	input logic [2:0]  A,
+	input logic [7:0]  Din,
+	output logic [7:0] Dout,
+	input logic 	   MEMRb, MEMWb, 
+	output logic 	   INTR, TXRDYb, RXRDYb,
+	// Clocks
+	output logic 	   BAUDOUTb,
+	input logic 	   RCLK,
+	// E1A Driver
+	input logic 	   SIN, DSRb, DCDb, CTSb, RIb,
+	output logic 	   SOUT, RTSb, DTRb, OUT1b, OUT2b
+	);
 
   // transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
   typedef enum {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
 
   // Registers
   logic [10:0] RBR;
-  logic [7:0] FCR, LCR, LSR, SCR, DLL, DLM;
-  logic [3:0] IER, MSR;
-  logic [4:0] MCR;
+  logic [7:0]  FCR, LCR, LSR, SCR, DLL, DLM;
+  logic [3:0]  IER, MSR;
+  logic [4:0]  MCR;
 
   // Syncrhonized and delayed UART signals
-  logic SINd, DSRbd, DCDbd, CTSbd, RIbd;
-  logic SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync;
-  logic DSRb2, DCDb2, CTSb2, RIb2;
-  logic SOUTbit;
+  logic 	   SINd, DSRbd, DCDbd, CTSbd, RIbd;
+  logic 	   SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync;
+  logic 	   DSRb2, DCDb2, CTSb2, RIb2;
+  logic 	   SOUTbit;
 
   // Control signals
-  logic loop; // loopback mode
-  logic DLAB; // Divisor Latch Access Bit (LCR bit 7)
+  logic 	   loop; // loopback mode
+  logic 	   DLAB; // Divisor Latch Access Bit (LCR bit 7)
 
   // Baud and rx/tx timing
-  logic baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
+  logic 	   baudpulse, txbaudpulse, rxbaudpulse; // high one system clk cycle each baud/16 period
   logic [16+`UART_PRESCALE-1:0] baudcount;
-  logic [3:0] 			rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
-  logic [3:0] rxbitsreceived, txbitssent;
+  logic [3:0] 					rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
+  logic [3:0] 					rxbitsreceived, txbitssent;
   statetype rxstate, txstate;
 
   // shift registrs and FIFOs
-  logic [9:0] rxshiftreg;
-  logic [10:0] rxfifo[15:0];
-  logic [7:0] txfifo[15:0];
-  logic [4:0] rxfifotailunwrapped;
-  logic [3:0] rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
-  logic [3:0] rxfifoentries, txfifoentries;
-  logic [3:0] rxbitsexpected, txbitsexpected;
+  logic [9:0] 					rxshiftreg;
+  logic [10:0] 					rxfifo[15:0];
+  logic [7:0] 					txfifo[15:0];
+  logic [4:0] 					rxfifotailunwrapped;
+  logic [3:0] 					rxfifohead, rxfifotail, txfifohead, txfifotail, rxfifotriggerlevel;
+  logic [3:0] 					rxfifoentries, txfifoentries;
+  logic [3:0] 					rxbitsexpected, txbitsexpected;
 
   // receive data
-  logic [10:0] RXBR;
-  logic [6:0] rxtimeoutcnt;
-  logic rxcentered;
-  logic rxparity, rxparitybit, rxstopbit;
-  logic rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
-  logic rxdataready;
-  logic rxfifoempty, rxfifotriggered, rxfifotimeout;
-  logic rxfifodmaready;
-  logic [8:0] rxdata9;
-  logic [7:0] rxdata;
-  logic [15:0] RXerrbit, rxfullbit;
-  logic [31:0] rxfullbitunwrapped;
+  logic [10:0] 					RXBR;
+  logic [6:0] 					rxtimeoutcnt;
+  logic 						rxcentered;
+  logic 						rxparity, rxparitybit, rxstopbit;
+  logic 						rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
+  logic 						rxdataready;
+  logic 						rxfifoempty, rxfifotriggered, rxfifotimeout;
+  logic 						rxfifodmaready;
+  logic [8:0] 					rxdata9;
+  logic [7:0] 					rxdata;
+  logic [15:0] 					RXerrbit, rxfullbit;
+  logic [31:0] 					rxfullbitunwrapped;
 
   // transmit data
-  logic [7:0] TXHR, nexttxdata;
-  logic [11:0] txdata, txsr;
-  logic txnextbit, txhrfull, txsrfull;
-  logic txparity;
-  logic txfifoempty, txfifofull, txfifodmaready;
+  logic [7:0] 					TXHR, nexttxdata;
+  logic [11:0] 					txdata, txsr;
+  logic 						txnextbit, txhrfull, txsrfull;
+  logic 						txparity;
+  logic 						txfifoempty, txfifofull, txfifodmaready;
 
   // control signals
-  logic fifoenabled, fifodmamodesel, evenparitysel;
+  logic 						fifoenabled, fifodmamodesel, evenparitysel;
 
   // interrupts
-  logic RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
-  logic THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
-  logic rxdataavailintr, modemstatusintr, intrpending;
-  logic [2:0] intrID;
+  logic 						RXerr, RXerrIP, squashRXerrIP, prevSquashRXerrIP, setSquashRXerrIP, resetSquashRXerrIP;
+  logic 						THRE, THRE_IP, squashTHRE_IP, prevSquashTHRE_IP, setSquashTHRE_IP, resetSquashTHRE_IP;
+  logic 						rxdataavailintr, modemstatusintr, intrpending;
+  logic [2:0] 					intrID;
 
-  logic baudpulseComb;
+  logic 						baudpulseComb;
 
   ///////////////////////////////////////////
   // Input synchronization: 2-stage synchronizer
@@ -122,7 +122,7 @@ module uartPC16550D(
   always_ff @(posedge HCLK) begin
     {SINd, DSRbd, DCDbd, CTSbd, RIbd} <= #1 {SIN, DSRb, DCDb, CTSb, RIb};
     {SINsync, DSRbsync, DCDbsync, CTSbsync, RIbsync} <= #1 loop ? {SOUTbit, ~MCR[0], ~MCR[3], ~MCR[1], ~MCR[2]} : 
-        {SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing
+														{SINd, DSRbd, DCDbd, CTSbd, RIbd}; // syncrhonized signals, handle loopback testing
     {DSRb2, DCDb2, CTSb2, RIb2} <= #1 {DSRbsync, DCDbsync, CTSbsync, RIbsync}; // for detecting state changes
   end
 
@@ -138,24 +138,24 @@ module uartPC16550D(
       LSR <= #1 8'b01100000;
       MSR <= #1 4'b0;
       if (`FPGA) begin
-	DLL <= #1 8'd25;
-	DLM <= #1 8'b0;
+		DLL <= #1 8'd11;
+		DLM <= #1 8'b0;
       end else begin
-	DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
-	DLM <= #1 8'b0;
+		DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
+		DLM <= #1 8'b0;
       end	
-/* -----\/----- EXCLUDED -----\/-----
- -----/\----- EXCLUDED -----/\----- */
+	  /* -----\/----- EXCLUDED -----\/-----
+	   -----/\----- EXCLUDED -----/\----- */
       SCR <= #1 8'b0; // not strictly necessary to reset
     end else begin
       if (~MEMWb) begin
         case (A)
-/* -----\/----- EXCLUDED -----\/-----
-          3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section
-          3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
- -----/\----- EXCLUDED -----/\----- */
-	  // *** BUG FIX ME for now for the divider to be 11.  Our clock is 23 Mhz.  23Mhz /(25 * 16) = 57600 baud, which is close enough to 57600 baud
-          3'b000: if (DLAB) DLL <= #1 8'd25; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
+		  /* -----\/----- EXCLUDED -----\/-----
+           3'b000: if (DLAB) DLL <= #1 Din; // else TXHR <= #1 Din; // TX handled in TX register/FIFO section
+           3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
+		   -----/\----- EXCLUDED -----/\----- */
+		  // *** BUG FIX ME for now for the divider to be 11.  Our clock is 23 Mhz.  23Mhz /(25 * 16) = 57600 baud, which is close enough to 57600 baud
+          3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
           3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
 
           3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
@@ -316,7 +316,7 @@ module uartPC16550D(
   assign rxfifoempty = (rxfifohead == rxfifotail);
   // verilator lint_off WIDTH
   assign rxfifoentries = (rxfifohead >= rxfifotail) ? (rxfifohead-rxfifotail) : 
-                                                      (rxfifohead + 16 - rxfifotail);
+                         (rxfifohead + 16 - rxfifotail);
   // verilator lint_on WIDTH
   assign rxfifotriggered = rxfifoentries >= rxfifotriggerlevel;
   //assign rxfifotimeout = rxtimeoutcnt[6]; // time out after 4 character periods; *** probably not right yet
@@ -335,10 +335,10 @@ module uartPC16550D(
     for (i=0; i<16; i++) begin:rx
       assign RXerrbit[i] = |rxfifo[i][10:8]; // are any of the error conditions set?
       assign rxfullbit[i] = rxfullbitunwrapped[i] | rxfullbitunwrapped[i+16];
-/*      if (i > 0)
-        assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
-      else
-        assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
+	  /*      if (i > 0)
+       assign rxfullbit[i] = ((rxfifohead==i) | rxfullbit[i-1]) & (rxfifotail != i);
+       else
+       assign rxfullbit[0] = ((rxfifohead==i) | rxfullbit[15]) & (rxfifotail != i);*/
     end
   endgenerate
   assign rxfifohaserr = |(RXerrbit & rxfullbit);
@@ -361,7 +361,7 @@ module uartPC16550D(
     end
 
   ///////////////////////////////////////////
-  // transmit timing and control
+	// transmit timing and control
   ///////////////////////////////////////////
   always_ff @(posedge HCLK, negedge HRESETn)
     if (~HRESETn) begin
@@ -414,7 +414,7 @@ module uartPC16550D(
       3'b111: txdata = {1'b0, nexttxdata[0], nexttxdata[1], nexttxdata[2], nexttxdata[3], nexttxdata[4], nexttxdata[5], nexttxdata[6], nexttxdata[7], txparity, 2'b11};    // 8 data, parity
     endcase
   end
-       
+  
   // registers & FIFO
   always_ff @(posedge HCLK, negedge HRESETn)
     if (~HRESETn) begin
@@ -429,7 +429,7 @@ module uartPC16550D(
           txhrfull <= #1 1;
         end
         $write("%c",Din); // for testbench
-       end
+      end
       if (txstate == UART_IDLE) begin // move data into tx shift register if available
         if (fifoenabled) begin 
           if (~txfifoempty) begin
@@ -453,7 +453,7 @@ module uartPC16550D(
   assign txfifoempty = (txfifohead == txfifotail);
   // verilator lint_off WIDTH
   assign txfifoentries = (txfifohead >= txfifotail) ? (txfifohead-txfifotail) : 
-                                                      (txfifohead + 16 - txfifotail);
+                         (txfifohead + 16 - txfifotail);
   // verilator lint_on WIDTH
   assign txfifofull = (txfifoentries == 4'b1111);
 
@@ -480,7 +480,7 @@ module uartPC16550D(
   assign THRE = fifoenabled ? txfifoempty : ~txhrfull;
   assign THRE_IP = THRE & ~squashTHRE_IP; // THRE_IP squashed upon reading IIR
   assign modemstatusintr = |MSR[3:0]; // set interrupt when modem pins change
- 
+  
   // IIR: interrupt priority (Table 5)
   // set intrID based on highest priority pending interrupt source; otherwise, no interrupt is pending
   always_comb begin
@@ -532,4 +532,4 @@ module uartPC16550D(
 
 endmodule
 
-  /* verilator lint_on UNOPTFLAT */
+/* verilator lint_on UNOPTFLAT */

From 4e35736e90900684632b0d1f85cbf654ef31a99e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 15 Dec 2021 11:38:26 -0800
Subject: [PATCH 41/95] IEU cleanup:

---
 wally-pipelined/src/ieu/datapath.sv | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 83c1f918..ef35f2f5 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -78,11 +78,11 @@ module datapath (
   logic [`XLEN-1:0] SrcAE, SrcBE;
   logic [`XLEN-1:0] SrcAE2, SrcBE2;
 
-  logic [`XLEN-1:0] ALUResultE, AltResultE, ALUPreResultE;
+  logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
   logic [`XLEN-1:0] WriteDataE;
   logic [`XLEN-1:0] AddressE;
   // Memory stage signals
-  logic [`XLEN-1:0] ALUResultM;
+  logic [`XLEN-1:0] IEUResultM;
   logic [`XLEN-1:0] ResultM;
   // Writeback stage signals
   logic [`XLEN-1:0] SCResultW;
@@ -108,22 +108,22 @@ module datapath (
   mux3  #(`XLEN)  faemux(RD1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);
   mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
   mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
+  comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
-  alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUPreResultE, AddressE);
-  comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
+  alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, AddressE);
   mux2 #(`XLEN)   altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
-  mux2 #(`XLEN)   aluresultmux(ALUPreResultE, AltResultE, ALUResultSrcE, ALUResultE);
+  mux2 #(`XLEN)   ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
+  assign MemAdrE = AddressE;   // *** clean up this naming
+  assign PCTargetE = AddressE; // *** clean up this naming
 
   // Memory stage pipeline register
   flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
-  flopenrc #(`XLEN) ALUResultMReg(clk, reset, FlushM, ~StallM, ALUResultE, ALUResultM);
-  assign MemAdrE = AddressE;   // *** clean up this naming
-  assign PCTargetE = AddressE; // *** clean up this naming
+  flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
   flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, MemAdrE, MemAdrM);
   flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
   flopenrc #(5)     RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);	
-  mux2  #(`XLEN)    resultmuxM(ALUResultM, FIntResM, FWriteIntM, ResultM);
+  mux2  #(`XLEN)    resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
   
   // Writeback stage pipeline register and logic
   flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW);

From aebd746e71b72ebf7acb869441f18561e6f64330 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 15 Dec 2021 12:10:45 -0800
Subject: [PATCH 42/95] Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop
 from IEU to LSU to reduce wires crossing hierarchies

---
 wally-pipelined/src/cache/dcache.sv             |  4 ++--
 wally-pipelined/src/ieu/datapath.sv             | 10 +++-------
 wally-pipelined/src/ieu/ieu.sv                  |  8 ++++----
 wally-pipelined/src/ifu/bpred.sv                |  6 +++---
 wally-pipelined/src/ifu/ifu.sv                  |  8 ++++----
 wally-pipelined/src/lsu/lsu.sv                  | 12 +++++++-----
 wally-pipelined/src/lsu/lsuArb.sv               |  4 ++--
 wally-pipelined/src/wally/wallypipelinedhart.sv | 11 +++++------
 wally-pipelined/testbench/testbench-linux.sv    |  2 +-
 9 files changed, 31 insertions(+), 34 deletions(-)

diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 4c7180a3..b546a82b 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -36,7 +36,7 @@ module dcache
    input logic [6:0] 	       Funct7M,
    input logic [1:0] 	       AtomicM,
    input logic 		       FlushDCacheM,
-   input logic [11:0] 	       MemAdrE, // virtual address, but we only use the lower 12 bits.
+   input logic [11:0] 	       IEUAdrE, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0]  MemPAdrM, // physical address
    input logic [11:0] 	       VAdr, // when hptw writes dtlb we use this address to index SRAM.
 
@@ -147,7 +147,7 @@ module dcache
   // Read Path CPU (IEU) side
 
   mux4 #(INDEXLEN)
-  AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+  AdrSelMux(.d0(IEUAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d3(FlushAdr),
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index ef35f2f5..d0a046e1 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -43,14 +43,14 @@ module datapath (
   input  logic [`XLEN-1:0] PCE,
   input  logic [`XLEN-1:0] PCLinkE,
   output logic [2:0]       FlagsE,
-  output logic [`XLEN-1:0] PCTargetE,
+  output logic [`XLEN-1:0] IEUAdrE,
   output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
   // Memory stage signals
   input  logic             StallM, FlushM,
   input  logic             FWriteIntM,
   input  logic [`XLEN-1:0] FIntResM,
   output logic [`XLEN-1:0] SrcAM,
-  output logic [`XLEN-1:0] WriteDataM, MemAdrM, MemAdrE,
+  output logic [`XLEN-1:0] WriteDataM, 
   // Writeback stage signals
   input  logic             StallW, FlushW,
   input  logic             FWriteIntW,
@@ -80,7 +80,6 @@ module datapath (
 
   logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE;
   logic [`XLEN-1:0] WriteDataE;
-  logic [`XLEN-1:0] AddressE;
   // Memory stage signals
   logic [`XLEN-1:0] IEUResultM;
   logic [`XLEN-1:0] ResultM;
@@ -111,16 +110,13 @@ module datapath (
   comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
-  alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, AddressE);
+  alu   #(`XLEN)  alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE);
   mux2 #(`XLEN)   altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE);
   mux2 #(`XLEN)   ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
-  assign MemAdrE = AddressE;   // *** clean up this naming
-  assign PCTargetE = AddressE; // *** clean up this naming
 
   // Memory stage pipeline register
   flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
   flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
-  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, MemAdrE, MemAdrM);
   flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
   flopenrc #(5)     RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);	
   mux2  #(`XLEN)    resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index 4619b337..101ca4da 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -37,7 +37,7 @@ module ieu (
   input logic 		   FWriteIntE, 
   input logic 		   IllegalFPUInstrE,
   input logic [`XLEN-1:0]  FWriteDataE,
-  output logic [`XLEN-1:0] PCTargetE,
+  output logic [`XLEN-1:0] IEUAdrE,
   output logic 		   MulDivE, W64E,
   output logic [2:0] 	   Funct3E,
   output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
@@ -49,7 +49,7 @@ module ieu (
   output logic [1:0] 	   MemRWM, // read/write control goes to LSU
   output logic [1:0] 	   AtomicE, // atomic control goes to LSU	    
   output logic [1:0] 	   AtomicM, // atomic control goes to LSU
-  output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU
+  output logic [`XLEN-1:0] WriteDataM, // Address and write data to LSU
 
   output logic [2:0] 	   Funct3M, // size and signedness to LSU
   output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
@@ -127,11 +127,11 @@ module ieu (
     .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE,
     .ALUResultSrcE, .JumpE, .IllegalFPUInstrE,
     .FWriteDataE, .PCE, .PCLinkE, .FlagsE,
-    .PCTargetE,
+    .IEUAdrE,
     .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
     // Memory stage signals
     .StallM, .FlushM, .FWriteIntM, .FIntResM, 
-    .SrcAM, .WriteDataM, .MemAdrM, .MemAdrE,
+    .SrcAM, .WriteDataM,
     // Writeback stage signals
     .StallW, .FlushW, .FWriteIntW, .RegWriteW, 
     .SquashSCW, .ResultSrcW, .ReadDataW,
diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv
index 3121e725..56308b1d 100644
--- a/wally-pipelined/src/ifu/bpred.sv
+++ b/wally-pipelined/src/ifu/bpred.sv
@@ -45,7 +45,7 @@ module bpred
    // *** the specifics of how this is encode is subject to change.
    input logic              PCSrcE, // AKA Branch Taken
    // Signals required to check the branch prediction accuracy.
-   input logic [`XLEN-1:0]  PCTargetE, // The branch destination if the branch is taken.
+   input logic [`XLEN-1:0]  IEUAdrE, // The branch destination if the branch is taken.
    input logic [`XLEN-1:0]  PCD, // The address the branch predictor took.
    input logic [`XLEN-1:0]  PCLinkE, // The address following the branch instruction. (AKA Fall through address)
    input logic [4:0]        InstrClassE,
@@ -165,7 +165,7 @@ module bpred
           // update
           .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
           .UpdatePC(PCE),
-          .UpdateTarget(PCTargetE),
+          .UpdateTarget(IEUAdrE),
           .UpdateInvalid(PredictionInstrClassWrongE),
           .UpdateInstrClass(InstrClassE));
 
@@ -218,7 +218,7 @@ module bpred
   // Check the prediction makes execution.
 
   // first check if the target or fallthrough address matches what was predicted.
-  assign TargetWrongE = PCTargetE != PCD;
+  assign TargetWrongE = IEUAdrE != PCD;
   assign FallThroughWrongE = PCLinkE != PCD;
   // If the target is taken check the target rather than fallthrough.  The instruction needs to be a branch if PCSrcE is selected
   // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken.  If the real instruction is non cfi
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 09322609..8bc8a185 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -40,7 +40,7 @@ module ifu (
   // Execute
   output logic [`XLEN-1:0]    PCLinkE,
   input logic 		      PCSrcE, 
-  input logic [`XLEN-1:0]     PCTargetE,
+  input logic [`XLEN-1:0]     IEUAdrE,
   output logic [`XLEN-1:0]    PCE,
   output logic 		      BPPredWrongE, 
   // Mem
@@ -223,7 +223,7 @@ module ifu (
     .SelBPPredF(SelBPPredF),
     .PCE(PCE),
     .PCSrcE(PCSrcE),
-    .PCTargetE(PCTargetE),
+    .IEUAdrE(IEUAdrE),
     .PCD(PCD),
     .PCLinkE(PCLinkE),
     .InstrClassE(InstrClassE),
@@ -242,8 +242,8 @@ module ifu (
       assign BPPredClassNonCFIWrongE = 1'b0;
     end      
   endgenerate
-  // The true correct target is PCTargetE if PCSrcE is 1 else it is the fall through PCLinkE.
-  assign PCCorrectE =  PCSrcE ? PCTargetE : PCLinkE;
+  // The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE.
+  assign PCCorrectE =  PCSrcE ? IEUAdrE : PCLinkE;
 
   // pcadder
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 791e4d4a..6fcf4013 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -49,9 +49,9 @@ module lsu
    output logic 	       DCacheAccess,
 
    // address and write data
-   input logic [`XLEN-1:0]     MemAdrM,
-   input logic [`XLEN-1:0]     MemAdrE,
-   input logic [`XLEN-1:0]     WriteDataM, 
+   input  logic [`XLEN-1:0]    IEUAdrE,
+   output logic [`XLEN-1:0]    MemAdrM,
+   input  logic [`XLEN-1:0]    WriteDataM, 
    output logic [`XLEN-1:0]    ReadDataM,
 
    // cpu privilege
@@ -129,6 +129,8 @@ module lsu
 
   assign AnyCPUReqM = (|MemRWM)  | (|AtomicM);
 
+  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, MemAdrM);
+
   // *** add generate to conditionally create hptw, lsuArb, and mmu
   // based on `MEM_VIRTMEM
   hptw hptw(.clk(clk),
@@ -169,7 +171,7 @@ module lsu
 		 .Funct3M(Funct3M),
 		 .AtomicM(AtomicM),
 		 .MemAdrM(MemAdrM),
-		 .MemAdrE(MemAdrE[11:0]),		 
+		 .IEUAdrE(IEUAdrE[11:0]),		 
 		 .CommittedM(CommittedM),
 		 .PendingInterruptM(PendingInterruptM),		
 		 .StallW(StallW),
@@ -251,7 +253,7 @@ module lsu
 		.Funct7M(Funct7M),
 		.FlushDCacheM,
 		.AtomicM(AtomicMtoDCache),
-		.MemAdrE(MemAdrEtoDCache),
+		.IEUAdrE(MemAdrEtoDCache),
 		.MemPAdrM(MemPAdrM),
 		.VAdr(MemAdrM[11:0]),		
 		.WriteDataM(WriteDataM),
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index c0647c2b..be73b085 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -40,7 +40,7 @@ module lsuArb
    input logic [2:0] 	       Funct3M,
    input logic [1:0] 	       AtomicM,
    input logic [`XLEN-1:0]     MemAdrM,
-   input logic [11:0] 	       MemAdrE,
+   input logic [11:0] 	       IEUAdrE,
    input logic 		       StallW,
    input logic 		       PendingInterruptM,
    // to CPU
@@ -85,7 +85,7 @@ module lsuArb
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
   assign MemAdrMExt = {2'b00, MemAdrM};
   assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0]; 
-  assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : MemAdrE[11:0];  
+  assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];  
   assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.
   assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 4e8dbc47..13c2e77a 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -68,7 +68,6 @@ module wallypipelinedhart (
   (* mark_debug = "true" *) logic [31:0] 		    InstrM;
   logic [`XLEN-1:0] 	    PCF, PCD, PCE, PCLinkE;
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    PCM;
-  logic [`XLEN-1:0] 	    PCTargetE;
   logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
   logic [`XLEN-1:0] 	    PrivilegedNextPCM;
   (* mark_debug = "true" *) logic [1:0] 		    MemRWM;
@@ -122,7 +121,7 @@ module wallypipelinedhart (
 
   // cpu lsu interface
   logic [2:0] 		    Funct3M;
-  logic [`XLEN-1:0] 	    MemAdrE;
+  logic [`XLEN-1:0] 	    IEUAdrE;
   (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    MemAdrM;  
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    ReadDataM;
@@ -170,7 +169,7 @@ module wallypipelinedhart (
     .InstrReadF, .ICacheStallF,
 
     // Execute
-    .PCLinkE, .PCSrcE, .PCTargetE, .PCE,
+    .PCLinkE, .PCSrcE, .IEUAdrE, .PCE,
     .BPPredWrongE, 
   
     // Mem
@@ -209,7 +208,7 @@ module wallypipelinedhart (
 
      // Execute Stage interface
      .PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE,
-     .FWriteDataE, .PCTargetE, .MulDivE, .W64E,
+     .FWriteDataE, .IEUAdrE, .MulDivE, .W64E,
      .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
      //.SrcAE, .SrcBE, 
      .FWriteIntM,
@@ -219,7 +218,7 @@ module wallypipelinedhart (
      .MemRWM, // read/write control goes to LSU
      .AtomicE, // atomic control goes to LSU	    
      .AtomicM, // atomic control goes to LSU
-     .MemAdrM, .MemAdrE, .WriteDataM, // Address and write data to LSU
+     .WriteDataM, // Write data to LSU
      .Funct3M, // size and signedness to LSU
      .SrcAM, // to privilege and fpu
      .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
@@ -248,7 +247,7 @@ module wallypipelinedhart (
 	.CommittedM, .DCacheMiss, .DCacheAccess,
 	.SquashSCW,            
 	//.DataMisalignedM(DataMisalignedM),
-	.MemAdrE, .MemAdrM, .WriteDataM,
+	.IEUAdrE, .MemAdrM, .WriteDataM,
 	.ReadDataM, .FlushDCacheM,
 	// connected to ahb (all stay the same)
 	.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index b09b19aa..a64ca434 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -100,7 +100,7 @@ module testbench();
   flopenrc #(`XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
   flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
   flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
-  flopenrc #(`XLEN)     MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.dp.MemAdrM, MemAdrW);
+  flopenrc #(`XLEN)     MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.MemAdrM, MemAdrW);
   flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);  
   flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
 

From d9f569afe188e21e2ca0d1c5ca5822f147902cbb Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 15 Dec 2021 12:38:35 -0800
Subject: [PATCH 43/95] Added irscv-arch-test and rsicv-isa-sim

---
 addins/riscv-arch-test | 2 +-
 addins/riscv-isa-sim   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index 84d04381..be67c99b 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit 84d043817f75f752c9873326475e11f16e3a6f7c
+Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
diff --git a/addins/riscv-isa-sim b/addins/riscv-isa-sim
index d22b2801..0f30988e 160000
--- a/addins/riscv-isa-sim
+++ b/addins/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit d22b280198e74b871e04fc0ddb622fb825fdae49
+Subproject commit 0f30988e4d0e8daac893834b91979f7700bab481

From ee81cfff0cbebba97ee28394966e31e26259ec00 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 17 Dec 2021 14:38:25 -0600
Subject: [PATCH 44/95] Possible fix for icache deadlock interaction with hptw.

---
 wally-pipelined/src/cache/icachefsm.sv | 21 ++++++++++++++++++---
 wally-pipelined/src/lsu/lsu.sv         |  8 ++++----
 wally-pipelined/src/lsu/lsuArb.sv      |  6 ++----
 wally-pipelined/src/mmu/hptw.sv        | 22 +++++++++++++---------
 4 files changed, 37 insertions(+), 20 deletions(-)

diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index b104de4e..96bea67c 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -137,9 +137,16 @@ module icachefsm
       STATE_READY: begin
         SelAdr = 2'b00;
         ICacheReadEn = 1'b1;
+/* -----\/----- EXCLUDED -----\/-----
         if (ITLBMissF & ~(ExceptionM | PendingInterruptM)) begin
           NextState = STATE_TLB_MISS;
-        end else if (hit & ~spill) begin
+        end else 
+ -----/\----- EXCLUDED -----/\----- */
+		if(ITLBMissF) begin
+		  NextState = STATE_READY;
+		  ICacheStallF = 1'b0;
+		end
+		else if (hit & ~spill) begin
           ICacheStallF = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  if(StallF) begin
@@ -325,6 +332,7 @@ module icachefsm
           NextState = STATE_READY;
 		end
       end
+/* -----\/----- EXCLUDED -----\/-----
       STATE_TLB_MISS: begin
         if (WalkerInstrPageFaultF) begin
           NextState = STATE_READY;
@@ -341,11 +349,15 @@ module icachefsm
 		SelAdr = 2'b01;
         NextState = STATE_READY;
       end
+ -----/\----- EXCLUDED -----/\----- */
       STATE_CPU_BUSY: begin
 		ICacheStallF = 1'b0;
+/* -----\/----- EXCLUDED -----\/-----
 		if (ITLBMissF) begin
           NextState = STATE_TLB_MISS;
-		end else if(StallF) begin
+		end else
+ -----/\----- EXCLUDED -----/\----- */
+        if(StallF) begin
 		  NextState = STATE_CPU_BUSY;
 		  SelAdr = 2'b01;
 		end
@@ -356,9 +368,12 @@ module icachefsm
       STATE_CPU_BUSY_SPILL: begin
 		ICacheStallF = 1'b0;
 		ICacheReadEn = 1'b1;
+/* -----\/----- EXCLUDED -----\/-----
 		if (ITLBMissF) begin
           NextState = STATE_TLB_MISS;
-		end else if(StallF) begin
+		end else 
+ -----/\----- EXCLUDED -----/\----- */
+		if(StallF) begin
 		  NextState = STATE_CPU_BUSY_SPILL;
 		  SelAdr = 2'b10;
 		end
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 791e4d4a..9d83c7b5 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -144,16 +144,18 @@ module lsu
 	    .ITLBWriteF(ITLBWriteF),
 	    .DTLBWriteM(DTLBWriteM),
 	    .HPTWReadPTE(ReadDataM),
-	    .HPTWStall(HPTWStall),
-            .TranslationPAdr,			  
+	    .DCacheStall(DCacheStall),
+        .TranslationPAdr,			  
 	    .HPTWRead(HPTWRead),
 	    .SelPTW(SelPTW),
+		.HPTWStall,
 	    .AnyCPUReqM,
 	    .MemAfterIWalkDone,
 	    .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
 	    .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
 	    .WalkerStorePageFaultM(WalkerStorePageFaultM));
 
+  assign LSUStall = DCacheStall | HPTWStall;
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
@@ -163,7 +165,6 @@ module lsu
 		 .SelPTW(SelPTW),
 		 .HPTWRead(HPTWRead),
 		 .TranslationPAdrE(TranslationPAdr),
-		 .HPTWStall(HPTWStall),		 
 		 // CPU connection
 		 .MemRWM(MemRWM),
 		 .Funct3M(Funct3M),
@@ -174,7 +175,6 @@ module lsu
 		 .PendingInterruptM(PendingInterruptM),		
 		 .StallW(StallW),
 		 .DataMisalignedM(DataMisalignedM),
-		 .LSUStall(LSUStall),
 		 // DCACHE
 		 .DisableTranslation(DisableTranslation),
 		 .MemRWMtoLRSC(MemRWMtoLRSC),
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index c0647c2b..05cdf0ad 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -33,7 +33,6 @@ module lsuArb
    input logic 		       SelPTW,
    input logic 		       HPTWRead,
    input logic [`PA_BITS-1:0]  TranslationPAdrE,
-   output logic 	       HPTWStall, 
 
    // from CPU
    input logic [1:0] 	       MemRWM,
@@ -46,7 +45,7 @@ module lsuArb
    // to CPU
    output logic 	       DataMisalignedM,
    output logic 	       CommittedM,
-   output logic 	       LSUStall, 
+   //output logic 	       LSUStall, 
   
    // to D Cache
    output logic 	       DisableTranslation, 
@@ -98,10 +97,9 @@ module lsuArb
   // not clear at all.  I think it should be LSUStall from the LSU,
   // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
   //assign HPTWStall = SelPTW ? DCacheStall : 1'b1;  
-  assign HPTWStall = DCacheStall;  
 
   assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
 
-  assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
+  //assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
   
 endmodule
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index 5ca5032e..b386b474 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -38,13 +38,14 @@ module hptw
    input logic 		       ITLBMissF, DTLBMissM, // TLB Miss
    input logic [1:0] 	       MemRWM, // 10 = read, 01 = write
    input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU
-   input logic 		       HPTWStall, // stall from LSU
+   input logic 		       DCacheStall, // stall from LSU
    input logic 		       MemAfterIWalkDone,
    input logic 		       AnyCPUReqM,
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0] 	       PageType, // page type to TLBs
    output logic 	       ITLBWriteF, DTLBWriteM, // write TLB with new entry
    output logic 	       SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU
+   output logic            HPTWStall,
    output logic [`PA_BITS-1:0] TranslationPAdr,
    output logic 	       HPTWRead, // HPTW requesting to read memory
    output logic 	       WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
@@ -54,7 +55,7 @@ module hptw
 				     L1_ADR, L1_RD, 
 				     L2_ADR, L2_RD, 
 				     L3_ADR, L3_RD, 
-				     LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
+				     LEAF, LEAF_DELAY, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
 
   generate
     if (`MEM_VIRTMEM) begin
@@ -86,7 +87,7 @@ module hptw
 
 	  // State flops
  	  flopenr #(1) TLBMissMReg(clk, reset, StartWalk, DTLBMissM, DTLBWalk); // when walk begins, record whether it was for DTLB (or record 0 for ITLB)
-	  assign PRegEn = HPTWRead & ~HPTWStall;
+	  assign PRegEn = HPTWRead & ~DCacheStall;
   	  flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
 	
       // Assign PTE descriptors common across all XLEN values
@@ -100,7 +101,8 @@ module hptw
 	  // Enable and select signals based on states
       assign StartWalk = (WalkerState == IDLE) & TLBMiss;
 	  assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
-	  assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT) & (WalkerState != LEAF);
+	  assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT) & (WalkerState != LEAF) & (WalkerState != LEAF_DELAY);
+	  assign HPTWStall = (WalkerState != IDLE) & (WalkerState != FAULT);
 	  assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
 	  assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
 
@@ -168,7 +170,7 @@ module hptw
 	    IDLE: if (TLBMiss)	 		NextWalkerState = InitialWalkerState;
 		      else 					NextWalkerState = IDLE;
 	    L3_ADR: 			NextWalkerState = L3_RD; // first access in SV48
-	    L3_RD: if (HPTWStall) NextWalkerState = L3_RD;
+	    L3_RD: if (DCacheStall) NextWalkerState = L3_RD;
 	                else 			NextWalkerState = L2_ADR;
 //	    LEVEL3: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
 //		  		else if (ValidNonLeafPTE) NextWalkerState = L2_ADR;
@@ -177,7 +179,7 @@ module hptw
 				else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
 		  		else if (ValidNonLeafPTE) NextWalkerState = L2_RD;
 		 		else 				NextWalkerState = FAULT;			
-	    L2_RD: if (HPTWStall) NextWalkerState = L2_RD;
+	    L2_RD: if (DCacheStall) NextWalkerState = L2_RD;
 	      			else 			NextWalkerState = L1_ADR;
 //	    LEVEL2: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
 //				else if (ValidNonLeafPTE) NextWalkerState = L1_ADR;
@@ -186,7 +188,7 @@ module hptw
 				else if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
 		  		else if (ValidNonLeafPTE) NextWalkerState = L1_RD;
 		 		else 				NextWalkerState = FAULT;	
-	    L1_RD: if (HPTWStall) NextWalkerState = L1_RD;
+	    L1_RD: if (DCacheStall) NextWalkerState = L1_RD;
 	      			else 			NextWalkerState = L0_ADR;
 //	    LEVEL1: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF;
 //	      		else if (ValidNonLeafPTE) NextWalkerState = L0_ADR;
@@ -194,11 +196,13 @@ module hptw
 	    L0_ADR: if (ValidLeafPTE && ~Misaligned) NextWalkerState = LEAF; // could shortcut this by a cyle for all Lx_ADR superpages
 		  		else if (ValidNonLeafPTE) NextWalkerState = L0_RD;
 		 		else 				NextWalkerState = FAULT;
-	    L0_RD: if (HPTWStall) NextWalkerState = L0_RD;
+	    L0_RD: if (DCacheStall) NextWalkerState = L0_RD;
 	      			else 			NextWalkerState = LEAF;
 //	    LEVEL0: if (ValidLeafPTE) 	NextWalkerState = LEAF;
 //				else 				NextWalkerState = FAULT;
-	    LEAF: 						NextWalkerState = IDLE;
+	    LEAF: 	if (DTLBWalk)		NextWalkerState = IDLE; // updates TLB
+		        else                NextWalkerState = LEAF_DELAY;
+	    LEAF_DELAY: 				NextWalkerState = IDLE;		 // give time to allow address translation
 	    FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
  	                        else NextWalkerState = IDLE;
 	    default: begin

From a11597b6bd767728bcf0d7ec675dd923aac9a13f Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 17 Dec 2021 14:40:25 -0600
Subject: [PATCH 45/95] Added more debugging code for FPGA.

---
 fpga/constraints/debug2.xdc                  | 103 +++++++++++++++++++
 fpga/generator/wally.tcl                     |   6 +-
 wally-pipelined/src/ebu/ahblite.sv           |  52 +++++-----
 wally-pipelined/src/ifu/ifu.sv               |   4 +-
 wally-pipelined/src/lsu/lsu.sv               |   2 +-
 wally-pipelined/src/mmu/hptw.sv              |   6 +-
 wally-pipelined/src/privileged/csrc.sv       |   2 +-
 wally-pipelined/src/privileged/privileged.sv |   2 +-
 8 files changed, 140 insertions(+), 37 deletions(-)

diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index f026114b..6cf9d3a8 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -46,10 +46,12 @@ create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe7]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
 connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/PCM[0]} {wallypipelinedsoc/hart/PCM[1]} {wallypipelinedsoc/hart/PCM[2]} {wallypipelinedsoc/hart/PCM[3]} {wallypipelinedsoc/hart/PCM[4]} {wallypipelinedsoc/hart/PCM[5]} {wallypipelinedsoc/hart/PCM[6]} {wallypipelinedsoc/hart/PCM[7]} {wallypipelinedsoc/hart/PCM[8]} {wallypipelinedsoc/hart/PCM[9]} {wallypipelinedsoc/hart/PCM[10]} {wallypipelinedsoc/hart/PCM[11]} {wallypipelinedsoc/hart/PCM[12]} {wallypipelinedsoc/hart/PCM[13]} {wallypipelinedsoc/hart/PCM[14]} {wallypipelinedsoc/hart/PCM[15]} {wallypipelinedsoc/hart/PCM[16]} {wallypipelinedsoc/hart/PCM[17]} {wallypipelinedsoc/hart/PCM[18]} {wallypipelinedsoc/hart/PCM[19]} {wallypipelinedsoc/hart/PCM[20]} {wallypipelinedsoc/hart/PCM[21]} {wallypipelinedsoc/hart/PCM[22]} {wallypipelinedsoc/hart/PCM[23]} {wallypipelinedsoc/hart/PCM[24]} {wallypipelinedsoc/hart/PCM[25]} {wallypipelinedsoc/hart/PCM[26]} {wallypipelinedsoc/hart/PCM[27]} {wallypipelinedsoc/hart/PCM[28]} {wallypipelinedsoc/hart/PCM[29]} {wallypipelinedsoc/hart/PCM[30]} {wallypipelinedsoc/hart/PCM[31]} {wallypipelinedsoc/hart/PCM[32]} {wallypipelinedsoc/hart/PCM[33]} {wallypipelinedsoc/hart/PCM[34]} {wallypipelinedsoc/hart/PCM[35]} {wallypipelinedsoc/hart/PCM[36]} {wallypipelinedsoc/hart/PCM[37]} {wallypipelinedsoc/hart/PCM[38]} {wallypipelinedsoc/hart/PCM[39]} {wallypipelinedsoc/hart/PCM[40]} {wallypipelinedsoc/hart/PCM[41]} {wallypipelinedsoc/hart/PCM[42]} {wallypipelinedsoc/hart/PCM[43]} {wallypipelinedsoc/hart/PCM[44]} {wallypipelinedsoc/hart/PCM[45]} {wallypipelinedsoc/hart/PCM[46]} {wallypipelinedsoc/hart/PCM[47]} {wallypipelinedsoc/hart/PCM[48]} {wallypipelinedsoc/hart/PCM[49]} {wallypipelinedsoc/hart/PCM[50]} {wallypipelinedsoc/hart/PCM[51]} {wallypipelinedsoc/hart/PCM[52]} {wallypipelinedsoc/hart/PCM[53]} {wallypipelinedsoc/hart/PCM[54]} {wallypipelinedsoc/hart/PCM[55]} {wallypipelinedsoc/hart/PCM[56]} {wallypipelinedsoc/hart/PCM[57]} {wallypipelinedsoc/hart/PCM[58]} {wallypipelinedsoc/hart/PCM[59]} {wallypipelinedsoc/hart/PCM[60]} {wallypipelinedsoc/hart/PCM[61]} {wallypipelinedsoc/hart/PCM[62]} {wallypipelinedsoc/hart/PCM[63]} ]]
+
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe8]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
 connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]} ]]
+
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe9]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
@@ -467,3 +469,104 @@ create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe103]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe103]
 connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/hart/ifu/icache/InstrReadF ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe104]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
+connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[0]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[1]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[2]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[3]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[4]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[5]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[6]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[7]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[8]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[9]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[10]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[11]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[12]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[13]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[14]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[15]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[16]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[17]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[18]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[19]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[20]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[21]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[22]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[23]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[24]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[25]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[26]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[27]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[28]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[29]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[30]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[31]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[32]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[33]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[34]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[35]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[36]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[37]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[38]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[39]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[40]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[41]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[42]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[43]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[44]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[45]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[46]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[47]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[48]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[49]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[50]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[51]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[52]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[53]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[54]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[55]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[56]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[57]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[58]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[59]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[60]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[61]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[62]} {wallypipelinedsoc/hart/priv/csr/counters/INSTRET_REGW[63]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe105]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe105]
+connect_debug_port u_ila_0/probe105 [get_nets [list {wallypipelinedsoc/hart/ebu/HRDATA[0]} {wallypipelinedsoc/hart/ebu/HRDATA[1]} {wallypipelinedsoc/hart/ebu/HRDATA[2]} {wallypipelinedsoc/hart/ebu/HRDATA[3]} {wallypipelinedsoc/hart/ebu/HRDATA[4]} {wallypipelinedsoc/hart/ebu/HRDATA[5]} {wallypipelinedsoc/hart/ebu/HRDATA[6]} {wallypipelinedsoc/hart/ebu/HRDATA[7]} {wallypipelinedsoc/hart/ebu/HRDATA[8]} {wallypipelinedsoc/hart/ebu/HRDATA[9]} {wallypipelinedsoc/hart/ebu/HRDATA[10]} {wallypipelinedsoc/hart/ebu/HRDATA[11]} {wallypipelinedsoc/hart/ebu/HRDATA[12]} {wallypipelinedsoc/hart/ebu/HRDATA[13]} {wallypipelinedsoc/hart/ebu/HRDATA[14]} {wallypipelinedsoc/hart/ebu/HRDATA[15]} {wallypipelinedsoc/hart/ebu/HRDATA[16]} {wallypipelinedsoc/hart/ebu/HRDATA[17]} {wallypipelinedsoc/hart/ebu/HRDATA[18]} {wallypipelinedsoc/hart/ebu/HRDATA[19]} {wallypipelinedsoc/hart/ebu/HRDATA[20]} {wallypipelinedsoc/hart/ebu/HRDATA[21]} {wallypipelinedsoc/hart/ebu/HRDATA[22]} {wallypipelinedsoc/hart/ebu/HRDATA[23]} {wallypipelinedsoc/hart/ebu/HRDATA[24]} {wallypipelinedsoc/hart/ebu/HRDATA[25]} {wallypipelinedsoc/hart/ebu/HRDATA[26]} {wallypipelinedsoc/hart/ebu/HRDATA[27]} {wallypipelinedsoc/hart/ebu/HRDATA[28]} {wallypipelinedsoc/hart/ebu/HRDATA[29]} {wallypipelinedsoc/hart/ebu/HRDATA[30]} {wallypipelinedsoc/hart/ebu/HRDATA[31]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe106]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe106]
+connect_debug_port u_ila_0/probe106 [get_nets [list {wallypipelinedsoc/hart/ebu/HWDATA[0]} {wallypipelinedsoc/hart/ebu/HWDATA[1]} {wallypipelinedsoc/hart/ebu/HWDATA[2]} {wallypipelinedsoc/hart/ebu/HWDATA[3]} {wallypipelinedsoc/hart/ebu/HWDATA[4]} {wallypipelinedsoc/hart/ebu/HWDATA[5]} {wallypipelinedsoc/hart/ebu/HWDATA[6]} {wallypipelinedsoc/hart/ebu/HWDATA[7]} {wallypipelinedsoc/hart/ebu/HWDATA[8]} {wallypipelinedsoc/hart/ebu/HWDATA[9]} {wallypipelinedsoc/hart/ebu/HWDATA[10]} {wallypipelinedsoc/hart/ebu/HWDATA[11]} {wallypipelinedsoc/hart/ebu/HWDATA[12]} {wallypipelinedsoc/hart/ebu/HWDATA[13]} {wallypipelinedsoc/hart/ebu/HWDATA[14]} {wallypipelinedsoc/hart/ebu/HWDATA[15]} {wallypipelinedsoc/hart/ebu/HWDATA[16]} {wallypipelinedsoc/hart/ebu/HWDATA[17]} {wallypipelinedsoc/hart/ebu/HWDATA[18]} {wallypipelinedsoc/hart/ebu/HWDATA[19]} {wallypipelinedsoc/hart/ebu/HWDATA[20]} {wallypipelinedsoc/hart/ebu/HWDATA[21]} {wallypipelinedsoc/hart/ebu/HWDATA[22]} {wallypipelinedsoc/hart/ebu/HWDATA[23]} {wallypipelinedsoc/hart/ebu/HWDATA[24]} {wallypipelinedsoc/hart/ebu/HWDATA[25]} {wallypipelinedsoc/hart/ebu/HWDATA[26]} {wallypipelinedsoc/hart/ebu/HWDATA[27]} {wallypipelinedsoc/hart/ebu/HWDATA[28]} {wallypipelinedsoc/hart/ebu/HWDATA[29]} {wallypipelinedsoc/hart/ebu/HWDATA[30]} {wallypipelinedsoc/hart/ebu/HWDATA[31]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 32 [get_debug_ports u_ila_0/probe107]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe107]
+connect_debug_port u_ila_0/probe107 [get_nets [list {wallypipelinedsoc/hart/ebu/HADDR[0]} {wallypipelinedsoc/hart/ebu/HADDR[1]} {wallypipelinedsoc/hart/ebu/HADDR[2]} {wallypipelinedsoc/hart/ebu/HADDR[3]} {wallypipelinedsoc/hart/ebu/HADDR[4]} {wallypipelinedsoc/hart/ebu/HADDR[5]} {wallypipelinedsoc/hart/ebu/HADDR[6]} {wallypipelinedsoc/hart/ebu/HADDR[7]} {wallypipelinedsoc/hart/ebu/HADDR[8]} {wallypipelinedsoc/hart/ebu/HADDR[9]} {wallypipelinedsoc/hart/ebu/HADDR[10]} {wallypipelinedsoc/hart/ebu/HADDR[11]} {wallypipelinedsoc/hart/ebu/HADDR[12]} {wallypipelinedsoc/hart/ebu/HADDR[13]} {wallypipelinedsoc/hart/ebu/HADDR[14]} {wallypipelinedsoc/hart/ebu/HADDR[15]} {wallypipelinedsoc/hart/ebu/HADDR[16]} {wallypipelinedsoc/hart/ebu/HADDR[17]} {wallypipelinedsoc/hart/ebu/HADDR[18]} {wallypipelinedsoc/hart/ebu/HADDR[19]} {wallypipelinedsoc/hart/ebu/HADDR[20]} {wallypipelinedsoc/hart/ebu/HADDR[21]} {wallypipelinedsoc/hart/ebu/HADDR[22]} {wallypipelinedsoc/hart/ebu/HADDR[23]} {wallypipelinedsoc/hart/ebu/HADDR[24]} {wallypipelinedsoc/hart/ebu/HADDR[25]} {wallypipelinedsoc/hart/ebu/HADDR[26]} {wallypipelinedsoc/hart/ebu/HADDR[27]} {wallypipelinedsoc/hart/ebu/HADDR[28]} {wallypipelinedsoc/hart/ebu/HADDR[29]} {wallypipelinedsoc/hart/ebu/HADDR[30]} {wallypipelinedsoc/hart/ebu/HADDR[31]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe108]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe108]
+connect_debug_port u_ila_0/probe108 [get_nets [list {wallypipelinedsoc/hart/ebu/HREADY}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe109]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe109]
+connect_debug_port u_ila_0/probe109 [get_nets [list {wallypipelinedsoc/hart/ebu/HRESP}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe110]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe110]
+connect_debug_port u_ila_0/probe110 [get_nets [list {wallypipelinedsoc/hart/ebu/HWRITE}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe111]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe111]
+connect_debug_port u_ila_0/probe111 [get_nets [list {wallypipelinedsoc/hart/ebu/HSIZE[0]} {wallypipelinedsoc/hart/ebu/HSIZE[1]} {wallypipelinedsoc/hart/ebu/HSIZE[2]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 3 [get_debug_ports u_ila_0/probe112]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe112]
+connect_debug_port u_ila_0/probe112 [get_nets [list {wallypipelinedsoc/hart/ebu/HBURST[0]} {wallypipelinedsoc/hart/ebu/HBURST[1]} {wallypipelinedsoc/hart/ebu/HBURST[2]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe113]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe113]
+connect_debug_port u_ila_0/probe113 [get_nets [list {wallypipelinedsoc/hart/ebu/HPROT[0]} {wallypipelinedsoc/hart/ebu/HPROT[1]} {wallypipelinedsoc/hart/ebu/HPROT[2]} {wallypipelinedsoc/hart/ebu/HPROT[3]}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe114]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe114]
+connect_debug_port u_ila_0/probe114 [get_nets [list {wallypipelinedsoc/hart/ebu/HMASTLOCK}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe115]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe115]
+connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/hart/priv/InterruptM}]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe116]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
+connect_debug_port u_ila_0/probe116 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/ITLBMissF]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe117]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
+connect_debug_port u_ila_0/probe117 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/DTLBMissM]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe118]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
+connect_debug_port u_ila_0/probe118 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/ITLBWriteF]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe119]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
+connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/DTLBWriteM]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 11 [get_debug_ports u_ila_0/probe120]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
+connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/hart/lsu/hptw/WalkerState[0]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[1]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[2]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[3]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[4]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[5]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[6]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[7]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[8]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[9]} {wallypipelinedsoc/hart/lsu/hptw/WalkerState[10]}]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 56 [get_debug_ports u_ila_0/probe121]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe121]
+connect_debug_port u_ila_0/probe121 [get_nets [list {wallypipelinedsoc/hart/lsu/MemPAdrM[0]} {wallypipelinedsoc/hart/lsu/MemPAdrM[1]} {wallypipelinedsoc/hart/lsu/MemPAdrM[2]} {wallypipelinedsoc/hart/lsu/MemPAdrM[3]} {wallypipelinedsoc/hart/lsu/MemPAdrM[4]} {wallypipelinedsoc/hart/lsu/MemPAdrM[5]} {wallypipelinedsoc/hart/lsu/MemPAdrM[6]} {wallypipelinedsoc/hart/lsu/MemPAdrM[7]} {wallypipelinedsoc/hart/lsu/MemPAdrM[8]} {wallypipelinedsoc/hart/lsu/MemPAdrM[9]} {wallypipelinedsoc/hart/lsu/MemPAdrM[10]} {wallypipelinedsoc/hart/lsu/MemPAdrM[11]} {wallypipelinedsoc/hart/lsu/MemPAdrM[12]} {wallypipelinedsoc/hart/lsu/MemPAdrM[13]} {wallypipelinedsoc/hart/lsu/MemPAdrM[14]} {wallypipelinedsoc/hart/lsu/MemPAdrM[15]} {wallypipelinedsoc/hart/lsu/MemPAdrM[16]} {wallypipelinedsoc/hart/lsu/MemPAdrM[17]} {wallypipelinedsoc/hart/lsu/MemPAdrM[18]} {wallypipelinedsoc/hart/lsu/MemPAdrM[19]} {wallypipelinedsoc/hart/lsu/MemPAdrM[20]} {wallypipelinedsoc/hart/lsu/MemPAdrM[21]} {wallypipelinedsoc/hart/lsu/MemPAdrM[22]} {wallypipelinedsoc/hart/lsu/MemPAdrM[23]} {wallypipelinedsoc/hart/lsu/MemPAdrM[24]} {wallypipelinedsoc/hart/lsu/MemPAdrM[25]} {wallypipelinedsoc/hart/lsu/MemPAdrM[26]} {wallypipelinedsoc/hart/lsu/MemPAdrM[27]} {wallypipelinedsoc/hart/lsu/MemPAdrM[28]} {wallypipelinedsoc/hart/lsu/MemPAdrM[29]} {wallypipelinedsoc/hart/lsu/MemPAdrM[30]} {wallypipelinedsoc/hart/lsu/MemPAdrM[31]} {wallypipelinedsoc/hart/lsu/MemPAdrM[32]} {wallypipelinedsoc/hart/lsu/MemPAdrM[33]} {wallypipelinedsoc/hart/lsu/MemPAdrM[34]} {wallypipelinedsoc/hart/lsu/MemPAdrM[35]} {wallypipelinedsoc/hart/lsu/MemPAdrM[36]} {wallypipelinedsoc/hart/lsu/MemPAdrM[37]} {wallypipelinedsoc/hart/lsu/MemPAdrM[38]} {wallypipelinedsoc/hart/lsu/MemPAdrM[39]} {wallypipelinedsoc/hart/lsu/MemPAdrM[40]} {wallypipelinedsoc/hart/lsu/MemPAdrM[41]} {wallypipelinedsoc/hart/lsu/MemPAdrM[42]} {wallypipelinedsoc/hart/lsu/MemPAdrM[43]} {wallypipelinedsoc/hart/lsu/MemPAdrM[44]} {wallypipelinedsoc/hart/lsu/MemPAdrM[45]} {wallypipelinedsoc/hart/lsu/MemPAdrM[46]} {wallypipelinedsoc/hart/lsu/MemPAdrM[47]} {wallypipelinedsoc/hart/lsu/MemPAdrM[48]} {wallypipelinedsoc/hart/lsu/MemPAdrM[49]} {wallypipelinedsoc/hart/lsu/MemPAdrM[50]} {wallypipelinedsoc/hart/lsu/MemPAdrM[51]} {wallypipelinedsoc/hart/lsu/MemPAdrM[52]} {wallypipelinedsoc/hart/lsu/MemPAdrM[53]} {wallypipelinedsoc/hart/lsu/MemPAdrM[54]} {wallypipelinedsoc/hart/lsu/MemPAdrM[55]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 56 [get_debug_ports u_ila_0/probe122]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe122]
+connect_debug_port u_ila_0/probe122 [get_nets [list {wallypipelinedsoc/hart/ifu/PCPFmmu[0]} {wallypipelinedsoc/hart/ifu/PCPFmmu[1]} {wallypipelinedsoc/hart/ifu/PCPFmmu[2]} {wallypipelinedsoc/hart/ifu/PCPFmmu[3]} {wallypipelinedsoc/hart/ifu/PCPFmmu[4]} {wallypipelinedsoc/hart/ifu/PCPFmmu[5]} {wallypipelinedsoc/hart/ifu/PCPFmmu[6]} {wallypipelinedsoc/hart/ifu/PCPFmmu[7]} {wallypipelinedsoc/hart/ifu/PCPFmmu[8]} {wallypipelinedsoc/hart/ifu/PCPFmmu[9]} {wallypipelinedsoc/hart/ifu/PCPFmmu[10]} {wallypipelinedsoc/hart/ifu/PCPFmmu[11]} {wallypipelinedsoc/hart/ifu/PCPFmmu[12]} {wallypipelinedsoc/hart/ifu/PCPFmmu[13]} {wallypipelinedsoc/hart/ifu/PCPFmmu[14]} {wallypipelinedsoc/hart/ifu/PCPFmmu[15]} {wallypipelinedsoc/hart/ifu/PCPFmmu[16]} {wallypipelinedsoc/hart/ifu/PCPFmmu[17]} {wallypipelinedsoc/hart/ifu/PCPFmmu[18]} {wallypipelinedsoc/hart/ifu/PCPFmmu[19]} {wallypipelinedsoc/hart/ifu/PCPFmmu[20]} {wallypipelinedsoc/hart/ifu/PCPFmmu[21]} {wallypipelinedsoc/hart/ifu/PCPFmmu[22]} {wallypipelinedsoc/hart/ifu/PCPFmmu[23]} {wallypipelinedsoc/hart/ifu/PCPFmmu[24]} {wallypipelinedsoc/hart/ifu/PCPFmmu[25]} {wallypipelinedsoc/hart/ifu/PCPFmmu[26]} {wallypipelinedsoc/hart/ifu/PCPFmmu[27]} {wallypipelinedsoc/hart/ifu/PCPFmmu[28]} {wallypipelinedsoc/hart/ifu/PCPFmmu[29]} {wallypipelinedsoc/hart/ifu/PCPFmmu[30]} {wallypipelinedsoc/hart/ifu/PCPFmmu[31]} {wallypipelinedsoc/hart/ifu/PCPFmmu[32]} {wallypipelinedsoc/hart/ifu/PCPFmmu[33]} {wallypipelinedsoc/hart/ifu/PCPFmmu[34]} {wallypipelinedsoc/hart/ifu/PCPFmmu[35]} {wallypipelinedsoc/hart/ifu/PCPFmmu[36]} {wallypipelinedsoc/hart/ifu/PCPFmmu[37]} {wallypipelinedsoc/hart/ifu/PCPFmmu[38]} {wallypipelinedsoc/hart/ifu/PCPFmmu[39]} {wallypipelinedsoc/hart/ifu/PCPFmmu[40]} {wallypipelinedsoc/hart/ifu/PCPFmmu[41]} {wallypipelinedsoc/hart/ifu/PCPFmmu[42]} {wallypipelinedsoc/hart/ifu/PCPFmmu[43]} {wallypipelinedsoc/hart/ifu/PCPFmmu[44]} {wallypipelinedsoc/hart/ifu/PCPFmmu[45]} {wallypipelinedsoc/hart/ifu/PCPFmmu[46]} {wallypipelinedsoc/hart/ifu/PCPFmmu[47]} {wallypipelinedsoc/hart/ifu/PCPFmmu[48]} {wallypipelinedsoc/hart/ifu/PCPFmmu[49]} {wallypipelinedsoc/hart/ifu/PCPFmmu[50]} {wallypipelinedsoc/hart/ifu/PCPFmmu[51]} {wallypipelinedsoc/hart/ifu/PCPFmmu[52]} {wallypipelinedsoc/hart/ifu/PCPFmmu[53]} {wallypipelinedsoc/hart/ifu/PCPFmmu[54]} {wallypipelinedsoc/hart/ifu/PCPFmmu[55]} ]]
+
+
diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl
index 26b3babf..af1c105d 100644
--- a/fpga/generator/wally.tcl
+++ b/fpga/generator/wally.tcl
@@ -69,9 +69,9 @@ open_run impl_1
 exec mkdir -p sim/
 exec rm -rf sim/*
 
-write_verilog -force -mode funcsim sim/funcsim.v
-write_verilog -force -mode timesim sim/timesim.v
-write_sdf     -force sim/timesim.sdf
+write_verilog -force -mode funcsim sim/imp-funcsim.v
+write_verilog -force -mode timesim sim/imp-timesim.v
+write_sdf     -force sim/imp-timesim.sdf
 
 # reports
 check_timing                                                              -file reports/imp_check_timing.rpt
diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index 13a095c4..8ad276ab 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -35,39 +35,39 @@ package ahbliteState;
 endpackage
 
 module ahblite (
-  input logic 		     clk, reset,
+  input logic 				 clk, reset,
   // Load control
-  input logic 		     UnsignedLoadM,
-  input logic [1:0] 	     AtomicMaskedM,
+  input logic 				 UnsignedLoadM,
+  input logic [1:0] 		 AtomicMaskedM,
   // Signals from Instruction Cache
   input logic [`PA_BITS-1:0] InstrPAdrF, // *** rename these to match block diagram
-  input logic 		     InstrReadF,
-  output logic [`XLEN-1:0]   InstrRData,
-  output logic 		     InstrAckF,
+  input logic 				 InstrReadF,
+  output logic [`XLEN-1:0] 	 InstrRData,
+  output logic 				 InstrAckF,
   // Signals from Data Cache
   input logic [`PA_BITS-1:0] DCtoAHBPAdrM,
-  input logic 		     DCtoAHBReadM, 
-  input logic 		     DCtoAHBWriteM,
-  input logic [`XLEN-1:0]    DCtoAHBWriteData,
-  output logic [`XLEN-1:0]   DCfromAHBReadData,
-  input logic [1:0] 	     MemSizeM,     // *** remove
-  output logic 		     DCfromAHBAck,
+  input logic 				 DCtoAHBReadM, 
+  input logic 				 DCtoAHBWriteM,
+  input logic [`XLEN-1:0] 	 DCtoAHBWriteData,
+  output logic [`XLEN-1:0] 	 DCfromAHBReadData,
+  input logic [1:0] 		 MemSizeM, // *** remove
+  output logic 				 DCfromAHBAck,
   // AHB-Lite external signals
-  input logic [`AHBW-1:0]    HRDATA,
-  input logic 		     HREADY, HRESP,
-  output logic 		     HCLK, HRESETn,
-  output logic [31:0] 	     HADDR, 
-  output logic [`AHBW-1:0]   HWDATA,
-  output logic 		     HWRITE, 
-  output logic [2:0] 	     HSIZE,
-  output logic [2:0] 	     HBURST,
-  output logic [3:0] 	     HPROT,
-  output logic [1:0] 	     HTRANS,
-  output logic 		     HMASTLOCK,
+  (* mark_debug = "true" *) input logic [`AHBW-1:0] HRDATA,
+  (* mark_debug = "true" *) input logic HREADY, HRESP,
+  (* mark_debug = "true" *) output logic HCLK, HRESETn,
+  (* mark_debug = "true" *) output logic [31:0] HADDR, 
+  (* mark_debug = "true" *) output logic [`AHBW-1:0] HWDATA,
+  (* mark_debug = "true" *) output logic HWRITE, 
+  (* mark_debug = "true" *) output logic [2:0] HSIZE,
+  (* mark_debug = "true" *) output logic [2:0] HBURST,
+  (* mark_debug = "true" *) output logic [3:0] HPROT,
+  (* mark_debug = "true" *) output logic [1:0] HTRANS,
+  (* mark_debug = "true" *) output logic HMASTLOCK,
   // Delayed signals for writes
-  output logic [2:0] 	     HADDRD,
-  output logic [3:0] 	     HSIZED,
-  output logic 		     HWRITED
+  (* mark_debug = "true" *) output logic [2:0] HADDRD,
+  (* mark_debug = "true" *) output logic [3:0] HSIZED,
+  (* mark_debug = "true" *) output logic HWRITED
 );
 
   logic GrantData;
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 09322609..4e84acee 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -33,7 +33,7 @@ module ifu (
   // Fetch
   input logic [`XLEN-1:0]     InstrInF,
   input logic 		      InstrAckF,
-  output logic [`XLEN-1:0]    PCF, 
+  (* mark_debug = "true" *) output logic [`XLEN-1:0]    PCF, 
   output logic [`PA_BITS-1:0] InstrPAdrF,
   output logic 		      InstrReadF,
   output logic 		      ICacheStallF,
@@ -101,7 +101,7 @@ module ifu (
 
   logic                        BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
   
-  logic [`PA_BITS-1:0]         PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
+(* mark_debug = "true" *)  logic [`PA_BITS-1:0]         PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
   logic [`XLEN+1:0]            PCFExt;
 
   generate
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 791e4d4a..3f25a689 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -96,7 +96,7 @@ module lsu
   logic 	         DataMisalignedM;
 
   
-  logic [`PA_BITS-1:0] 	       MemPAdrM;  // from mmu to dcache
+  (* mark_debug = "true" *) logic [`PA_BITS-1:0] 	       MemPAdrM;  // from mmu to dcache
  
   logic 		       DTLBMissM;
   logic 		       DTLBWriteM;
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index 5ca5032e..95c8989d 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -35,7 +35,7 @@ module hptw
    input logic 		       clk, reset,
    input logic [`XLEN-1:0]     SATP_REGW, // includes SATP.MODE to determine number of levels in page table
    input logic [`XLEN-1:0]     PCF, MemAdrM, // addresses to translate
-   input logic 		       ITLBMissF, DTLBMissM, // TLB Miss
+   (* mark_debug = "true" *) input logic 		       ITLBMissF, DTLBMissM, // TLB Miss
    input logic [1:0] 	       MemRWM, // 10 = read, 01 = write
    input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU
    input logic 		       HPTWStall, // stall from LSU
@@ -43,7 +43,7 @@ module hptw
    input logic 		       AnyCPUReqM,
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0] 	       PageType, // page type to TLBs
-   output logic 	       ITLBWriteF, DTLBWriteM, // write TLB with new entry
+   (* mark_debug = "true" *) output logic 	       ITLBWriteF, DTLBWriteM, // write TLB with new entry
    output logic 	       SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU
    output logic [`PA_BITS-1:0] TranslationPAdr,
    output logic 	       HPTWRead, // HPTW requesting to read memory
@@ -72,7 +72,7 @@ module hptw
       logic [`SVMODE_BITS-1:0]	    SvMode;
       logic [`XLEN-1:0] 	    TranslationVAdr;
       
-      statetype WalkerState, NextWalkerState, InitialWalkerState;
+	  (* mark_debug = "true" *)      statetype WalkerState, NextWalkerState, InitialWalkerState;
 
 	  // Extract bits from CSRs and inputs
       assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv
index f1e3c966..34eaf276 100644
--- a/wally-pipelined/src/privileged/csrc.sv
+++ b/wally-pipelined/src/privileged/csrc.sv
@@ -92,7 +92,7 @@ module csrc #(parameter
 
   generate
     if (`ZICOUNTERS_SUPPORTED) begin
-      logic [63:0] CYCLE_REGW, INSTRET_REGW;
+     (* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
      logic [63:0] CYCLEPlusM, INSTRETPlusM;
        logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
       logic        WriteCYCLEM, WriteINSTRETM;
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index c5bc8a45..94a96fb0 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -98,7 +98,7 @@ module privileged (
   logic IllegalInstrFaultM, TrappedSRETM;
 
   logic MTrapM, STrapM, UTrapM;
-  logic InterruptM; 
+  (* mark_debug = "true" *)  logic InterruptM; 
 
   logic       STATUS_SPP, STATUS_TSR, STATUS_TW; 
   logic       STATUS_MIE, STATUS_SIE;

From 0f319b45c16f1652c9f6d53d8c9f67416ce7f277 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Fri, 17 Dec 2021 17:45:26 -0800
Subject: [PATCH 46/95] Do File cleanups

---
 examples/asm/ch5/Makefile                   |  10 +++
 examples/asm/ch5/ch5                        | Bin 0 -> 1080 bytes
 examples/asm/ch5/ch5.S                      |  16 +++++
 examples/asm/ch5/ch5.debug                  |  38 +++++++++++
 examples/asm/ch5/example                    | Bin 0 -> 6072 bytes
 examples/asm/example/Makefile               |   2 +
 examples/asm/example/example                | Bin 0 -> 6072 bytes
 examples/asm/example/example.S              |  67 ++++++++++++++++++++
 examples/asm/test                           | Bin 0 -> 6296 bytes
 examples/asm/test.S                         |  22 +++++++
 wally-pipelined/regression/fpga-wave.do     |  20 ++----
 wally-pipelined/regression/linux-wave.do    |   8 +--
 wally-pipelined/regression/wave-all.do      |  28 ++------
 wally-pipelined/regression/wave-coremark.do |   8 +--
 wally-pipelined/regression/wave.do          |  22 ++-----
 15 files changed, 183 insertions(+), 58 deletions(-)
 create mode 100644 examples/asm/ch5/Makefile
 create mode 100755 examples/asm/ch5/ch5
 create mode 100644 examples/asm/ch5/ch5.S
 create mode 100644 examples/asm/ch5/ch5.debug
 create mode 100755 examples/asm/ch5/example
 create mode 100644 examples/asm/example/Makefile
 create mode 100755 examples/asm/example/example
 create mode 100644 examples/asm/example/example.S
 create mode 100755 examples/asm/test
 create mode 100644 examples/asm/test.S

diff --git a/examples/asm/ch5/Makefile b/examples/asm/ch5/Makefile
new file mode 100644
index 00000000..6f1cd89d
--- /dev/null
+++ b/examples/asm/ch5/Makefile
@@ -0,0 +1,10 @@
+ch5.debug: ch5
+	riscv64-unknown-elf-objdump -D ch5 > ch5.debug
+
+ch5: ch5.S Makefile
+	riscv64-unknown-elf-gcc -nodefaultlibs -nostartfiles -o ch5 ch5.S
+# -ffreestanding 
+# -nostdlib 
+
+clean: 
+	rm -f ch5 ch5.debug
\ No newline at end of file
diff --git a/examples/asm/ch5/ch5 b/examples/asm/ch5/ch5
new file mode 100755
index 0000000000000000000000000000000000000000..3684ea3833c315acc061fcbd46daf2616e3a457e
GIT binary patch
literal 1080
zcmb_aO-sW-5S{c3y+sfyc&XTf7gK3Pya-8Yl|m^>_26mAml|x7kgTPiRP^AX2Y-%7
z|C0CvbT*mAHX6LRhxcaR%)Xudxa;;03yK1A6yO8IY?>f|PKnn-8kCWA*vG666(}cF
zLi--lE9Ds_B!ij?k2M`O>ngM!RIs0F5TI-{5h5?PC!lO$SdJ!pyIwQgVPgTNfC~YR
z02?9o%EKadC(kioQv^E9oG7|2!TaZ&l!Pk@Dlnt_koh&zpELS8>MHuos`4Jv72Ao9
zKI)=AAU)gX0qHN9`d*IDS&r`H=+`;^(BR{+VcX~J6W{J@0XTv0!YBwrVC-@fSmua@
zf#-8Ks-rUO7^enncaM4l#&F&q4q125Nn$IGS<KCdqrO<?Iwm)PxjuHM#kXT_TF5*~
z`ASCIopR8U522ZyN1k=V-54AHhauicyhMe(<o!=+zDg`9`(rjRQ3MEOUb6h>Eh!K$
vzIwWM)>D+eQT;J3DB)c6xI}uDco`Y@|1nfD%{G?ZU;OLe*5A|mzxw|IBGX>;

literal 0
HcmV?d00001

diff --git a/examples/asm/ch5/ch5.S b/examples/asm/ch5/ch5.S
new file mode 100644
index 00000000..cfba5645
--- /dev/null
+++ b/examples/asm/ch5/ch5.S
@@ -0,0 +1,16 @@
+# ch5.s
+# David_Harris@hmc.edu 14 December 2021
+
+.section .text.init
+
+.globl _start
+_start:
+    lw x1, 4(x0)
+    sw x1, 8(x0)
+    add x2, x1, x1
+    beq x1, x2, done
+loop:
+    jal x0, loop
+done:
+
+.end
diff --git a/examples/asm/ch5/ch5.debug b/examples/asm/ch5/ch5.debug
new file mode 100644
index 00000000..28027a62
--- /dev/null
+++ b/examples/asm/ch5/ch5.debug
@@ -0,0 +1,38 @@
+
+ch5:     file format elf64-littleriscv
+
+
+Disassembly of section .text:
+
+0000000000010078 <_start>:
+   10078:	00402083          	lw	ra,4(zero) # 4 <_start-0x10074>
+   1007c:	00102423          	sw	ra,8(zero) # 8 <_start-0x10070>
+   10080:	00108133          	add	sp,ra,ra
+   10084:	00208463          	beq	ra,sp,1008c <done>
+
+0000000000010088 <loop>:
+   10088:	0000006f          	j	10088 <loop>
+
+Disassembly of section .riscv.attributes:
+
+0000000000000000 <.riscv.attributes>:
+   0:	3241                	addiw	tp,tp,-16
+   2:	0000                	unimp
+   4:	7200                	ld	s0,32(a2)
+   6:	7369                	lui	t1,0xffffa
+   8:	01007663          	bgeu	zero,a6,14 <_start-0x10064>
+   c:	0028                	addi	a0,sp,8
+   e:	0000                	unimp
+  10:	7205                	lui	tp,0xfffe1
+  12:	3676                	fld	fa2,376(sp)
+  14:	6934                	ld	a3,80(a0)
+  16:	7032                	0x7032
+  18:	5f30                	lw	a2,120(a4)
+  1a:	326d                	addiw	tp,tp,-5
+  1c:	3070                	fld	fa2,224(s0)
+  1e:	615f 7032 5f30      	0x5f307032615f
+  24:	3266                	fld	ft4,120(sp)
+  26:	3070                	fld	fa2,224(s0)
+  28:	645f 7032 5f30      	0x5f307032645f
+  2e:	30703263          	0x30703263
+	...
diff --git a/examples/asm/ch5/example b/examples/asm/ch5/example
new file mode 100755
index 0000000000000000000000000000000000000000..a9b74047949c0c1022323eb3f86a6a5e588b2095
GIT binary patch
literal 6072
zcmeHLZ%iD=6@UBZ4qxpiU`TOlHwMlHm(mL)wBRN|$Dadir6h{$RF0Y~%ie;|x#P}z
zi({f%xj&o<q_Jb2#Sy8I5J(Pkqsmp1Uh1l{U1Zrx8>t`aHd53G8*2Q)61IXJCynjC
z*`0x7xl=#%LludUX5P$ie(%kjH?y;|`-<nuR-WU4B_2Kl(mG?50B+iGpvbJ)P`IHU
zcr3pO>kJmbmJ+jN%1Y7fVG{DqHtDrvuA==_MJAugU*ws*_o!rgNo)_DZ&V9yp4z^5
zVv$rSKr$NrpfJJRDm)bZ!f`n2nFn`%F*;RfvsFHL&a8d6d>*E^&I7FBJypQ9&O?dq
z=%jF-yY;|aV?o(;!+?F3*pB|$gSO8#rEvH;%!#(~PG{uCE#BM6#Uil?;T%OyG7-H+
zc*O!h5AtG>LfaV6jWrfTJ!RAO*~)==h^!ahk1jkOI64(el_kjdTtV5@9n&7K$Cu0#
zn+qL|=0_c0xb4@<XA5_4b1Q2dP$-Jc(Uwh}39(d+rDit0c{hXILfE;Pmphxh<6hop
zlVg!5nkxsDeN%k$rO)B)%pWf$_uKD1F??!d-OReV#=M!pKkgP>jz!+JPq~NfDIQ>C
zq$hG5oOx-Ou&2R^dBTPg^Mr^J^MrsB^8}9)^8|+y^8}#8jIp_S^Zw*W0xrIu9I<gm
z$zObZcRD#z0p=KoVsnx5FGnJ0i@$TEVPt0C)a|#@&+mKYx^ODGu;ccjSz+7o=JDzB
zuR0c<z4qMI7iPPrl{F5&^0nW*me_G;cYMnbY#dm)r*w#LSp4vqa%e3dPY;wRv6qB{
zwU>%!Hq_ob-f8z<)|>jr`}vnI?`?W<{6*d`V?5#&Lon*SQ>P3Jiq7{$kUxo6IBNbd
zG7Li15ZpWxtr(i;Qv$N$b;FyLqCswEu;SkzebO-GOUEm=*Tml+$S15f=blUOsY|Dw
z=u6*e7uIj2$*P{~@py6VT9Si<Ezu+8v-WGrzty>;7cLby9NW}+r${b}rT+Dmxk6-p
zP9&nOTr1~sj0x%JLcDHp^KYj{+YYuXO;_!<bA=n~pkdTme<43UnO9?Lee7FT;N7bi
zz&Tl5<E;O<WT;hvi+s{v0f+6jiqZ4GOZ{?&^N`({SK@s9^M{^49Y5Yy!+CZcW*p~<
z^VKFV7CE>p7KwVeR`j4P+Lm1NS6di&u+nS;vVY5_EAd%)OpLg32Lqht#&8$kjA50e
zlk{Aurf0@o+BSOuA`hC+arL)NIZY+&|GG<aRsi=s`q8gz*9Wd#`_u+&zwVP-^?x-2
zs}Wd@z-k2k?-6LH_h9A-YqvEw|F~ppTgR^NmDE(b9&uGeV=ZztUs%}>TqRb;e4Doa
zN4363Le)}$6f!BgN#P}hf(5ghT?+UvXYcn+hJd$yb}wI!3s7zGm-GuDf;%g212&)K
zcI@!RM)qc1>JcChCbQyemPi>j0UQ}Evr4RraO0k}qW}RuW4`pW1UBd36MZgA97yDe
z9qT>FZSa@;XR~|Kz*okH+`xz(cCW&wkzT=)!#JFzabQdMs(}koZ;A8Uh-aH`+OWn!
zN5;1vfj-N@Kbr&p5OEHc*0CMGhe-N6=4|8sGY5Vp2R@qv$1k_6_P@-5=UPV|7b4p_
zqM5Ar^NocQSM1wTid*-2t$_<G_P>YX*5_q+4&0vuk0G9q`?-CSK_G4$=@>TG<IJ{*
zCQiPsN&1z+U-^8!gLnaNhf&M(^?QQjmpOYL*^~Ac#EJc0x_|bX=HXL{w+L9lL=GjA
zu2Vcl0*>iVMhQ@k-<rhE8O$U#P@JQ9jM~{x@dpsk$NfKT@w1fT*7M;9)XvA$&lA*6
zt-<GDhh_h7qx=JO+;33+8FY`tVT_K;;@~#yEbV_vho=nOzT&(h%aqOkpV4ujrv5xc
z4LwWo+ti;bHh?54vfnSsx_ZE;yA;sW9$#2jHL2Uz>jOp8!+KwLH+D#pHz@V^gI%&;
z^6Eh?EXjQbKnVsyepOe!uA1x&!;U0tn%pm`y}H&9-I^RwC2wCK&=0|`y{e+)TSt;I
zU<rrTm+3sL2SN`kiho<b*8P+#2w~OVE%}4N5cmS2K21gc%!=fdbs300LSzbt=Zmuo
z_lG4qQB~7=gGO)bGmSs-NS=-sNg{rr(&E_O<v>`MH65X4{t-?{Q&(Ua0MlDeV<-)3
zDCq0Oz;8iwhHof$wlw~<QEKwEZSOFA^M-@c9=X@+SAi`Bopwmqkni_(DH+Z&WNAu>
z7|Ts!5YmE57=gtVXCPutJ9jPyq$?bjOjiSHAgt;TkbS*ih7_sGT~v+u8!-lOh5G}#
z+=WutOu2{EaJ%W?Qumn44z8tOfh)sZmtoEoHU)YDF5Gbe+(_Uu?kFx<*EL^PpRSTO
z-T$68q6u<>uyc;xTTW8bFXMl?%!H5CvQ&yKqR(jTe#8Dp(%+JcI@b30vFE-FeRi%_
zQzE-hFazxTV6qN7?$6L??-4iEXS`hc&DfFYKf718Q+@Vcw(7I?c8fkc@86(5Gd3_H
zl~#YAMx0<Qe(W5cr26&$MSmCe6aU$LhS8b+dInHQxFj+80@iWtkO5{Cr|9@U%)m&M
z=`onJt$Tv>U8njV(4X3*xfL^;KZ^^wX|lOvbumqnizTL?TZ~)BC$wz(BK^;9otRbs
EKb_svjsO4v

literal 0
HcmV?d00001

diff --git a/examples/asm/example/Makefile b/examples/asm/example/Makefile
new file mode 100644
index 00000000..081f342c
--- /dev/null
+++ b/examples/asm/example/Makefile
@@ -0,0 +1,2 @@
+example: example.S
+	riscv64-unknown-elf-gcc -o example example.S
diff --git a/examples/asm/example/example b/examples/asm/example/example
new file mode 100755
index 0000000000000000000000000000000000000000..a9b74047949c0c1022323eb3f86a6a5e588b2095
GIT binary patch
literal 6072
zcmeHLZ%iD=6@UBZ4qxpiU`TOlHwMlHm(mL)wBRN|$Dadir6h{$RF0Y~%ie;|x#P}z
zi({f%xj&o<q_Jb2#Sy8I5J(Pkqsmp1Uh1l{U1Zrx8>t`aHd53G8*2Q)61IXJCynjC
z*`0x7xl=#%LludUX5P$ie(%kjH?y;|`-<nuR-WU4B_2Kl(mG?50B+iGpvbJ)P`IHU
zcr3pO>kJmbmJ+jN%1Y7fVG{DqHtDrvuA==_MJAugU*ws*_o!rgNo)_DZ&V9yp4z^5
zVv$rSKr$NrpfJJRDm)bZ!f`n2nFn`%F*;RfvsFHL&a8d6d>*E^&I7FBJypQ9&O?dq
z=%jF-yY;|aV?o(;!+?F3*pB|$gSO8#rEvH;%!#(~PG{uCE#BM6#Uil?;T%OyG7-H+
zc*O!h5AtG>LfaV6jWrfTJ!RAO*~)==h^!ahk1jkOI64(el_kjdTtV5@9n&7K$Cu0#
zn+qL|=0_c0xb4@<XA5_4b1Q2dP$-Jc(Uwh}39(d+rDit0c{hXILfE;Pmphxh<6hop
zlVg!5nkxsDeN%k$rO)B)%pWf$_uKD1F??!d-OReV#=M!pKkgP>jz!+JPq~NfDIQ>C
zq$hG5oOx-Ou&2R^dBTPg^Mr^J^MrsB^8}9)^8|+y^8}#8jIp_S^Zw*W0xrIu9I<gm
z$zObZcRD#z0p=KoVsnx5FGnJ0i@$TEVPt0C)a|#@&+mKYx^ODGu;ccjSz+7o=JDzB
zuR0c<z4qMI7iPPrl{F5&^0nW*me_G;cYMnbY#dm)r*w#LSp4vqa%e3dPY;wRv6qB{
zwU>%!Hq_ob-f8z<)|>jr`}vnI?`?W<{6*d`V?5#&Lon*SQ>P3Jiq7{$kUxo6IBNbd
zG7Li15ZpWxtr(i;Qv$N$b;FyLqCswEu;SkzebO-GOUEm=*Tml+$S15f=blUOsY|Dw
z=u6*e7uIj2$*P{~@py6VT9Si<Ezu+8v-WGrzty>;7cLby9NW}+r${b}rT+Dmxk6-p
zP9&nOTr1~sj0x%JLcDHp^KYj{+YYuXO;_!<bA=n~pkdTme<43UnO9?Lee7FT;N7bi
zz&Tl5<E;O<WT;hvi+s{v0f+6jiqZ4GOZ{?&^N`({SK@s9^M{^49Y5Yy!+CZcW*p~<
z^VKFV7CE>p7KwVeR`j4P+Lm1NS6di&u+nS;vVY5_EAd%)OpLg32Lqht#&8$kjA50e
zlk{Aurf0@o+BSOuA`hC+arL)NIZY+&|GG<aRsi=s`q8gz*9Wd#`_u+&zwVP-^?x-2
zs}Wd@z-k2k?-6LH_h9A-YqvEw|F~ppTgR^NmDE(b9&uGeV=ZztUs%}>TqRb;e4Doa
zN4363Le)}$6f!BgN#P}hf(5ghT?+UvXYcn+hJd$yb}wI!3s7zGm-GuDf;%g212&)K
zcI@!RM)qc1>JcChCbQyemPi>j0UQ}Evr4RraO0k}qW}RuW4`pW1UBd36MZgA97yDe
z9qT>FZSa@;XR~|Kz*okH+`xz(cCW&wkzT=)!#JFzabQdMs(}koZ;A8Uh-aH`+OWn!
zN5;1vfj-N@Kbr&p5OEHc*0CMGhe-N6=4|8sGY5Vp2R@qv$1k_6_P@-5=UPV|7b4p_
zqM5Ar^NocQSM1wTid*-2t$_<G_P>YX*5_q+4&0vuk0G9q`?-CSK_G4$=@>TG<IJ{*
zCQiPsN&1z+U-^8!gLnaNhf&M(^?QQjmpOYL*^~Ac#EJc0x_|bX=HXL{w+L9lL=GjA
zu2Vcl0*>iVMhQ@k-<rhE8O$U#P@JQ9jM~{x@dpsk$NfKT@w1fT*7M;9)XvA$&lA*6
zt-<GDhh_h7qx=JO+;33+8FY`tVT_K;;@~#yEbV_vho=nOzT&(h%aqOkpV4ujrv5xc
z4LwWo+ti;bHh?54vfnSsx_ZE;yA;sW9$#2jHL2Uz>jOp8!+KwLH+D#pHz@V^gI%&;
z^6Eh?EXjQbKnVsyepOe!uA1x&!;U0tn%pm`y}H&9-I^RwC2wCK&=0|`y{e+)TSt;I
zU<rrTm+3sL2SN`kiho<b*8P+#2w~OVE%}4N5cmS2K21gc%!=fdbs300LSzbt=Zmuo
z_lG4qQB~7=gGO)bGmSs-NS=-sNg{rr(&E_O<v>`MH65X4{t-?{Q&(Ua0MlDeV<-)3
zDCq0Oz;8iwhHof$wlw~<QEKwEZSOFA^M-@c9=X@+SAi`Bopwmqkni_(DH+Z&WNAu>
z7|Ts!5YmE57=gtVXCPutJ9jPyq$?bjOjiSHAgt;TkbS*ih7_sGT~v+u8!-lOh5G}#
z+=WutOu2{EaJ%W?Qumn44z8tOfh)sZmtoEoHU)YDF5Gbe+(_Uu?kFx<*EL^PpRSTO
z-T$68q6u<>uyc;xTTW8bFXMl?%!H5CvQ&yKqR(jTe#8Dp(%+JcI@b30vFE-FeRi%_
zQzE-hFazxTV6qN7?$6L??-4iEXS`hc&DfFYKf718Q+@Vcw(7I?c8fkc@86(5Gd3_H
zl~#YAMx0<Qe(W5cr26&$MSmCe6aU$LhS8b+dInHQxFj+80@iWtkO5{Cr|9@U%)m&M
z=`onJt$Tv>U8njV(4X3*xfL^;KZ^^wX|lOvbumqnizTL?TZ~)BC$wz(BK^;9otRbs
EKb_svjsO4v

literal 0
HcmV?d00001

diff --git a/examples/asm/example/example.S b/examples/asm/example/example.S
new file mode 100644
index 00000000..f487950a
--- /dev/null
+++ b/examples/asm/example/example.S
@@ -0,0 +1,67 @@
+// example.s
+// David_Harris@hmc.edu 5 December 2021
+
+.section .text.init
+//.globl rvtest_entry_point
+//rvtest_entry_point:
+
+.globl main
+main:
+    li a0, 42
+
+self_loop:
+    j self_loop
+
+.end
+
+/*
+#include "model_test.h"
+#include "arch_test.h"
+RVTEST_ISA("RV32I")
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+
+#ifdef TEST_CASE_1
+
+RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
+
+RVTEST_SIGBASE( x3,signature_x3_1)
+
+inst_0:
+// rs2 == rd != rs1, rs1==x4, rs2==x24, rd==x24, rs1_val > 0 and rs2_val > 0, rs2_val == 1, rs1_val == (2**(xlen-1)-1), rs1_val != rs2_val, rs1_val == 2147483647
+// opcode: add ; op1:x4; op2:x24; dest:x24; op1val:0x7fffffff;  op2val:0x1
+TEST_RR_OP(add, x24, x4, x24, 0x80000000, 0x7fffffff, 0x1, x3, 0, x18)
+
+
+80000000 <rvtest_entry_point>:
+
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+80000000:	feedc0b7          	lui	ra,0xfeedc
+8
+
+80003220 <rvtest_code_end>:
+#endif
+
+
+RVTEST_CODE_END
+RVMODEL_HALT
+80003220:	00408093          	addi	ra,ra,4
+80003224:	00100093          	li	ra,1
+
+80003228 <write_tohost>:
+80003228:	00001f17          	auipc	t5,0x1
+8000322c:	dc1f2c23          	sw	ra,-552(t5) # 80004000 <tohost>
+
+80003230 <self_loop>:
+80003230:	0000006f          	j	80003230 <self_loop>
+80003234:	0000                	unimp
+	...
+*/
\ No newline at end of file
diff --git a/examples/asm/test b/examples/asm/test
new file mode 100755
index 0000000000000000000000000000000000000000..fef7868c62fa8bccead16fa64818e3fd0ba85236
GIT binary patch
literal 6296
zcmeHLZ%iD=6@R<8cL%lWfRDzcCINHQVC0^-m=@AF^f)-cj)NMUSg}=iIrbKO&K-yM
z7ROX_a(_5uh~vn*h$A1WAdp<ksam&5N}4pX9b(yPWwn)RrB$Q~8xp8wiMlbyO=HtH
zyEAYccj||JX(UFPeKWuLy*F>({Mp%k$+fG2=Qv=AhtGl3E@)2x2W`mzhF&nDa6mQi
z_*@5H*H{EwO3aoniv_)fNyyRbq}7DEgtnLD>3k+nn04MqR5HCd*84Bl$`+%sQvO*a
zl-L9i4|DHYV%)stSon+VlVR5^K+Xnq%3{2<<)KS@>C<n`!f@FvTrl&lt-v+R!h{e$
zQ=3~n5xvaKo2E|963gM=yU?=BnZVAcF~=IM$8X&kY2`h&TqHyor;rhkh35%tg8`re
zS&@*%ILt>vwYgze@q}rrymuBt>kaRO=eGM#jYks2G3>33%PpSSIpOlSym51{(~{lq
z+?M?>hw0|#Da+o+9MYO>un4`*aD72*OxPqu5|ah5-%n!K5q4(gjaH{;#KU`y?nvl~
zy7E5h&^RA|VID3{esDd0*tGD(z<YyhC)ZBbnkW4q-_N}f3B6?+cMO;kJiy>!N9Z(I
z&0{cX8UrilQ6oysqXJ6IqXv|iM|qT(M>&+3M*$^fjLqEK1M$HaTze%xXymjff9;jM
zWAVXK(EB(RnGS9KVlZ@Z!^5xE3{D;zzx$K1{fAoqVR$b*xAX3?DZ^s}g(DN2zihs}
z=jOhdA5FDQNLkr@`O80lIkxlO-e^fbZ0x<gAT<kcQuy6#(y=vsbgZ{Xio9SrT6sNh
zGQV=+bgRj8Lv{9y^zc8vanSkv$n(6<jq!+<_QR0pUX|3_Cs^MW!2L<IG~53E-~br5
z_QTw(;nMzDK4Cysv}&MG%Io7M`%3?P^^=-@?^v{ShdugEZw_I-KD{r-C$68jqA%U&
zZCJiFMrQR=hszW1>#MT}LjA)hHcy#u#-FKlgs-^sYF;a7y_e_CizGh%QlB9*KWAg%
z2Cji~We*$1!gJB8zQSLQ4>cZblAJRp<0VUe71Rt_tFPol&zSAThQ}ZL4Bnc#0@gDd
z?AGeP6!kYqaE*_fO5vo*SUPn1*NGF8oQteZbCGrX{3H9%M^87}IoF>~TF-u5v78qP
z9eoy=S${MJaotLFM&O3Y9w_fMO+7Az9Jp=)E^@=TcJD+&O|s7yKpsiw=y|Y}o)!0L
zy=BMlx^M3RD962!oQ^-F@8{}o>T-t4WX@N)td9y{-L|W5R<8GdcJpsWSo2jL(5mmN
z5m=4DY6Mmz@P843AJF?SbB5I$>*~H&RMy!1?3N<C-DbB{Ky4**6mL*E3|u)Dg&d=D
z_`8+fN4qLSKY6&xqn$iF<RRgMSxqku_-<$K`(%azZ~X-Vd-E-|7{CDR-oAtaq5_nq
zjDxfrzzEf8aT7Sw;$|4yn6BR}IF}aBPIhClY=EyVmRW&V72wtat23F41wJVb^s@yD
zGw_KXmnIHmMu;7DUm`q`9GE#+@}G@vmxiy554o=qJM8|2RV}@QPh#g?8V5GD$2DAl
zij;W%6!CQ9{gr0z*23~{Ie@n{eC53ShT=^r_TSg=ESO1|mk%=F=QVugy1IjSIzK<k
zfL}$N!!Js<Pnz&sjikR~PG@H#1OE36_;d#RpBeCb8SqT&$A}9c-TFZ@Y5lio3&yx&
zzm!lsb$?Z9xUgd1HBmfupZ+id9>{>l5YNGV<S5Vx#BD7lu(}>c_8>hs$TvSpZ)p6L
z`}!A%=kjJ4PFX*{B{(ecvvf1?2WtNy{Vq93@#_?K7_fke9Fin`PVpCc9sf{=VGDi-
z6F)CtCaH$v0>xjXb`DcKAMqUAcd6^VgyN~^QU$g1XX@u!YNtx$bI?F>3d45FS82cO
z<Qhl!NF2`4_^>$CX?9lb(-sXkuQ(?Q(M~%5_tAcLQGXtx4(+A*ZR$@kb5s;1x6dcK
zRr!clwMn4J9p0cSD`LC1(+iTK2G#ENc5DzuPeAPO1=`#`(W3^Gpy=*C0#d-=<&#y}
zW3#7cXm&)mqPTlRxl>hopj~nMWzo~^_xC`c?Vv2F_!bn!Bv{0*)nz)8^t9CS<es1{
z0L>6o6+1Yg4(dtqQSkb^x)m8+)C;1=t-67jK!}V&bAEAv!JeQ<$0{pIXFzLhXsLb5
zCAymHMUl9IN{iilmIFc6t*8hsbCGbm6nO=f1TekjG=|c+b_Kkh82b`5r}>6*cYW<M
zwW8D2xT9I~%@YiW2i%<=pA2j^=&-v~1^GU2o0Q}nLzaewh&JOS23<-(3L>yL=?p~7
zxqJ6wK-z*qQFqlZ`-8Fyez&(1^pGNTxr?$Ee=WuUwqTE6b+@5Z6<r=+C0ubT*pz@q
zx5)?e6#%xSpn)yPZJW*u>H<9i8!kRSt|>G^u1_|%sw&>LZdE2P+y60bM169Su=9@H
zr_NEkzLftZxV@I8O;{uP3}^SQ0{Xv{*=0(Eo1C^_g<z~3c0XhPTdA2vmDKt+Y+0A2
z&)yGZl*sNw%m6!wnEXCAJdmW%-bd9`pYby3KZy;={<C|bgX%v=-|wmVtp0S0KD$2-
z(VsN=j7VjwKhGgfFcv>{o}Z)o)&E6*KeiM9*?o-Bnf`hPP|4<x$#%rC@2(UYd`SEM
zPD%sQV=$?+wZkwX?^69Hx`5UqX2Z<J&*DOE&}{5jTuct?xR_!*wSRJdPN)Ayo^I;M
KqD8%ss{bFt@8ItM

literal 0
HcmV?d00001

diff --git a/examples/asm/test.S b/examples/asm/test.S
new file mode 100644
index 00000000..0399a456
--- /dev/null
+++ b/examples/asm/test.S
@@ -0,0 +1,22 @@
+.globl main 
+.equ N, 5
+
+.data
+//A: .word 5, 42, −88, 2, −5033, 720, 314 
+str1: .string "RISC-V"
+.align 2
+B: .word 0x32A
+.bss
+C: .space 
+D: .space
+.balign 4 
+
+.text 
+main:
+    li a0, 42
+    jr ra
+
+.section .rodata 
+str2: .string "Hello"
+
+.end
diff --git a/wally-pipelined/regression/fpga-wave.do b/wally-pipelined/regression/fpga-wave.do
index a5916df3..43585e87 100644
--- a/wally-pipelined/regression/fpga-wave.do
+++ b/wally-pipelined/regression/fpga-wave.do
@@ -126,23 +126,17 @@ add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/r
 add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/rd2
 add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/we3
 add wave -noupdate -group RegFile /testbench/dut/wallypipelinedsoc/hart/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ALUResultW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/IntResultW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ReadDataW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/CSRReadValW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultSrcW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/wallypipelinedsoc/hart/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/a
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/b
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/ALUControl
 add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/flags
+add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/FlagsEEEEE
 add wave -noupdate -group alu -divider internals
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/overflow
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/carry
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/zero
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/neg
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/lt
-add wave -noupdate -group alu /testbench/dut/wallypipelinedsoc/hart/ieu/dp/alu/ltu
 add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs1D
 add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs2D
 add wave -noupdate -group Forward /testbench/dut/wallypipelinedsoc/hart/ieu/fw/Rs1E
@@ -167,8 +161,8 @@ add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCE
 add wave -noupdate -group PCS /testbench/dut/wallypipelinedsoc/hart/PCM
 add wave -noupdate -group PCS /testbench/PCW
 add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/InstrD
-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/SrcAE
-add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/SrcBE
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/ForwardedSrcAE
+add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/ForwardedSrcBE
 add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/Funct3E
 add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/MulDivE
 add wave -noupdate -group muldiv /testbench/dut/wallypipelinedsoc/hart/mdu/W64E
diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index 4532b932..ff0b82be 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -151,11 +151,11 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
 add wave -noupdate -group alu -divider internals
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
diff --git a/wally-pipelined/regression/wave-all.do b/wally-pipelined/regression/wave-all.do
index e7bf6067..097f3478 100644
--- a/wally-pipelined/regression/wave-all.do
+++ b/wally-pipelined/regression/wave-all.do
@@ -499,7 +499,7 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/WriteDataE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/TargetBaseE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultM
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ALUResultW
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/IntResultW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/ResultW
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/clk
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/regf/reset
@@ -562,27 +562,11 @@ add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/d0
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/d1
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/s
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/srcbmux/y
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/a
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/b
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/alucontrol
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/flags
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/condinvb
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/presum
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sum
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/shift
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/slt
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sltu
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/bor
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/right
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/arith
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/w64
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/carry
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/zero
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/neg
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/lt
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/ltu
-add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/overflow
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/A
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/B
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/ALUControl
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/Result
+add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/FlagsE
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/a
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/amt
 add wave -noupdate -radix hexadecimal /testbench/dut/hart/ieu/dp/alu/sh/right
diff --git a/wally-pipelined/regression/wave-coremark.do b/wally-pipelined/regression/wave-coremark.do
index 5ce1a232..4d774046 100644
--- a/wally-pipelined/regression/wave-coremark.do
+++ b/wally-pipelined/regression/wave-coremark.do
@@ -130,11 +130,11 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
 add wave -noupdate -group alu -divider internals
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 8bff207f..e8c76de0 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -127,23 +127,17 @@ add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/IntResultW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
+add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
 add wave -noupdate -group alu -divider internals
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
 add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
 add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
 add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
@@ -168,8 +162,8 @@ add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
 add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
 add wave -noupdate -expand -group PCS /testbench/PCW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcAE
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/SrcBE
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcAE
+add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcBE
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E
@@ -178,8 +172,6 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/genblk1/div/start
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivDoneM
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
 add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
 add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N

From 10dfefa8ada018a6758990b33b56b8b1e0d48950 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 05:36:32 -0800
Subject: [PATCH 47/95] Simplified FWriteInt interfaces by merging into
 RegWrite

---
 wally-pipelined/src/fpu/fpu.sv                | 16 ++--
 wally-pipelined/src/ieu/controller.sv         | 37 ++------
 wally-pipelined/src/ieu/datapath.sv           | 20 ++--
 wally-pipelined/src/ieu/forward.sv            | 10 +-
 wally-pipelined/src/ieu/ieu.sv                | 13 ++-
 wally-pipelined/src/lsu/subwordread.sv        | 94 +++++++++----------
 .../src/wally/wallypipelinedhart.sv           |  8 +-
 7 files changed, 91 insertions(+), 107 deletions(-)

diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv
index d38dcd51..0ba61c6c 100755
--- a/wally-pipelined/src/fpu/fpu.sv
+++ b/wally-pipelined/src/fpu/fpu.sv
@@ -36,7 +36,7 @@ module fpu (
   input logic [4:0] 	   RdM, RdW, // which FP register to write to (from IEU)
   output logic 		   FRegWriteM, // FP register write enable
   output logic 		   FStallD, // Stall the decode stage
-  output logic 		   FWriteIntE, FWriteIntM, FWriteIntW, // integer register write enable
+  output logic 		   FWriteIntE, // integer register write enables
   output logic [`XLEN-1:0] FWriteDataE, // Data to be written to memory
   output logic [`XLEN-1:0] FIntResM, // data to be written to integer register
   output logic 		   FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
@@ -260,9 +260,9 @@ module fpu (
      flopenrc #(64) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM); 
      flopenrc #(5)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, FFlgE, FFlgM);      
      flopenrc #(`XLEN) EMRegSgnRes (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
-     flopenrc #(8) EMCtrlReg (clk, reset, FlushM, ~StallM,
-			       {FRegWriteE, FResultSelE, FrmE, FmtE, FWriteIntE},
-			       {FRegWriteM, FResultSelM, FrmM, FmtM, FWriteIntM});
+     flopenrc #(7) EMCtrlReg (clk, reset, FlushM, ~StallM,
+			       {FRegWriteE, FResultSelE, FrmE, FmtE},
+			       {FRegWriteM, FResultSelM, FrmM, FmtM});
      
      // BEGIN MEMORY STAGE
      
@@ -273,9 +273,9 @@ module fpu (
      flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); 
      flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); 
      flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
-     flopenrc #(5)  MWCtrlReg(clk, reset, FlushW, ~StallW,
-			      {FRegWriteM, FResultSelM, FmtM, FWriteIntM},
-			      {FRegWriteW, FResultSelW, FmtW, FWriteIntW});
+     flopenrc #(4)  MWCtrlReg(clk, reset, FlushW, ~StallW,
+			      {FRegWriteM, FResultSelM, FmtM},
+			      {FRegWriteW, FResultSelW, FmtW});
      
      // BEGIN WRITEBACK STAGE
      
@@ -290,8 +290,6 @@ module fpu (
   end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
      assign FStallD = 0;
      assign FWriteIntE = 0; 
-     assign FWriteIntM = 0;
-     assign FWriteIntW = 0;
      assign FWriteDataE = 0;
      assign FIntResM = 0;
      assign FDivBusyE = 0;
diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 02e380a4..907aa650 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -37,6 +37,7 @@ module controller(
   // Execute stage control signals
   input logic 	     StallE, FlushE,  
   input logic  [2:0] FlagsE, 
+  input  logic       FWriteIntE,
   output logic       PCSrcE,        // for datapath and Hazard Unit
   output logic [2:0] ALUControlE, 
   output logic 	     ALUSrcAE, ALUSrcBE,
@@ -56,6 +57,7 @@ module controller(
   output logic       RegWriteM,     // for Hazard Unit
   output logic       InvalidateICacheM, FlushDCacheM,
   output logic       InstrValidM, 
+  output logic       FWriteIntM,
   // Writeback stage control signals
   input  logic       StallW, FlushW,
   output logic 	     RegWriteW,     // for datapath and Hazard Unit
@@ -98,6 +100,7 @@ module controller(
   logic        zeroE, ltE, ltuE;
   logic        unused;
 	logic        BranchFlagE;
+  logic        IEURegWriteE;
 
   // Extract fields
   assign OpD = InstrD[6:0];
@@ -167,25 +170,13 @@ module controller(
   assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
   assign CSRWriteD = CSRReadD & !(CSRZeroSrcD && InstrD[13]); // Don't write if setting or clearing zeros
 
-  // ALU Decoding *** should move to ALU for better modularity
+  // ALU Decoding
   assign sltD = (Funct3D == 3'b010);
   assign sltuD = (Funct3D == 3'b011);
   assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);
   assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
-
   assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
-//  assign SubArithD = aluc3D; // ***cleanup
-
-  // *** replace all of this
   assign ALUControlD = {W64D, SubArithD, ALUOpD};
-/*  always_comb
-    case(ALUOpD)
-      2'b00:                ALUControlD = 5'b00000; // addition
-      2'b01:                ALUControlD = 5'b00000;  // add for branch offset
-//      2'b01:                ALUControlD = 5'b01000;  // subtraction
-//      2'b11:                ALUControlD = 5'b01110;  // pass B through for lui ***no longer used
-      default:              ALUControlD = {W64D, aluc3D, Funct3D}; // R-type instructions
-    endcase*/
 
   // Fences
   // Ordinary fence is presently a nop
@@ -208,32 +199,24 @@ module controller(
   // Execute stage pipeline control register and logic
   flopenrc #(27) controlregE(clk, reset, FlushE, ~StallE,
                            {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MulDivD, AtomicD, InvalidateICacheD, FlushDCacheD, InstrValidD},
-                           {RegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
+                           {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
 
   // Branch Logic
   assign {zeroE, ltE, ltuE} = FlagsE;
   mux4 #(1) branchflagmux(zeroE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
   assign BranchTakenE = BranchFlagE ^ Funct3E[0];
-/*  always_comb
-    case(Funct3E)
-      3'b000:  BranchTakenE = zeroE;  // beq
-      3'b001:  BranchTakenE = ~zeroE; // bne
-      3'b100:  BranchTakenE = ltE;    // blt
-      3'b101:  BranchTakenE = ~ltE;   // bge
-      3'b110:  BranchTakenE = ltuE;   // bltu
-      3'b111:  BranchTakenE = ~ltuE;  // bgeu
-      default: BranchTakenE = 1'b0; // undefined mode
-    endcase*/
     
   assign PCSrcE = JumpE | BranchE & BranchTakenE;
 
   assign MemReadE = MemRWE[1];
   assign SCE = (ResultSrcE == 3'b100);
+
+  assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
   
   // Memory stage pipeline control register
-  flopenrc #(17) controlregM(clk, reset, FlushM, ~StallM,
-                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE},
-                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, AtomicM, InvalidateICacheM, FlushDCacheM, InstrValidM});
+  flopenrc #(18) controlregM(clk, reset, FlushM, ~StallM,
+                         {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE},
+                         {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, InstrValidM});
   
   // Writeback stage pipeline control register
   flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW,
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index d0a046e1..9ad32acb 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -53,7 +53,6 @@ module datapath (
   output logic [`XLEN-1:0] WriteDataM, 
   // Writeback stage signals
   input  logic             StallW, FlushW,
-  input  logic             FWriteIntW,
   input  logic             RegWriteW, 
   input  logic             SquashSCW,
   input  logic [2:0]       ResultSrcW,
@@ -92,8 +91,7 @@ module datapath (
   assign Rs1D      = InstrD[19:15];
   assign Rs2D      = InstrD[24:20];
   assign RdD       = InstrD[11:7];
-  // *** can FWriteIntW be merged with RegWriteW
-  regfile regf(clk, reset, {RegWriteW | FWriteIntW}, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
+  regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
   extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
  
   // Execute stage pipeline register and logic
@@ -106,7 +104,6 @@ module datapath (
 	
   mux3  #(`XLEN)  faemux(RD1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);
   mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
-  mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
   comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);
@@ -119,12 +116,23 @@ module datapath (
   flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM);
   flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM);
   flopenrc #(5)     RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM);	
-  mux2  #(`XLEN)    resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
   
   // Writeback stage pipeline register and logic
   flopenrc #(`XLEN) ResultWReg(clk, reset, FlushW, ~StallW, ResultM, ResultW);
   flopenrc #(5)     RdWReg(clk, reset, FlushW, ~StallW, RdM, RdW);
   flopen #(`XLEN)   ReadDataWReg(.clk, .en(~StallW), .d(ReadDataM), .q(ReadDataW));
+  mux5  #(`XLEN)    resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);	 
+
+  // floating point interactions: fcvt, fp stores
+  generate
+    if (`F_SUPPORTED) begin:fpmux
+      mux2  #(`XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM);
+      mux2  #(`XLEN)  writedatamux(ForwardedSrcBE, FWriteDataE, ~IllegalFPUInstrE, WriteDataE);
+    end else begin
+      assign ResultM = IEUResultM;
+      assign WriteDataE = ForwardedSrcBE;
+    end
+  endgenerate
 
   // handle Store Conditional result if atomic extension supported
   generate
@@ -133,6 +141,4 @@ module datapath (
     else 
       assign SCResultW = 0;
   endgenerate
-
-  mux5  #(`XLEN) resultmuxW(ResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, WriteDataW);	 
 endmodule
diff --git a/wally-pipelined/src/ieu/forward.sv b/wally-pipelined/src/ieu/forward.sv
index cab6c3ed..40f3cd98 100644
--- a/wally-pipelined/src/ieu/forward.sv
+++ b/wally-pipelined/src/ieu/forward.sv
@@ -30,7 +30,7 @@ module forward(
   input logic [4:0]  Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW,
   input logic        MemReadE, MulDivE, CSRReadE,
   input logic        RegWriteM, RegWriteW,
-  input logic	       FWriteIntE, FWriteIntM, FWriteIntW,
+  input logic	       FWriteIntE, 
   input logic        SCE,
   // Forwarding controls
   output logic [1:0] ForwardAE, ForwardBE,
@@ -41,12 +41,12 @@ module forward(
     ForwardAE = 2'b00;
     ForwardBE = 2'b00;
     if (Rs1E != 5'b0)
-      if      ((Rs1E == RdM) & (RegWriteM|FWriteIntM)) ForwardAE = 2'b10;
-      else if ((Rs1E == RdW) & (RegWriteW|FWriteIntW)) ForwardAE = 2'b01;
+      if      ((Rs1E == RdM) & RegWriteM) ForwardAE = 2'b10;
+      else if ((Rs1E == RdW) & RegWriteW) ForwardAE = 2'b01;
  
     if (Rs2E != 5'b0)
-      if      ((Rs2E == RdM) & (RegWriteM|FWriteIntM)) ForwardBE = 2'b10;
-      else if ((Rs2E == RdW) & (RegWriteW|FWriteIntW)) ForwardBE = 2'b01;
+      if      ((Rs2E == RdM) & RegWriteM) ForwardBE = 2'b10;
+      else if ((Rs2E == RdW) & RegWriteW) ForwardBE = 2'b01;
   end
 
   // Stall on dependent operations that finish in Mem Stage and can't bypass in time
diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv
index 101ca4da..aabd8798 100644
--- a/wally-pipelined/src/ieu/ieu.sv
+++ b/wally-pipelined/src/ieu/ieu.sv
@@ -40,9 +40,7 @@ module ieu (
   output logic [`XLEN-1:0] IEUAdrE,
   output logic 		   MulDivE, W64E,
   output logic [2:0] 	   Funct3E,
-  output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-//  output logic [`XLEN-1:0] SrcAE, SrcBE,
-  input logic 		   FWriteIntM,
+  output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
 
   // Memory stage interface
   input logic 		   SquashSCW, // from LSU
@@ -59,7 +57,6 @@ module ieu (
 
   // Writeback stage
   input logic [`XLEN-1:0]  CSRReadValW, ReadDataM, MulDivResultW,
-  input logic 		   FWriteIntW,
   output logic [4:0]       RdW,
   output logic [`XLEN-1:0] ReadDataW,
   // input  logic [`XLEN-1:0] PCLinkW,
@@ -82,6 +79,7 @@ module ieu (
   logic        ALUResultSrcE;
   logic        SCE;
   logic [4:0]  RdE;
+  logic        FWriteIntM;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E;
@@ -96,7 +94,7 @@ module ieu (
     .StallD, .FlushD, .InstrD, .ImmSrcD,
     .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
     // Execute stage control signals
-    .StallE, .FlushE, .FlagsE, 
+    .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE,        // for datapath and Hazard Unit
     .ALUControlE, .ALUSrcAE, .ALUSrcBE,
     .ALUResultSrcE,
@@ -109,6 +107,7 @@ module ieu (
     .SCE, .AtomicE, .AtomicM, .Funct3M,
     .RegWriteM,     // for Hazard Unit
     .InvalidateICacheM, .FlushDCacheM, .InstrValidM, 
+    .FWriteIntM,
     // Writeback stage control signals
     .StallW, .FlushW,
     .RegWriteW,     // for datapath and Hazard Unit
@@ -133,7 +132,7 @@ module ieu (
     .StallM, .FlushM, .FWriteIntM, .FIntResM, 
     .SrcAM, .WriteDataM,
     // Writeback stage signals
-    .StallW, .FlushW, .FWriteIntW, .RegWriteW, 
+    .StallW, .FlushW, .RegWriteW, 
     .SquashSCW, .ResultSrcW, .ReadDataW,
     // input  logic [`XLEN-1:0] PCLinkW,
     .CSRReadValW, .ReadDataM, .MulDivResultW, 
@@ -146,7 +145,7 @@ module ieu (
     .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
     .MemReadE, .MulDivE, .CSRReadE,
     .RegWriteM, .RegWriteW,
-    .FWriteIntE, .FWriteIntM, .FWriteIntW,
+    .FWriteIntE,
     .SCE,
     // Forwarding controls
     .ForwardAE, .ForwardBE,
diff --git a/wally-pipelined/src/lsu/subwordread.sv b/wally-pipelined/src/lsu/subwordread.sv
index 1e975725..1f04c4cb 100644
--- a/wally-pipelined/src/lsu/subwordread.sv
+++ b/wally-pipelined/src/lsu/subwordread.sv
@@ -42,82 +42,82 @@ module subwordread (
       logic [`XLEN-1:0] offset4, offset5, offset6, offset7;
 
       always_comb
-	case(Funct3M[1:0])
-	  3: offset0 = ReadDataWordMuxM;                                                               //ld
-	  2: offset0 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[31:0]} : {{32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; //lw(u)
-	  1: offset0 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[15:0]} : {{48{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u)
-	  0: offset0 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[7:0]}  : {{56{ReadDataWordMuxM[7]}},  ReadDataWordMuxM[7:0]};  //lb(u)
-	endcase
+		case(Funct3M[1:0])
+		3: offset0 = ReadDataWordMuxM;                                                               //ld
+		2: offset0 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[31:0]} : {{32{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:0]}; //lw(u)
+		1: offset0 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[15:0]} : {{48{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u)
+		0: offset0 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[7:0]}  : {{56{ReadDataWordMuxM[7]}},  ReadDataWordMuxM[7:0]};  //lb(u)
+		endcase
 
       assign offset1 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[15:8]} : {{56{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:8]}; //lb(u)
       
       always_comb
-	case(Funct3M[0])
-	  1: offset2 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[31:16]} : {{48{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u)
-	  0: offset2 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[23:16]} : {{56{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u)
-	endcase
+		case(Funct3M[0])
+		1: offset2 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[31:16]} : {{48{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u)
+		0: offset2 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[23:16]} : {{56{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u)
+		endcase
 
       assign offset3 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[31:24]} : {{56{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:24]};//lb(u)
 
       always_comb
-	case(Funct3M[1:0])
-	  3: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//ld(u) // unaligned will cause fault.
-	  2: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//lw(u)
-	  1: offset4 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[47:32]} : {{48{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:32]};//lh(u)
-	  0: offset4 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[39:32]} : {{56{ReadDataWordMuxM[39]}}, ReadDataWordMuxM[39:32]};//lb(u)
-	endcase
+		case(Funct3M[1:0])
+		3: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//ld(u) // unaligned will cause fault.
+		2: offset4 = Funct3M[2] ? {{32'b0}, ReadDataWordMuxM[63:32]} : {{32{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:32]};//lw(u)
+		1: offset4 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[47:32]} : {{48{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:32]};//lh(u)
+		0: offset4 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[39:32]} : {{56{ReadDataWordMuxM[39]}}, ReadDataWordMuxM[39:32]};//lb(u)
+		endcase
       
       assign offset5 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[47:40]} : {{56{ReadDataWordMuxM[47]}}, ReadDataWordMuxM[47:40]};//lb(u)
 
       always_comb
-	case(Funct3M[0])
-	  1: offset6 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[63:48]} : {{48{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:48]};//lh(u)
-	  0: offset6 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[55:48]} : {{56{ReadDataWordMuxM[55]}}, ReadDataWordMuxM[55:48]};//lb(u)
-	endcase
-      
+		case(Funct3M[0])
+		1: offset6 = Funct3M[2] ? {{48'b0}, ReadDataWordMuxM[63:48]} : {{48{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:48]};//lh(u)
+		0: offset6 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[55:48]} : {{56{ReadDataWordMuxM[55]}}, ReadDataWordMuxM[55:48]};//lb(u)
+		endcase
+		
       assign offset7 = Funct3M[2] ? {{56'b0}, ReadDataWordMuxM[63:56]} : {{56{ReadDataWordMuxM[63]}}, ReadDataWordMuxM[63:56]};//lb(u)
 
       // address mux
       always_comb
-	case(MemPAdrM[2:0])
-	  0: ReadDataM = offset0;
-	  1: ReadDataM = offset1;
-	  2: ReadDataM = offset2;
-	  3: ReadDataM = offset3;
-	  4: ReadDataM = offset4;
-	  5: ReadDataM = offset5;
-	  6: ReadDataM = offset6;
-	  7: ReadDataM = offset7;
-	endcase
+		case(MemPAdrM[2:0])
+		0: ReadDataM = offset0;
+		1: ReadDataM = offset1;
+		2: ReadDataM = offset2;
+		3: ReadDataM = offset3;
+		4: ReadDataM = offset4;
+		5: ReadDataM = offset5;
+		6: ReadDataM = offset6;
+		7: ReadDataM = offset7;
+		endcase
 
     end else begin // 32-bit
      // byte mux
       always_comb
-	case(Funct3M[1:0])
-	  3: offset0 = ReadDataWordMuxM;                                                                 //ld  illegal
-	  2: offset0 = ReadDataWordMuxM[31:0];                                                           //lw
-	  1: offset0 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[15:0]} : {{16{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u)
-	  0: offset0 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[7:0]}  : {{24{ReadDataWordMuxM[7]}},  ReadDataWordMuxM[7:0]};  //lb(u)
-	endcase
+		case(Funct3M[1:0])
+		  3: offset0 = ReadDataWordMuxM;                                                                 //ld  illegal
+		  2: offset0 = ReadDataWordMuxM[31:0];                                                           //lw
+		  1: offset0 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[15:0]} : {{16{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:0]}; //lh(u)
+		  0: offset0 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[7:0]}  : {{24{ReadDataWordMuxM[7]}},  ReadDataWordMuxM[7:0]};  //lb(u)
+		endcase
 
       assign offset1 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[15:8]} : {{24{ReadDataWordMuxM[15]}}, ReadDataWordMuxM[15:8]}; //lb(u)
       
       always_comb
-	case(Funct3M[0])
-	  1: offset2 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[31:16]} : {{16{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u)
-	  0: offset2 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[23:16]} : {{24{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u)
-	endcase
+		case(Funct3M[0])
+		  1: offset2 = Funct3M[2] ? {{16'b0}, ReadDataWordMuxM[31:16]} : {{16{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:16]};//lh(u)
+		  0: offset2 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[23:16]} : {{24{ReadDataWordMuxM[23]}}, ReadDataWordMuxM[23:16]};//lb(u)
+		endcase
 
       assign offset3 = Funct3M[2] ? {{24'b0}, ReadDataWordMuxM[31:24]} : {{24{ReadDataWordMuxM[31]}}, ReadDataWordMuxM[31:24]};//lb(u)
 
       // address mux
       always_comb
-	case(MemPAdrM[1:0])
-	  0: ReadDataM = offset0;
-	  1: ReadDataM = offset1;
-	  2: ReadDataM = offset2;
-	  3: ReadDataM = offset3;
-	endcase
+		case(MemPAdrM[1:0])
+		  0: ReadDataM = offset0;
+		  1: ReadDataM = offset1;
+		  2: ReadDataM = offset2;
+		  3: ReadDataM = offset3;
+		endcase
     end
   endgenerate
 endmodule
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 13c2e77a..7be5b8c6 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -89,7 +89,7 @@ module wallypipelinedhart (
   logic [2:0] 		    FRM_REGW;
    logic [4:0]        RdM, RdW;
   logic 		    FStallD;
-  logic 		    FWriteIntE, FWriteIntM, FWriteIntW;
+  logic 		    FWriteIntE;
   logic [`XLEN-1:0] 	    FWriteDataE;
   logic [`XLEN-1:0] 	    FIntResM;  
   logic 		    FDivBusyE;
@@ -210,8 +210,6 @@ module wallypipelinedhart (
      .PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE,
      .FWriteDataE, .IEUAdrE, .MulDivE, .W64E,
      .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-     //.SrcAE, .SrcBE, 
-     .FWriteIntM,
 
      // Memory stage interface
      .SquashSCW, // from LSU
@@ -225,7 +223,7 @@ module wallypipelinedhart (
 
      // Writeback stage
      .CSRReadValW, .ReadDataM, .MulDivResultW,
-     .FWriteIntW, .RdW, .ReadDataW,
+     .RdW, .ReadDataW,
      .InstrValidM, 
 
      // hazards
@@ -370,7 +368,7 @@ module wallypipelinedhart (
      .RdM, .RdW, // which FP register to write to (from IEU)
      .FRegWriteM, // FP register write enable
      .FStallD, // Stall the decode stage
-     .FWriteIntE, .FWriteIntM, .FWriteIntW, // integer register write enable
+     .FWriteIntE, // integer register write enable
      .FWriteDataE, // Data to be written to memory
      .FIntResM, // data to be written to integer register
      .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)

From 23c6b6370fb2e445edd3c7316c7aa82c5499d7dd Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 05:40:38 -0800
Subject: [PATCH 48/95] Forwarding logic factoring

---
 wally-pipelined/src/ieu/forward.sv | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/ieu/forward.sv b/wally-pipelined/src/ieu/forward.sv
index 40f3cd98..d041f943 100644
--- a/wally-pipelined/src/ieu/forward.sv
+++ b/wally-pipelined/src/ieu/forward.sv
@@ -36,6 +36,8 @@ module forward(
   output logic [1:0] ForwardAE, ForwardBE,
   output logic       FPUStallD, LoadStallD, MulDivStallD, CSRRdStallD
 );
+
+  logic MatchDE;
   
   always_comb begin
     ForwardAE = 2'b00;
@@ -50,9 +52,10 @@ module forward(
   end
 
   // Stall on dependent operations that finish in Mem Stage and can't bypass in time
-   assign FPUStallD = FWriteIntE & ((Rs1D == RdE) | (Rs2D == RdE)); 
-   assign LoadStallD = (MemReadE|SCE) & ((Rs1D == RdE) | (Rs2D == RdE));  
-   assign MulDivStallD = MulDivE & ((Rs1D == RdE) | (Rs2D == RdE)); 
-   assign CSRRdStallD = CSRReadE & ((Rs1D == RdE) | (Rs2D == RdE));
+  assign MatchDE = (Rs1D == RdE) | (Rs2D == RdE); // Decode-stage instruction source depends on result from execute stage instruction
+  assign FPUStallD = FWriteIntE & MatchDE; 
+  assign LoadStallD = (MemReadE|SCE) & MatchDE;  
+  assign MulDivStallD = MulDivE & MatchDE; 
+  assign CSRRdStallD = CSRReadE & MatchDE;
 
 endmodule

From ebcffcdebd027b072af29cd910c7b9b37d99711b Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 09:27:25 -0800
Subject: [PATCH 49/95] Moved W64 truncation after result mux

---
 wally-pipelined/src/ieu/alu.sv      | 34 +++++++++++++----------------
 wally-pipelined/src/ieu/datapath.sv |  6 ++---
 2 files changed, 17 insertions(+), 23 deletions(-)

diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index e2dd7eef..1d49bb40 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -32,7 +32,7 @@ module alu #(parameter WIDTH=32) (
   output logic [WIDTH-1:0] Result,
   output logic [WIDTH-1:0] Sum);
 
-  logic [WIDTH-1:0] CondInvB, SumTrunc, Shift, SLT, SLTU, bor;
+  logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
   logic        Right;
   logic        Carry, Neg;
   logic        LT, LTU;
@@ -50,17 +50,7 @@ module alu #(parameter WIDTH=32) (
   assign CondInvB = SubArith ? ~B : B;
   assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
-  // support W-type RV64I ADDW/SUBW/ADDIW that sign-extend 32-bit result to 64 bits
-  generate
-    if (WIDTH==64)
-      assign SumTrunc = W64 ? {{32{Sum[31]}}, Sum[31:0]} : Sum;
-    else
-      assign SumTrunc = Sum;
-  endgenerate
-  
   // Shifts
-  // assign arith = alucontrol[3]; // sra
-  // assign w64 = alucontrol[4];
   assign Right = (Funct3[2:0] == 3'b101); // sra or srl
   shifter sh(A, B[5:0], Right, SubArith, W64, Shift);
   
@@ -80,14 +70,20 @@ module alu #(parameter WIDTH=32) (
   assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
   always_comb
     case (ALUFunct)
-      3'b000: Result = SumTrunc;  // add or sub
-      3'b001: Result = Shift;     // sll
-      3'b010: Result = SLT;       // slt
-      3'b011: Result = SLTU;      // sltu
-      3'b100: Result = A ^ B;     // xor
-      3'b101: Result = Shift;     // sra or srl
-      3'b110: Result = A | B;     // or 
-      3'b111: Result = A & B;     // and
+      3'b000: FullResult = Sum;       // add or sub
+      3'b001: FullResult = Shift;     // sll
+      3'b010: FullResult = SLT;       // slt
+      3'b011: FullResult = SLTU;      // sltu
+      3'b100: FullResult = A ^ B;     // xor
+      3'b101: FullResult = Shift;     // sra or srl
+      3'b110: FullResult = A | B;     // or 
+      3'b111: FullResult = A & B;     // and
     endcase
+
+  // support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits
+  generate
+    if (WIDTH==64)  assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
+    else            assign Result = FullResult;
+  endgenerate
 endmodule
 
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index 9ad32acb..c36077d2 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -136,9 +136,7 @@ module datapath (
 
   // handle Store Conditional result if atomic extension supported
   generate
-    if (`A_SUPPORTED)
-      assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
-    else 
-      assign SCResultW = 0;
+    if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW};
+    else              assign SCResultW = 0;
   endgenerate
 endmodule

From 53baf3e7877a28b6c23272ed7a8fc871d6ea9dce Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 09:43:09 -0800
Subject: [PATCH 50/95] Cleaning shifter

---
 wally-pipelined/src/ieu/shifter.sv | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/wally-pipelined/src/ieu/shifter.sv b/wally-pipelined/src/ieu/shifter.sv
index 0e53de9d..e09e783c 100644
--- a/wally-pipelined/src/ieu/shifter.sv
+++ b/wally-pipelined/src/ieu/shifter.sv
@@ -38,7 +38,7 @@ module shifter (
   // extension.
 
   generate
-    if (`XLEN==32) begin
+    if (`XLEN==32) begin:shifter
       // funnel shifter (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
       logic [62:0]        z, zshift;
       logic [4:0]         offset;
@@ -56,7 +56,7 @@ module shifter (
       // funnel operation
       assign zshift = z >> offset;
       assign y = zshift[31:0];      
-    end else begin  // RV64
+    end else begin:shifter  // RV64
       // funnel shifter followed by masking
       // research idea: investigate shifter designs for mixed 32/64-bit shifts
       logic [126:0] z, zshift;
@@ -83,12 +83,7 @@ module shifter (
   
       // funnel operation
       assign zshift = z >> offset;
-      assign ylower = zshift[31:0];    
-
-      // mask upper 32 bits for W-type 32-bit shifts
-      // harris: is there a clever way to get zshift[31] earlier for arithmetic right shifts to speed up critical path?
-      assign yupper = w64 ? {32{zshift[31]}} : zshift[63:32];
-      assign y = {yupper, ylower};
+      assign y = zshift[63:0];    
     end
   endgenerate
 endmodule

From eed2765033e571c161861a9727c061b61ea48378 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 10:01:12 -0800
Subject: [PATCH 51/95] Factored out common parts of shifter

---
 wally-pipelined/src/ieu/shifter.sv | 50 ++++++++++++------------------
 1 file changed, 19 insertions(+), 31 deletions(-)

diff --git a/wally-pipelined/src/ieu/shifter.sv b/wally-pipelined/src/ieu/shifter.sv
index e09e783c..de7377a7 100644
--- a/wally-pipelined/src/ieu/shifter.sv
+++ b/wally-pipelined/src/ieu/shifter.sv
@@ -31,40 +31,28 @@ module shifter (
   input  logic             right, arith, w64,
   output logic [`XLEN-1:0] y);
 
+  localparam BITS = $clog2(`XLEN);
+
+  logic [2*`XLEN-2:0]      z, zshift;
+  logic [BITS-1:0]         amttrunc, offset;
+
   // The best shifter architecture differs based on `XLEN.
   // for RV32, only 32-bit shifts are needed.  These are 
   // most efficiently implemented with a funnel shifter.  
   // For RV64, 32 and 64-bit shifts are needed, with sign
   // extension.
 
+  // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
   generate
-    if (`XLEN==32) begin:shifter
-      // funnel shifter (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
-      logic [62:0]        z, zshift;
-      logic [4:0]         offset;
-  
-      // funnel input
-      always_comb  
-        if (right)
+    if (`XLEN==32) begin:shifter // RV32
+      always_comb  // funnel mux
+        if (right) 
           if (arith) z = {{31{a[31]}}, a};
           else       z = {31'b0, a};
         else         z = {a, 31'b0};
-    
-      // shift amount
-      assign offset = right ? amt[4:0] : ~amt[4:0];
-    
-      // funnel operation
-      assign zshift = z >> offset;
-      assign y = zshift[31:0];      
+      assign amttrunc = amt[4:0]; // shift amount
     end else begin:shifter  // RV64
-      // funnel shifter followed by masking
-      // research idea: investigate shifter designs for mixed 32/64-bit shifts
-      logic [126:0] z, zshift;
-      logic [31:0]   ylower, yupper;
-      logic [5:0]         offset, amt6;
-  
-      // funnel input
-      always_comb  
+      always_comb  // funnel mux
         if (w64) begin // 32-bit shifts
           if (right)
             if (arith) z = {64'b0, {31{a[31]}}, a[31:0]};
@@ -76,16 +64,16 @@ module shifter (
             else       z = {63'b0, a};
           else         z = {a, 63'b0};         
         end
-    
-      // shift amount
-      assign amt6 = w64 ? {1'b0, amt[4:0]} : amt[5:0]; // 32 or 64-bit shift
-      assign offset = right ? amt6 : ~amt6;
-  
-      // funnel operation
-      assign zshift = z >> offset;
-      assign y = zshift[63:0];    
+      assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt[5:0]; // 32 or 64-bit shift
     end
   endgenerate
+
+  // opposite offset for right shfits
+  assign offset = right ? amttrunc : ~amttrunc;
+  
+  // funnel operation
+  assign zshift = z >> offset;
+  assign y = zshift[`XLEN-1:0];    
 endmodule
 
 

From 27ec8ff893e053affd1478d9e7488c9c5bf39549 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 10:08:52 -0800
Subject: [PATCH 52/95] Shared ALU mux input for shifts

---
 wally-pipelined/src/ieu/alu.sv     |  5 ++---
 wally-pipelined/src/ieu/shifter.sv | 18 +++++++-----------
 2 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index 1d49bb40..a2aa1a44 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -69,13 +69,12 @@ module alu #(parameter WIDTH=32) (
   // Select appropriate ALU Result
   assign ALUFunct = Funct3 & {3{ALUOp}}; // Force ALUFunct to 0 to Add when ALUOp = 0
   always_comb
-    case (ALUFunct)
+    casez (ALUFunct)
       3'b000: FullResult = Sum;       // add or sub
-      3'b001: FullResult = Shift;     // sll
+      3'b?01: FullResult = Shift;     // sll, sra, or srl
       3'b010: FullResult = SLT;       // slt
       3'b011: FullResult = SLTU;      // sltu
       3'b100: FullResult = A ^ B;     // xor
-      3'b101: FullResult = Shift;     // sra or srl
       3'b110: FullResult = A | B;     // or 
       3'b111: FullResult = A & B;     // and
     endcase
diff --git a/wally-pipelined/src/ieu/shifter.sv b/wally-pipelined/src/ieu/shifter.sv
index de7377a7..fc170e75 100644
--- a/wally-pipelined/src/ieu/shifter.sv
+++ b/wally-pipelined/src/ieu/shifter.sv
@@ -27,20 +27,16 @@
 
 module shifter (
   input  logic [`XLEN-1:0] a,
-  input  logic [5:0]       amt,
+  input  logic [`LOG_XLEN-1:0]       amt,
   input  logic             right, arith, w64,
   output logic [`XLEN-1:0] y);
 
-  localparam BITS = $clog2(`XLEN);
-
   logic [2*`XLEN-2:0]      z, zshift;
-  logic [BITS-1:0]         amttrunc, offset;
+  logic [`LOG_XLEN-1:0]    amttrunc, offset;
 
-  // The best shifter architecture differs based on `XLEN.
-  // for RV32, only 32-bit shifts are needed.  These are 
-  // most efficiently implemented with a funnel shifter.  
-  // For RV64, 32 and 64-bit shifts are needed, with sign
-  // extension.
+  // Handle left and right shifts with a funnel shifter.
+  // For RV32, only 32-bit shifts are needed.   
+  // For RV64, 32 and 64-bit shifts are needed, with sign extension.
 
   // funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong)
   generate
@@ -50,7 +46,7 @@ module shifter (
           if (arith) z = {{31{a[31]}}, a};
           else       z = {31'b0, a};
         else         z = {a, 31'b0};
-      assign amttrunc = amt[4:0]; // shift amount
+      assign amttrunc = amt; // shift amount
     end else begin:shifter  // RV64
       always_comb  // funnel mux
         if (w64) begin // 32-bit shifts
@@ -64,7 +60,7 @@ module shifter (
             else       z = {63'b0, a};
           else         z = {a, 63'b0};         
         end
-      assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt[5:0]; // 32 or 64-bit shift
+      assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt; // 32 or 64-bit shift
     end
   endgenerate
 

From 7e026f3e78f20d1d64237c983398eca3ae8f06a6 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 10:21:17 -0800
Subject: [PATCH 53/95] Simplified Shifter Right input

---
 wally-pipelined/src/ieu/alu.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index a2aa1a44..0558cbe1 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -51,8 +51,8 @@ module alu #(parameter WIDTH=32) (
   assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
   // Shifts
-  assign Right = (Funct3[2:0] == 3'b101); // sra or srl
-  shifter sh(A, B[5:0], Right, SubArith, W64, Shift);
+  assign Right = Funct3[2]; // sra or srl
+  shifter sh(A, B[`LOG_XLEN-1:0], Right, SubArith, W64, Shift);
   
   // condition code flags based on add/subtract output
   // Overflow occurs when the numbers being added have the same sign 

From 721d0b5bcf59a48047512fc85091a3bbd8f11f55 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 10:25:40 -0800
Subject: [PATCH 54/95] Simplified shifter right input

---
 wally-pipelined/src/ieu/alu.sv     |  6 ++---
 wally-pipelined/src/ieu/shifter.sv | 42 +++++++++++++++---------------
 2 files changed, 23 insertions(+), 25 deletions(-)

diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index 0558cbe1..827aeb8a 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -33,7 +33,6 @@ module alu #(parameter WIDTH=32) (
   output logic [WIDTH-1:0] Sum);
 
   logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
-  logic        Right;
   logic        Carry, Neg;
   logic        LT, LTU;
   logic        Overflow;
@@ -51,9 +50,8 @@ module alu #(parameter WIDTH=32) (
   assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
   
   // Shifts
-  assign Right = Funct3[2]; // sra or srl
-  shifter sh(A, B[`LOG_XLEN-1:0], Right, SubArith, W64, Shift);
-  
+  shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
+
   // condition code flags based on add/subtract output
   // Overflow occurs when the numbers being added have the same sign 
   // and the result has the opposite sign
diff --git a/wally-pipelined/src/ieu/shifter.sv b/wally-pipelined/src/ieu/shifter.sv
index fc170e75..232f7241 100644
--- a/wally-pipelined/src/ieu/shifter.sv
+++ b/wally-pipelined/src/ieu/shifter.sv
@@ -26,10 +26,10 @@
 `include "wally-config.vh"
 
 module shifter (
-  input  logic [`XLEN-1:0] a,
-  input  logic [`LOG_XLEN-1:0]       amt,
-  input  logic             right, arith, w64,
-  output logic [`XLEN-1:0] y);
+  input  logic [`XLEN-1:0]     A,
+  input  logic [`LOG_XLEN-1:0] Amt,
+  input  logic                 Right, Arith, W64,
+  output logic [`XLEN-1:0]     Y);
 
   logic [2*`XLEN-2:0]      z, zshift;
   logic [`LOG_XLEN-1:0]    amttrunc, offset;
@@ -42,34 +42,34 @@ module shifter (
   generate
     if (`XLEN==32) begin:shifter // RV32
       always_comb  // funnel mux
-        if (right) 
-          if (arith) z = {{31{a[31]}}, a};
-          else       z = {31'b0, a};
-        else         z = {a, 31'b0};
-      assign amttrunc = amt; // shift amount
+        if (Right) 
+          if (Arith) z = {{31{A[31]}}, A};
+          else       z = {31'b0, A};
+        else         z = {A, 31'b0};
+      assign amttrunc = Amt; // shift amount
     end else begin:shifter  // RV64
       always_comb  // funnel mux
-        if (w64) begin // 32-bit shifts
-          if (right)
-            if (arith) z = {64'b0, {31{a[31]}}, a[31:0]};
-            else       z = {95'b0, a[31:0]};
-          else         z = {32'b0, a[31:0], 63'b0};
+        if (W64) begin // 32-bit shifts
+          if (Right)
+            if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]};
+            else       z = {95'b0, A[31:0]};
+          else         z = {32'b0, A[31:0], 63'b0};
         end else begin
-          if (right)
-            if (arith) z = {{63{a[63]}}, a};
-            else       z = {63'b0, a};
-          else         z = {a, 63'b0};         
+          if (Right)
+            if (Arith) z = {{63{A[63]}}, A};
+            else       z = {63'b0, A};
+          else         z = {A, 63'b0};         
         end
-      assign amttrunc = w64 ? {1'b0, amt[4:0]} : amt; // 32 or 64-bit shift
+      assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32 or 64-bit shift
     end
   endgenerate
 
   // opposite offset for right shfits
-  assign offset = right ? amttrunc : ~amttrunc;
+  assign offset = Right ? amttrunc : ~amttrunc;
   
   // funnel operation
   assign zshift = z >> offset;
-  assign y = zshift[`XLEN-1:0];    
+  assign Y = zshift[`XLEN-1:0];    
 endmodule
 
 

From 67577d7c91ffaf574e96cdb28aee0aadf0ba813b Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 21:26:00 -0800
Subject: [PATCH 55/95] Renamed RD1D to R1D, etc.

---
 wally-pipelined/src/ieu/alu.sv      |  8 ++++----
 wally-pipelined/src/ieu/datapath.sv | 14 +++++++-------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/wally-pipelined/src/ieu/alu.sv b/wally-pipelined/src/ieu/alu.sv
index 827aeb8a..a93ebd29 100644
--- a/wally-pipelined/src/ieu/alu.sv
+++ b/wally-pipelined/src/ieu/alu.sv
@@ -52,10 +52,10 @@ module alu #(parameter WIDTH=32) (
   // Shifts
   shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
 
-  // condition code flags based on add/subtract output
-  // Overflow occurs when the numbers being added have the same sign 
-  // and the result has the opposite sign
-  assign Overflow = (A[WIDTH-1] ~^ CondInvB[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
+  // condition code flags based on subtract output
+  // Overflow occurs when the numbers being subtracted have the opposite sign 
+  // and the result has the opposite sign of A
+  assign Overflow = (A[WIDTH-1] ^ B[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
   assign Neg  = Sum[WIDTH-1];
   assign LT = Neg ^ Overflow;
   assign LTU = ~Carry;
diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv
index c36077d2..9111a61f 100644
--- a/wally-pipelined/src/ieu/datapath.sv
+++ b/wally-pipelined/src/ieu/datapath.sv
@@ -66,11 +66,11 @@ module datapath (
 
   // Fetch stage signals
   // Decode stage signals
-  logic [`XLEN-1:0] RD1D, RD2D;
+  logic [`XLEN-1:0] R1D, R2D;
   logic [`XLEN-1:0] ExtImmD;
   logic [4:0]      RdD;
   // Execute stage signals
-  logic [`XLEN-1:0] RD1E, RD2E;
+  logic [`XLEN-1:0] R1E, R2E;
   logic [`XLEN-1:0] ExtImmE;
 
   // logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, SrcAE2, SrcBE2; // *** MAde forwardedsrcae an output to get rid of a mux in the critical path.
@@ -91,19 +91,19 @@ module datapath (
   assign Rs1D      = InstrD[19:15];
   assign Rs2D      = InstrD[24:20];
   assign RdD       = InstrD[11:7];
-  regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, WriteDataW, RD1D, RD2D);
+  regfile regf(clk, reset, RegWriteW, Rs1D, Rs2D, RdW, WriteDataW, R1D, R2D);
   extend ext(.InstrD(InstrD[31:7]), .ImmSrcD, .ExtImmD);
  
   // Execute stage pipeline register and logic
-  flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, RD1D, RD1E);
-  flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, RD2D, RD2E);
+  flopenrc #(`XLEN) RD1EReg(clk, reset, FlushE, ~StallE, R1D, R1E);
+  flopenrc #(`XLEN) RD2EReg(clk, reset, FlushE, ~StallE, R2D, R2E);
   flopenrc #(`XLEN) ExtImmEReg(clk, reset, FlushE, ~StallE, ExtImmD, ExtImmE);
   flopenrc #(5)     Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E);
   flopenrc #(5)     Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E);
   flopenrc #(5)     RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE);
 	
-  mux3  #(`XLEN)  faemux(RD1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);
-  mux3  #(`XLEN)  fbemux(RD2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
+  mux3  #(`XLEN)  faemux(R1E, WriteDataW, ResultM, ForwardAE, ForwardedSrcAE);
+  mux3  #(`XLEN)  fbemux(R2E, WriteDataW, ResultM, ForwardBE, ForwardedSrcBE);
   comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE);
   mux2  #(`XLEN)  srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE);
   mux2  #(`XLEN)  srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE);

From 406f129bedd9a9dc1a1830a5d5cbaa473d1c8098 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sat, 18 Dec 2021 22:08:23 -0800
Subject: [PATCH 56/95] Controller fix

---
 wally-pipelined/src/ieu/controller.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 907aa650..94f3d65c 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -173,7 +173,7 @@ module controller(
   // ALU Decoding
   assign sltD = (Funct3D == 3'b010);
   assign sltuD = (Funct3D == 3'b011);
-  assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);
+  assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);  // OpD[5] needed; ***explain why
   assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
   assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
   assign ALUControlD = {W64D, SubArithD, ALUOpD};

From f201af4bb7720b0344fe256ea9cf0ce148b17790 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Dec 2021 11:49:15 -0800
Subject: [PATCH 57/95] Renamed zero to eq in flag generation

---
 wally-pipelined/src/ieu/comparator.sv | 6 +++---
 wally-pipelined/src/ieu/controller.sv | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/wally-pipelined/src/ieu/comparator.sv b/wally-pipelined/src/ieu/comparator.sv
index 14117274..0c161d6d 100644
--- a/wally-pipelined/src/ieu/comparator.sv
+++ b/wally-pipelined/src/ieu/comparator.sv
@@ -30,7 +30,7 @@ module comparator #(parameter WIDTH=32) (
   output logic [2:0]       flags);
 
   logic [WIDTH-1:0] bbar, diff;
-  logic             carry, zero, neg, overflow, lt, ltu;
+  logic             carry, eq, neg, overflow, lt, ltu;
 
   // NOTE: This can be replaced by some faster logic optimized
   // to just compute flags and not the difference.
@@ -40,13 +40,13 @@ module comparator #(parameter WIDTH=32) (
   assign {carry, diff} = a + bbar + 1;
 
   // condition code flags based on add/subtract output
-  assign zero = (diff == 0);
+  assign eq = (diff == 0);
   assign neg  = diff[WIDTH-1];
   // overflow occurs when the numbers being subtracted have the opposite sign 
   // and the result has the opposite sign fron the first
   assign overflow = (a[WIDTH-1] ^ b[WIDTH-1]) & (a[WIDTH-1] ^ diff[WIDTH-1]);
   assign lt = neg ^ overflow;
   assign ltu = ~carry;
-  assign flags = {zero, lt, ltu};
+  assign flags = {eq, lt, ltu};
 endmodule
 
diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index 94f3d65c..b081d40f 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -97,7 +97,7 @@ module controller(
   logic        SubArithD;
   logic        subD, sraD, sltD, sltuD;
   logic        BranchTakenE;
-  logic        zeroE, ltE, ltuE;
+  logic        eqE, ltE, ltuE;
   logic        unused;
 	logic        BranchFlagE;
   logic        IEURegWriteE;
@@ -202,8 +202,8 @@ module controller(
                            {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MulDivE, AtomicE, InvalidateICacheE, FlushDCacheE, InstrValidE});
 
   // Branch Logic
-  assign {zeroE, ltE, ltuE} = FlagsE;
-  mux4 #(1) branchflagmux(zeroE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
+  assign {eqE, ltE, ltuE} = FlagsE;
+  mux4 #(1) branchflagmux(eqE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
   assign BranchTakenE = BranchFlagE ^ Funct3E[0];
     
   assign PCSrcE = JumpE | BranchE & BranchTakenE;

From 1126135b806537e463e38bccdf46d67de246fe0a Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 13:53:02 -0600
Subject: [PATCH 58/95] minro change. comments about needed changes in dcache.

---
 wally-pipelined/regression/wave.do     | 302 ++++++++++++-------------
 wally-pipelined/src/cache/dcache.sv    |   1 +
 wally-pipelined/src/cache/dcachefsm.sv |   5 +-
 3 files changed, 150 insertions(+), 158 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index e8c76de0..6a87625b 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -5,10 +5,9 @@ add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/test
 add wave -noupdate /testbench/memfilename
 add wave -noupdate /testbench/dut/hart/SATP_REGW
-add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/FunctionName/FunctionName
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
-add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
@@ -16,41 +15,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
 add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
 add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
-add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
+add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
+add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
 add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@@ -173,91 +172,83 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
-add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/fsm1/CURRENT_STATE
-add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/N
-add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/D
-add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/Q
-add wave -noupdate -group divider /testbench/dut/hart/mdu/genblk1/div/rem0
-add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
-add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextIndexF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/SavePC
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/UnalignedSelect
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
+add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/WayHit
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/VictimWay
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
 add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
 add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
@@ -279,7 +270,7 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
-add wave -noupdate -group AHB /testbench/dut/hart/ebu/StallW
+add wave -noupdate -expand -group lsu /testbench/dut/hart/hzu/LSUStall
 add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
@@ -375,17 +366,17 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testb
 add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushAdrFlag
 add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
 add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
@@ -421,23 +412,23 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
 add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
-add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
-add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
-add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
+add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
 add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
+add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
+add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
 add wave -noupdate /testbench/dut/hart/lsu/dcache/VAdr
 add wave -noupdate /testbench/dut/hart/lsu/dcache/MemPAdrM
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
@@ -518,7 +509,6 @@ add wave -noupdate /testbench/dut/hart/TrapM
 add wave -noupdate /testbench/dut/hart/ifu/icache/CompressedF
 add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
 add wave -noupdate /testbench/dut/hart/ifu/PCPFmmu
-add wave -noupdate /testbench/dut/hart/ifu/PCPF
 add wave -noupdate /testbench/dut/hart/ifu/PCF
 add wave -noupdate /testbench/dut/hart/ifu/immu/Translate
 add wave -noupdate /testbench/dut/hart/ifu/icache/FinalInstrRawF
@@ -528,8 +518,8 @@ add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
 add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF
 add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {122378 ns} 0}
-quietly wave cursor active 1
+WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {44117 ns} 0}
+quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
 configure wave -justifyvalue left
@@ -544,4 +534,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {122227 ns} {122479 ns}
+WaveRestoreZoom {43912 ns} {44304 ns}
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index b546a82b..258337f8 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -150,6 +150,7 @@ module dcache
   AdrSelMux(.d0(IEUAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+		//.d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d3(FlushAdr),
 	    .s(SelAdrM),
 	    .y(RAdr));
diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index 63e712f1..f6975758 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -108,7 +108,7 @@ module dcachefsm
 					   STATE_PTW_READ_MISS_EVICT_DIRTY,		
 					   STATE_PTW_READ_MISS_READ_WORD,
 					   STATE_PTW_READ_MISS_READ_WORD_DELAY,
-					   STATE_PTW_ACCESS_AFTER_WALK,		
+					   STATE_PTW_ACCESS_AFTER_WALK,		// dead state remove
 
 					   STATE_UNCACHED_WRITE,
 					   STATE_UNCACHED_WRITE_DONE,
@@ -623,7 +623,8 @@ module dcachefsm
 		CommittedM = 1'b1;
 		NextState = STATE_READY;
 		
-		
+		/// *** BUG BUG BUG missing AMO states.
+
 		// read hit valid cached
 		if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
 		  DCacheStall = 1'b0;

From cd3c1032b7e64bb77a78ee26650afb70e7f45dbd Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 13:55:57 -0600
Subject: [PATCH 59/95] Adds FSM to LSU which will handle the interactions
 between the hptw and dcache.  This will dramatically simplify the dcache by
 removing all walker states.

---
 wally-pipelined/src/lsu/lsu.sv | 101 +++++++++++++++++++++++++++++++++
 1 file changed, 101 insertions(+)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index b01ee6fa..48b1a56e 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -129,6 +129,107 @@ module lsu
 
   assign AnyCPUReqM = (|MemRWM)  | (|AtomicM);
 
+
+  typedef enum {STATE_T0_READY,
+				STATE_T0_REPLAY,
+				STATE_T0_FAULT_REPLAY,				
+				STATE_T3_DTLB_MISS,
+				STATE_T4_ITLB_MISS,
+				STATE_T5_ITLB_MISS,
+				STATE_T7_DITLB_MISS} statetype;
+
+  statetype CurrState, NextState;
+  logic 	   InterlockStall;
+  logic SelReplayCPURequest;
+  logic SelPTW2;
+  logic WalkerInstrPageFaultRaw;
+  
+  
+  always_ff @(posedge clk)
+    if (reset)    CurrState <= #1 STATE_T0_READY;
+    else CurrState <= #1 NextState;
+
+  always_comb begin
+	case(CurrState)
+	  STATE_T0_READY: begin
+		if(~ITLBMissF & DTLBMissM & AnyCPUReqM) begin
+		  NextState = STATE_T3_DTLB_MISS;
+		end
+		else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) begin
+		  NextState = STATE_T4_ITLB_MISS;
+		end
+		else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) begin
+		  NextState = STATE_T5_ITLB_MISS;
+		end
+		else if(ITLBMissF & DTLBMissM & AnyCPUReqM) begin
+		  NextState = STATE_T7_DITLB_MISS;
+		end else begin
+		  NextState = STATE_T0_READY;
+		end
+	  end
+	  STATE_T0_REPLAY: begin
+		if(DCacheStall) begin
+		  NextState = STATE_T0_REPLAY;
+		end else begin
+		  NextState = STATE_T0_READY;
+		end
+	  end
+	  STATE_T3_DTLB_MISS: begin
+		if(WalkerLoadPageFaultM | WalkerStorePageFaultM) begin
+		  NextState = STATE_T0_READY;
+		end else if(DTLBWriteM) begin
+		  NextState = STATE_T0_REPLAY;
+		end else begin
+		  NextState = STATE_T3_DTLB_MISS;
+		end
+	  end
+	  STATE_T4_ITLB_MISS: begin
+		if(WalkerInstrPageFaultRaw | ITLBWriteF) begin
+		  NextState = STATE_T0_READY;
+		end else begin
+		  NextState = STATE_T4_ITLB_MISS;
+		end
+	  end
+	  STATE_T5_ITLB_MISS: begin
+		if(ITLBWriteF) begin
+		  NextState = STATE_T0_REPLAY;
+		end else if(WalkerInstrPageFaultRaw) begin
+		  NextState = STATE_T0_FAULT_REPLAY;
+		end else begin
+		  NextState = STATE_T5_ITLB_MISS;
+		end
+	  end
+	  STATE_T0_FAULT_REPLAY: begin
+		if(DCacheStall) begin
+		  NextState = STATE_T0_FAULT_REPLAY;
+		end else begin
+		  NextState = STATE_T0_READY;
+		end
+	  end
+	  STATE_T7_DITLB_MISS: begin
+		if(WalkerStorePageFaultM | WalkerLoadPageFaultM) begin
+		  NextState = STATE_T0_READY;
+		end else if(DTLBWriteM) begin
+		  NextState = STATE_T5_ITLB_MISS;
+		end else begin
+		  NextState = STATE_T7_DITLB_MISS;
+		end
+	  end
+	  default: begin
+		NextState = STATE_T0_READY;
+	  end
+	endcase
+  end // always_comb
+
+  // signal to CPU it needs to wait on HPTW.
+  assign InterlockStall = (NextState != STATE_T0_READY) | (NextState != STATE_T0_FAULT_REPLAY) | (NextState != STATE_T0_READY);
+  // When replaying CPU memory request after PTW select the IEUAdrM for correct address.
+  assign SelReplayCPURequest = NextState == STATE_T0_READY;
+  assign SelPTW2 = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
+				  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
+  
+  
+
   flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, MemAdrM);
 
   // *** add generate to conditionally create hptw, lsuArb, and mmu

From 225cd5a1140d2fd49abdbbdc78560ce1efb6579a Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 14:00:30 -0600
Subject: [PATCH 60/95] Renamed MemAdrM to IEUAdrM.  This will free the name
 MemAdrm for use in the DCache.

---
 fpga/constraints/debug2.xdc                     |  2 +-
 wally-pipelined/regression/linux-wave.do        |  2 +-
 wally-pipelined/regression/wave.do              |  2 +-
 wally-pipelined/src/lsu/lsu.sv                  | 12 ++++++------
 wally-pipelined/src/lsu/lsuArb.sv               |  8 ++++----
 wally-pipelined/src/mmu/hptw.sv                 |  4 ++--
 wally-pipelined/src/privileged/privileged.sv    |  4 ++--
 wally-pipelined/src/privileged/trap.sv          | 10 +++++-----
 wally-pipelined/src/wally/wallypipelinedhart.sv |  6 +++---
 9 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index f026114b..67f6ba5e 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -49,7 +49,7 @@ connect_debug_port u_ila_0/probe7 [get_nets [list {wallypipelinedsoc/hart/PCM[0]
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe8]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
-connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/MemAdrM[0]} {wallypipelinedsoc/hart/MemAdrM[1]} {wallypipelinedsoc/hart/MemAdrM[2]} {wallypipelinedsoc/hart/MemAdrM[3]} {wallypipelinedsoc/hart/MemAdrM[4]} {wallypipelinedsoc/hart/MemAdrM[5]} {wallypipelinedsoc/hart/MemAdrM[6]} {wallypipelinedsoc/hart/MemAdrM[7]} {wallypipelinedsoc/hart/MemAdrM[8]} {wallypipelinedsoc/hart/MemAdrM[9]} {wallypipelinedsoc/hart/MemAdrM[10]} {wallypipelinedsoc/hart/MemAdrM[11]} {wallypipelinedsoc/hart/MemAdrM[12]} {wallypipelinedsoc/hart/MemAdrM[13]} {wallypipelinedsoc/hart/MemAdrM[14]} {wallypipelinedsoc/hart/MemAdrM[15]} {wallypipelinedsoc/hart/MemAdrM[16]} {wallypipelinedsoc/hart/MemAdrM[17]} {wallypipelinedsoc/hart/MemAdrM[18]} {wallypipelinedsoc/hart/MemAdrM[19]} {wallypipelinedsoc/hart/MemAdrM[20]} {wallypipelinedsoc/hart/MemAdrM[21]} {wallypipelinedsoc/hart/MemAdrM[22]} {wallypipelinedsoc/hart/MemAdrM[23]} {wallypipelinedsoc/hart/MemAdrM[24]} {wallypipelinedsoc/hart/MemAdrM[25]} {wallypipelinedsoc/hart/MemAdrM[26]} {wallypipelinedsoc/hart/MemAdrM[27]} {wallypipelinedsoc/hart/MemAdrM[28]} {wallypipelinedsoc/hart/MemAdrM[29]} {wallypipelinedsoc/hart/MemAdrM[30]} {wallypipelinedsoc/hart/MemAdrM[31]} {wallypipelinedsoc/hart/MemAdrM[32]} {wallypipelinedsoc/hart/MemAdrM[33]} {wallypipelinedsoc/hart/MemAdrM[34]} {wallypipelinedsoc/hart/MemAdrM[35]} {wallypipelinedsoc/hart/MemAdrM[36]} {wallypipelinedsoc/hart/MemAdrM[37]} {wallypipelinedsoc/hart/MemAdrM[38]} {wallypipelinedsoc/hart/MemAdrM[39]} {wallypipelinedsoc/hart/MemAdrM[40]} {wallypipelinedsoc/hart/MemAdrM[41]} {wallypipelinedsoc/hart/MemAdrM[42]} {wallypipelinedsoc/hart/MemAdrM[43]} {wallypipelinedsoc/hart/MemAdrM[44]} {wallypipelinedsoc/hart/MemAdrM[45]} {wallypipelinedsoc/hart/MemAdrM[46]} {wallypipelinedsoc/hart/MemAdrM[47]} {wallypipelinedsoc/hart/MemAdrM[48]} {wallypipelinedsoc/hart/MemAdrM[49]} {wallypipelinedsoc/hart/MemAdrM[50]} {wallypipelinedsoc/hart/MemAdrM[51]} {wallypipelinedsoc/hart/MemAdrM[52]} {wallypipelinedsoc/hart/MemAdrM[53]} {wallypipelinedsoc/hart/MemAdrM[54]} {wallypipelinedsoc/hart/MemAdrM[55]} {wallypipelinedsoc/hart/MemAdrM[56]} {wallypipelinedsoc/hart/MemAdrM[57]} {wallypipelinedsoc/hart/MemAdrM[58]} {wallypipelinedsoc/hart/MemAdrM[59]} {wallypipelinedsoc/hart/MemAdrM[60]} {wallypipelinedsoc/hart/MemAdrM[61]} {wallypipelinedsoc/hart/MemAdrM[62]} {wallypipelinedsoc/hart/MemAdrM[63]} ]]
+connect_debug_port u_ila_0/probe8 [get_nets [list {wallypipelinedsoc/hart/IEUAdrM[0]} {wallypipelinedsoc/hart/IEUAdrM[1]} {wallypipelinedsoc/hart/IEUAdrM[2]} {wallypipelinedsoc/hart/IEUAdrM[3]} {wallypipelinedsoc/hart/IEUAdrM[4]} {wallypipelinedsoc/hart/IEUAdrM[5]} {wallypipelinedsoc/hart/IEUAdrM[6]} {wallypipelinedsoc/hart/IEUAdrM[7]} {wallypipelinedsoc/hart/IEUAdrM[8]} {wallypipelinedsoc/hart/IEUAdrM[9]} {wallypipelinedsoc/hart/IEUAdrM[10]} {wallypipelinedsoc/hart/IEUAdrM[11]} {wallypipelinedsoc/hart/IEUAdrM[12]} {wallypipelinedsoc/hart/IEUAdrM[13]} {wallypipelinedsoc/hart/IEUAdrM[14]} {wallypipelinedsoc/hart/IEUAdrM[15]} {wallypipelinedsoc/hart/IEUAdrM[16]} {wallypipelinedsoc/hart/IEUAdrM[17]} {wallypipelinedsoc/hart/IEUAdrM[18]} {wallypipelinedsoc/hart/IEUAdrM[19]} {wallypipelinedsoc/hart/IEUAdrM[20]} {wallypipelinedsoc/hart/IEUAdrM[21]} {wallypipelinedsoc/hart/IEUAdrM[22]} {wallypipelinedsoc/hart/IEUAdrM[23]} {wallypipelinedsoc/hart/IEUAdrM[24]} {wallypipelinedsoc/hart/IEUAdrM[25]} {wallypipelinedsoc/hart/IEUAdrM[26]} {wallypipelinedsoc/hart/IEUAdrM[27]} {wallypipelinedsoc/hart/IEUAdrM[28]} {wallypipelinedsoc/hart/IEUAdrM[29]} {wallypipelinedsoc/hart/IEUAdrM[30]} {wallypipelinedsoc/hart/IEUAdrM[31]} {wallypipelinedsoc/hart/IEUAdrM[32]} {wallypipelinedsoc/hart/IEUAdrM[33]} {wallypipelinedsoc/hart/IEUAdrM[34]} {wallypipelinedsoc/hart/IEUAdrM[35]} {wallypipelinedsoc/hart/IEUAdrM[36]} {wallypipelinedsoc/hart/IEUAdrM[37]} {wallypipelinedsoc/hart/IEUAdrM[38]} {wallypipelinedsoc/hart/IEUAdrM[39]} {wallypipelinedsoc/hart/IEUAdrM[40]} {wallypipelinedsoc/hart/IEUAdrM[41]} {wallypipelinedsoc/hart/IEUAdrM[42]} {wallypipelinedsoc/hart/IEUAdrM[43]} {wallypipelinedsoc/hart/IEUAdrM[44]} {wallypipelinedsoc/hart/IEUAdrM[45]} {wallypipelinedsoc/hart/IEUAdrM[46]} {wallypipelinedsoc/hart/IEUAdrM[47]} {wallypipelinedsoc/hart/IEUAdrM[48]} {wallypipelinedsoc/hart/IEUAdrM[49]} {wallypipelinedsoc/hart/IEUAdrM[50]} {wallypipelinedsoc/hart/IEUAdrM[51]} {wallypipelinedsoc/hart/IEUAdrM[52]} {wallypipelinedsoc/hart/IEUAdrM[53]} {wallypipelinedsoc/hart/IEUAdrM[54]} {wallypipelinedsoc/hart/IEUAdrM[55]} {wallypipelinedsoc/hart/IEUAdrM[56]} {wallypipelinedsoc/hart/IEUAdrM[57]} {wallypipelinedsoc/hart/IEUAdrM[58]} {wallypipelinedsoc/hart/IEUAdrM[59]} {wallypipelinedsoc/hart/IEUAdrM[60]} {wallypipelinedsoc/hart/IEUAdrM[61]} {wallypipelinedsoc/hart/IEUAdrM[62]} {wallypipelinedsoc/hart/IEUAdrM[63]} ]]
 create_debug_port u_ila_0 probe
 set_property port_width 32 [get_debug_ports u_ila_0/probe9]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index ff0b82be..4bf8bf7e 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -75,7 +75,7 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
 add wave -noupdate -expand -group {Memory Stage} /testbench/textM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
 add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW
 add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW
 add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 6a87625b..71a5b715 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -12,7 +12,7 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/I
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
+add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
 add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
 add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
 add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 48b1a56e..27fb4ab7 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -50,7 +50,7 @@ module lsu
 
    // address and write data
    input  logic [`XLEN-1:0]    IEUAdrE,
-   output logic [`XLEN-1:0]    MemAdrM,
+   output logic [`XLEN-1:0]    IEUAdrM,
    input  logic [`XLEN-1:0]    WriteDataM, 
    output logic [`XLEN-1:0]    ReadDataM,
 
@@ -230,7 +230,7 @@ module lsu
   
   
 
-  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, MemAdrM);
+  flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
 
   // *** add generate to conditionally create hptw, lsuArb, and mmu
   // based on `MEM_VIRTMEM
@@ -238,7 +238,7 @@ module lsu
 	    .reset(reset),
 	    .SATP_REGW(SATP_REGW),
 	    .PCF(PCF),
-	    .MemAdrM(MemAdrM),
+	    .IEUAdrM(IEUAdrM),
 	    .ITLBMissF(ITLBMissF & ~PendingInterruptM),
 	    .DTLBMissM(DTLBMissM & ~PendingInterruptM),
 	    .MemRWM(MemRWM),
@@ -272,7 +272,7 @@ module lsu
 		 .MemRWM(MemRWM),
 		 .Funct3M(Funct3M),
 		 .AtomicM(AtomicM),
-		 .MemAdrM(MemAdrM),
+		 .IEUAdrM(IEUAdrM),
 		 .IEUAdrE(IEUAdrE[11:0]),		 
 		 .CommittedM(CommittedM),
 		 .PendingInterruptM(PendingInterruptM),		
@@ -295,7 +295,7 @@ module lsu
   dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
        .PrivilegeModeW, .DisableTranslation(DisableTranslation),
        .PAdr(MemPAdrMtoDCache),
-       .VAdr(MemAdrM),
+       .VAdr(IEUAdrM),
        .Size(Funct3MtoDCache[1:0]),
        .PTE(PTE),
        .PageTypeWriteVal(PageType),
@@ -356,7 +356,7 @@ module lsu
 		.AtomicM(AtomicMtoDCache),
 		.IEUAdrE(MemAdrEtoDCache),
 		.MemPAdrM(MemPAdrM),
-		.VAdr(MemAdrM[11:0]),		
+		.VAdr(IEUAdrM[11:0]),		
 		.WriteDataM(WriteDataM),
 		.ReadDataM(ReadDataM),
 		.DCacheStall(DCacheStall),
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index 3f99ba80..498f0682 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -38,7 +38,7 @@ module lsuArb
    input logic [1:0] 	       MemRWM,
    input logic [2:0] 	       Funct3M,
    input logic [1:0] 	       AtomicM,
-   input logic [`XLEN-1:0]     MemAdrM,
+   input logic [`XLEN-1:0]     IEUAdrM,
    input logic [11:0] 	       IEUAdrE,
    input logic 		       StallW,
    input logic 		       PendingInterruptM,
@@ -67,7 +67,7 @@ module lsuArb
 
   logic [2:0] PTWSize;
   logic [`PA_BITS-1:0]  TranslationPAdrM;
-  logic [`XLEN+1:0]  MemAdrMExt;
+  logic [`XLEN+1:0]  IEUAdrMExt;
   
   // multiplex the outputs to LSU
   assign DisableTranslation = SelPTW;  // change names between SelPTW would be confusing in DTLB.
@@ -82,8 +82,8 @@ module lsuArb
   flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
 
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
-  assign MemAdrMExt = {2'b00, MemAdrM};
-  assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0]; 
+  assign IEUAdrMExt = {2'b00, IEUAdrM};
+  assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0]; 
   assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];  
   assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index b386b474..103eef21 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -34,7 +34,7 @@ module hptw
   (
    input logic 		       clk, reset,
    input logic [`XLEN-1:0]     SATP_REGW, // includes SATP.MODE to determine number of levels in page table
-   input logic [`XLEN-1:0]     PCF, MemAdrM, // addresses to translate
+   input logic [`XLEN-1:0]     PCF, IEUAdrM, // addresses to translate
    input logic 		       ITLBMissF, DTLBMissM, // TLB Miss
    input logic [1:0] 	       MemRWM, // 10 = read, 01 = write
    input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU
@@ -82,7 +82,7 @@ module hptw
 	  assign TLBMiss = (DTLBMissM | ITLBMissF);
 
       // Determine which address to translate
- 	  assign TranslationVAdr = DTLBWalk ? MemAdrM : PCF;
+ 	  assign TranslationVAdr = DTLBWalk ? IEUAdrM : PCF;
       assign CurrentPPN = PTE[`PPN_BITS+9:10];
 
 	  // State flops
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index c5bc8a45..fb6da375 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -56,7 +56,7 @@ module privileged (
   input  logic             StoreMisalignedFaultM,
   input  logic             TimerIntM, ExtIntM, SwIntM,
   input  logic [63:0]      MTIME_CLINT, MTIMECMP_CLINT,
-  input  logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM,
+  input  logic [`XLEN-1:0] InstrMisalignedAdrM, IEUAdrM,
   input  logic [4:0]       SetFflagsM,
 
   // Trap signals from pmp/pma in mmu
@@ -231,7 +231,7 @@ module privileged (
             .MIP_REGW, .MIE_REGW, .SIP_REGW, .SIE_REGW,
             .STATUS_MIE, .STATUS_SIE,
             .PCM,
-            .InstrMisalignedAdrM, .MemAdrM, 
+            .InstrMisalignedAdrM, .IEUAdrM, 
             .InstrM,
             .InstrValidM, .CommittedM,
             .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv
index 3d6ce24e..02f3f620 100644
--- a/wally-pipelined/src/privileged/trap.sv
+++ b/wally-pipelined/src/privileged/trap.sv
@@ -39,7 +39,7 @@ module trap (
   (* mark_debug = "true" *) input logic [11:0] 	   MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW,
   input logic 		   STATUS_MIE, STATUS_SIE,
   input logic [`XLEN-1:0]  PCM,
-  input logic [`XLEN-1:0]  InstrMisalignedAdrM, MemAdrM, 
+  input logic [`XLEN-1:0]  InstrMisalignedAdrM, IEUAdrM, 
   input logic [31:0] 	   InstrM,
   input logic 		   InstrValidM, CommittedM,
   output logic 		   TrapM, MTrapM, STrapM, UTrapM, RetM,
@@ -157,12 +157,12 @@ module trap (
   
   always_comb 
     if      (InstrMisalignedFaultM) NextFaultMtvalM = InstrMisalignedAdrM;
-    else if (LoadMisalignedFaultM)  NextFaultMtvalM = MemAdrM;
-    else if (StoreMisalignedFaultM) NextFaultMtvalM = MemAdrM;
+    else if (LoadMisalignedFaultM)  NextFaultMtvalM = IEUAdrM;
+    else if (StoreMisalignedFaultM) NextFaultMtvalM = IEUAdrM;
     else if (BreakpointFaultM)      NextFaultMtvalM = PCM;
     else if (InstrPageFaultM)       NextFaultMtvalM = PCM;
-    else if (LoadPageFaultM)        NextFaultMtvalM = MemAdrM;
-    else if (StorePageFaultM)       NextFaultMtvalM = MemAdrM;
+    else if (LoadPageFaultM)        NextFaultMtvalM = IEUAdrM;
+    else if (StorePageFaultM)       NextFaultMtvalM = IEUAdrM;
     else if (IllegalInstrFaultM)    NextFaultMtvalM = {{(`XLEN-32){1'b0}}, InstrM};
     else                            NextFaultMtvalM = 0;
 endmodule
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 7be5b8c6..0756b44c 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -123,7 +123,7 @@ module wallypipelinedhart (
   logic [2:0] 		    Funct3M;
   logic [`XLEN-1:0] 	    IEUAdrE;
   (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
-  (* mark_debug = "true" *) logic [`XLEN-1:0] 	    MemAdrM;  
+  (* mark_debug = "true" *) logic [`XLEN-1:0] 	    IEUAdrM;  
   (* mark_debug = "true" *) logic [`XLEN-1:0] 	    ReadDataM;
   logic [`XLEN-1:0] 	    ReadDataW;  
   logic 		    CommittedM;
@@ -245,7 +245,7 @@ module wallypipelinedhart (
 	.CommittedM, .DCacheMiss, .DCacheAccess,
 	.SquashSCW,            
 	//.DataMisalignedM(DataMisalignedM),
-	.IEUAdrE, .MemAdrM, .WriteDataM,
+	.IEUAdrE, .IEUAdrM, .WriteDataM,
 	.ReadDataM, .FlushDCacheM,
 	// connected to ahb (all stay the same)
 	.DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck,
@@ -343,7 +343,7 @@ module wallypipelinedhart (
      .LoadMisalignedFaultM, .StoreMisalignedFaultM,
      .TimerIntM, .ExtIntM, .SwIntM,
      .MTIME_CLINT, .MTIMECMP_CLINT,
-     .InstrMisalignedAdrM, .MemAdrM,
+     .InstrMisalignedAdrM, .IEUAdrM,
      .SetFflagsM,
      // Trap signals from pmp/pma in mmu
      // *** do these need to be split up into one for dmem and one for ifu?

From a445bedcd2a657ace2a873835f40a88d31e1c780 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 14:57:42 -0600
Subject: [PATCH 61/95] Modified the icache memory to read using the virtual
 (non physical) address in the PCNextF stage. This allows recovering from an
 ITLBMiss to be 1 cycle after and simplifies the hptw slightly.

---
 wally-pipelined/regression/wave.do  | 124 ++++++++++++----------------
 wally-pipelined/src/cache/icache.sv |   5 +-
 wally-pipelined/src/ifu/ifu.sv      |   1 +
 wally-pipelined/src/lsu/lsu.sv      |  15 ++--
 wally-pipelined/src/mmu/hptw.sv     |   4 +-
 5 files changed, 67 insertions(+), 82 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 71a5b715..e7970db8 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -15,31 +15,31 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
 add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
 add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
 add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
 add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
 add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
-add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
 add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
 add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
 add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
@@ -97,21 +97,21 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if
 add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
 add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
-add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
-add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrW
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
+add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
+add wave -noupdate -group {instruction pipeline} /testbench/InstrW
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
@@ -126,7 +126,6 @@ add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/IntResultW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
 add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
@@ -134,8 +133,6 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
 add wave -noupdate -group alu -divider internals
 add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
 add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
@@ -154,13 +151,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
-add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
-add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
-add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
-add wave -noupdate -expand -group PCS /testbench/PCW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/InstrD
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/hart/PCF
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/hart/PCE
+add wave -noupdate -group PCS /testbench/dut/hart/PCM
+add wave -noupdate -group PCS /testbench/PCW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcAE
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcBE
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
@@ -241,6 +237,9 @@ add wave -noupdate -expand -group icache -expand -group {fsm out and control} /t
 add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
 add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
 add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/RAdr
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
 add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
 add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
 add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
@@ -367,7 +366,6 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testb
 add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
 add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
@@ -426,9 +424,9 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group typ
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
 add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
-add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
-add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
+add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
+add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
 add wave -noupdate /testbench/dut/hart/lsu/dcache/VAdr
 add wave -noupdate /testbench/dut/hart/lsu/dcache/MemPAdrM
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
@@ -499,26 +497,12 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
-add wave -noupdate -color Gold /testbench/dut/hart/lsu/dcache/subwordread/offset0
-add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset1
-add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset2
-add wave -noupdate /testbench/dut/hart/lsu/dcache/subwordread/offset3
-add wave -noupdate /testbench/dut/hart/ExceptionM
-add wave -noupdate /testbench/dut/hart/PendingInterruptM
-add wave -noupdate /testbench/dut/hart/TrapM
-add wave -noupdate /testbench/dut/hart/ifu/icache/CompressedF
+add wave -noupdate /testbench/dut/hart/lsu/CurrState
+add wave -noupdate /testbench/dut/hart/lsu/InterlockStall
+add wave -noupdate /testbench/dut/hart/ifu/icache/PCNextF
 add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
-add wave -noupdate /testbench/dut/hart/ifu/PCPFmmu
-add wave -noupdate /testbench/dut/hart/ifu/PCF
-add wave -noupdate /testbench/dut/hart/ifu/immu/Translate
-add wave -noupdate /testbench/dut/hart/ifu/icache/FinalInstrRawF
-add wave -noupdate /testbench/dut/hart/ifu/icache/StallF
-add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheMemReadData
-add wave -noupdate /testbench/dut/hart/ifu/icache/PCTagF
-add wave -noupdate /testbench/dut/hart/ifu/icache/PCPSpillF
-add wave -noupdate /testbench/dut/hart/ifu/icache/ICacheReadEn
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {44117 ns} 0}
+WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {23208 ns} 0}
 quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
@@ -534,4 +518,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {43912 ns} {44304 ns}
+WaveRestoreZoom {23041 ns} {23377 ns}
diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 372aeaec..e3e9d6db 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -32,6 +32,7 @@ module icache
    input logic 		       StallF, 
    input logic [`PA_BITS-1:0]  PCNextF,
    input logic [`PA_BITS-1:0]  PCPF,
+   input logic [`XLEN-1:0]  PCF,
 
    input logic ExceptionM, PendingInterruptM,
    
@@ -125,7 +126,7 @@ module icache
 
   mux3 #(INDEXLEN)
   AdrSelMux(.d0(PCNextF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
-	    .d1(PCPF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+	    .d1(PCF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d2(PCPSpillF[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .s(SelAdr),
 	    .y(RAdr));
@@ -219,7 +220,7 @@ module icache
 
   // Detect if the instruction is compressed
   assign CompressedF = FinalInstrRawF[1:0] != 2'b11;
-  assign spill = PCPF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
+  assign spill = PCF[4:1] == 4'b1111 ? 1'b1 : 1'b0;
 
 
   // to compute the fetch address we need to add the bit shifted
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 8bc8a185..7c8c1501 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -168,6 +168,7 @@ module ifu (
 
   .PCNextF(PCNextFPhys),
   .PCPF(PCPFmmu),
+  .PCF,
   .WalkerInstrPageFaultF,
   .InvalidateICacheM);
   
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 27fb4ab7..09c1f28c 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -141,7 +141,6 @@ module lsu
   statetype CurrState, NextState;
   logic 	   InterlockStall;
   logic SelReplayCPURequest;
-  logic SelPTW2;
   logic WalkerInstrPageFaultRaw;
   
   
@@ -222,10 +221,13 @@ module lsu
   end // always_comb
 
   // signal to CPU it needs to wait on HPTW.
-  assign InterlockStall = (NextState != STATE_T0_READY) | (NextState != STATE_T0_FAULT_REPLAY) | (NextState != STATE_T0_READY);
+  assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
+						  (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
+						  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
+  
   // When replaying CPU memory request after PTW select the IEUAdrM for correct address.
   assign SelReplayCPURequest = NextState == STATE_T0_READY;
-  assign SelPTW2 = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
+  assign SelPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
 				  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
   
   
@@ -250,7 +252,6 @@ module lsu
 	    .DCacheStall(DCacheStall),
         .TranslationPAdr,			  
 	    .HPTWRead(HPTWRead),
-	    .SelPTW(SelPTW),
 		.HPTWStall,
 	    .AnyCPUReqM,
 	    .MemAfterIWalkDone,
@@ -258,14 +259,14 @@ module lsu
 	    .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
 	    .WalkerStorePageFaultM(WalkerStorePageFaultM));
 
-  assign LSUStall = DCacheStall | HPTWStall;
+  assign LSUStall = DCacheStall | InterlockStall;
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
   // arbiter between IEU and hptw
   lsuArb arbiter(.clk(clk),
 		 // HPTW connection
-		 .SelPTW(SelPTW),
+		 .SelPTW,
 		 .HPTWRead(HPTWRead),
 		 .TranslationPAdrE(TranslationPAdr),
 		 // CPU connection
@@ -371,7 +372,7 @@ module lsu
 		.ITLBWriteF(ITLBWriteF),
 		.ITLBMissF,
 		.MemAfterIWalkDone,
-		.SelPTW(SelPTW),
+		.SelPTW,
 		.WalkerPageFaultM(WalkerPageFaultM),
 		.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
 
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index 103eef21..cb520788 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -44,7 +44,6 @@ module hptw
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0] 	       PageType, // page type to TLBs
    output logic 	       ITLBWriteF, DTLBWriteM, // write TLB with new entry
-   output logic 	       SelPTW, // LSU Arbiter should select signals from the PTW rather than from the IEU
    output logic            HPTWStall,
    output logic [`PA_BITS-1:0] TranslationPAdr,
    output logic 	       HPTWRead, // HPTW requesting to read memory
@@ -101,7 +100,6 @@ module hptw
 	  // Enable and select signals based on states
       assign StartWalk = (WalkerState == IDLE) & TLBMiss;
 	  assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
-	  assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT) & (WalkerState != LEAF) & (WalkerState != LEAF_DELAY);
 	  assign HPTWStall = (WalkerState != IDLE) & (WalkerState != FAULT);
 	  assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
 	  assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
@@ -213,7 +211,7 @@ module hptw
 	    end
 	  endcase
     end else begin // No Virtual memory supported; tie HPTW outputs to 0
-      assign HPTWRead = 0; assign SelPTW = 0;
+      assign HPTWRead = 0;
       assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
       assign TranslationPAdr = 0; 
     end

From f4d778c2f633f6f089397f6d27d641809067745a Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 15:10:33 -0600
Subject: [PATCH 62/95] Corrected the LSU's fsm for stalling CPU.  Removed
 state from hptw fsm.

---
 wally-pipelined/src/lsu/lsu.sv  | 4 ++--
 wally-pipelined/src/mmu/hptw.sv | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 09c1f28c..65772a71 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -222,8 +222,8 @@ module lsu
 
   // signal to CPU it needs to wait on HPTW.
   assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
-						  (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
-						  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
+						  (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultF) |
+						  (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
   
   // When replaying CPU memory request after PTW select the IEUAdrM for correct address.
   assign SelReplayCPURequest = NextState == STATE_T0_READY;
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index cb520788..d2a5fa1a 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -199,7 +199,7 @@ module hptw
 //	    LEVEL0: if (ValidLeafPTE) 	NextWalkerState = LEAF;
 //				else 				NextWalkerState = FAULT;
 	    LEAF: 	if (DTLBWalk)		NextWalkerState = IDLE; // updates TLB
-		        else                NextWalkerState = LEAF_DELAY;
+		        else                NextWalkerState = IDLE;
 	    LEAF_DELAY: 				NextWalkerState = IDLE;		 // give time to allow address translation
 	    FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
  	                        else NextWalkerState = IDLE;

From e3f2a252cdbb69e20c59d431dcea284c158782a5 Mon Sep 17 00:00:00 2001
From: Katherine Parry <kparry4@gmail.com>
Date: Sun, 19 Dec 2021 13:51:46 -0800
Subject: [PATCH 63/95] fixed some small errors in FMA

---
 wally-pipelined/src/fpu/fma.sv | 171 +++++++++++----------------------
 1 file changed, 56 insertions(+), 115 deletions(-)

diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv
index 6ad3f986..a90848f5 100644
--- a/wally-pipelined/src/fpu/fma.sv
+++ b/wally-pipelined/src/fpu/fma.sv
@@ -28,6 +28,7 @@
 // `define NE   11//(`Q_SUPPORTED ? 15 : `D_SUPPORTED ? 11 : 8)
 // `define NF   52//(`Q_SUPPORTED ? 112 : `D_SUPPORTED ? 52 : 23)
 // `define XLEN 64
+`define NANPAYLOAD 1
 module fma(
     input logic                 clk,
     input logic                 reset,
@@ -117,9 +118,8 @@ module fma1(
     logic [3*`NF+6:0]   AlignedAddendInv;   // aligned addend possibly inverted
     logic [2*`NF+1:0]   ProdManKilled;      // the product's mantissa possibly killed
     logic [3*`NF+4:0]   NegProdManKilled;   // a negated ProdManKilled
-    logic [8:0]         PNormCnt, NNormCnt; // the positive and nagitive LOA results
     logic [3*`NF+6:0]   PreSum, NegPreSum;  // positive and negitve versions of the sum
-
+    logic [`NE-1:0]     XExpVal, YExpVal;   // exponent value after taking into accound denormals
     ///////////////////////////////////////////////////////////////////////////////
     // Calculate the product
     //      - When multipliying two fp numbers, add the exponents
@@ -130,7 +130,7 @@ module fma1(
    
 
    // calculate the product's exponent 
-    expadd expadd(.FmtE, .XExpE, .YExpE, .XZeroE, .YZeroE, .XDenormE, .YDenormE, 
+    expadd expadd(.FmtE, .XExpE, .YExpE, .XZeroE, .YZeroE, .XDenormE, .YDenormE, .XExpVal, .YExpVal, 
                     .Denorm, .ProdExpE);
 
     // multiplication of the mantissa's
@@ -140,7 +140,7 @@ module fma1(
     // Alignment shifter
     ///////////////////////////////////////////////////////////////////////////////
 
-    align align(.ZExpE, .ZManE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .ProdExpE, .Denorm,
+    align align(.ZExpE, .ZManE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE, .ProdExpE, .Denorm, .XExpVal, .YExpVal,
                         .AlignedAddendE, .AddendStickyE, .KillProdE);
                         
     // calculate the signs and take the opperation into account
@@ -150,9 +150,9 @@ module fma1(
     // // Addition/LZA
     // ///////////////////////////////////////////////////////////////////////////////
         
-    add add(.AlignedAddendE, .ProdManE, .PSgnE, .ZSgnEffE, .KillProdE, .AlignedAddendInv, .ProdManKilled, .NegProdManKilled, .NegSumE, .PreSum, .NegPreSum, .InvZE, .XZeroE, .YZeroE);
+    add add(.AlignedAddendE, .ProdManE, .PSgnE, .ZSgnEffE, .KillProdE, .AlignedAddendInv, .ProdManKilled, .NegSumE, .PreSum, .NegPreSum, .InvZE, .XZeroE, .YZeroE);
     
-    loa loa(.A(AlignedAddendInv+{162'b0,InvZE}), .P(ProdManKilled), .NegSumE, .NormCntE);
+    loa loa(.A(AlignedAddendInv+{162'b0,InvZE}), .P(ProdManKilled), .NormCntE);
 
     // Choose the positive sum and accompanying LZA result.
     assign SumE = NegSumE ? NegPreSum[3*`NF+5:0] : PreSum[3*`NF+5:0];
@@ -167,11 +167,11 @@ module expadd(
     input  logic [`NE-1:0]  XExpE, YExpE,  // input exponents
     input  logic            XDenormE, YDenormE,    // are the inputs denormalized
     input  logic            XZeroE, YZeroE,        // are the inputs zero
+    output logic [`NE-1:0]  XExpVal, YExpVal,      // Exponent value after taking into account denormals
     output logic [`NE-1:0]  Denorm,        // value of denormalized exponent
     output logic [`NE+1:0]  ProdExpE       // product's exponent B^(1023)NE+2
 );
 
-    logic [`NE-1:0] XExpVal, YExpVal;       // Exponent value after taking into account denormals
 
     // denormalized numbers have diffrent values depending on which precison it is.
     //      double - 1
@@ -233,6 +233,7 @@ module align(
     input logic  [`NF:0]        ZManE,      // fractions in U(0.NF) format]
     input logic                 ZDenormE,   // is the input denormal
     input logic                 XZeroE, YZeroE, ZZeroE, // is the input zero
+    input logic  [`NE-1:0]      XExpVal, YExpVal,       // Exponent value after taking into account denormals
     input logic  [`NE+1:0]      ProdExpE,       // the product's exponent
     input logic  [`NE-1:0]      Denorm,         // the biased value of a denormalized number
     output logic [3*`NF+5:0]    AlignedAddendE, // Z aligned for addition in U(NF+5.2NF+1)
@@ -254,7 +255,8 @@ module align(
     //      - positive means the product is larger, so shift Z right
     //      - Denormal numbers have a diffrent exponent value depending on the precision
     assign ZExpVal = ZDenormE ? Denorm : ZExpE;
-    assign AlignCnt = ProdExpE - {2'b0, ZExpVal} + (`NF+3);
+    // assign AlignCnt = ProdExpE - {2'b0, ZExpVal} + (`NF+3);
+    assign AlignCnt = XZeroE|YZeroE ? -1 : {2'b0, XExpVal} + {2'b0, YExpVal} - 1020+`NF - {2'b0, ZExpVal};
 
     // Defualt Addition without shifting
     //          |   54'b0    |  106'b(product)  | 2'b0 |
@@ -312,14 +314,14 @@ module add(
     input logic                 PSgnE, ZSgnEffE,// the product and modified Z signs
     input logic                 KillProdE,      // should the product be set to 0
     input logic                 XZeroE, YZeroE, // is the input zero
-    output logic [3*`NF+6:0] AlignedAddendInv,  // aligned addend possibly inverted
-    output logic [2*`NF+1:0] ProdManKilled,     // the product's mantissa possibly killed
-    output logic [3*`NF+4:0] NegProdManKilled,  // a negated ProdManKilled
+    output logic [3*`NF+6:0]    AlignedAddendInv,  // aligned addend possibly inverted
+    output logic [2*`NF+1:0]    ProdManKilled,     // the product's mantissa possibly killed
     output logic                NegSumE,        // was the sum negitive
     output logic                InvZE,          // do you invert Z
-    output logic [3*`NF+6:0]   PreSum, NegPreSum// possibly negitive sum
+    output logic [3*`NF+6:0]    PreSum, NegPreSum// possibly negitive sum
 );
 
+    logic [3*`NF+4:0] NegProdManKilled;  // a negated ProdManKilled
     ///////////////////////////////////////////////////////////////////////////////
     // Addition
     ///////////////////////////////////////////////////////////////////////////////
@@ -334,17 +336,17 @@ module add(
     // Kill the product if the product is too small to effect the addition (determined in fma1.sv)
     assign ProdManKilled = ProdManE&{2*`NF+2{~KillProdE}};
     // Negate ProdMan for LZA and the negitive sum calculation
-    assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, ~ProdManKilled&{2*`NF+2{~(XZeroE|YZeroE)}}};
+    assign NegProdManKilled = {{`NF+3{~(XZeroE|YZeroE|KillProdE)}}, ~ProdManKilled&{2*`NF+2{~(XZeroE|YZeroE|KillProdE)}}};
 
 
-    // Is the sum negitive
-    assign NegSumE = (AlignedAddendE > {54'b0, ProdManKilled, 2'b0})&InvZE; //***use this to avoid addition and final muxing???
 
     // Do the addition
     //      - calculate a positive and negitive sum in parallel
     assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0} + {{3*`NF+6{1'b0}}, InvZE};
-    assign NegPreSum = AlignedAddendE + {NegProdManKilled, 2'b0} + {{(3*`NF+3){1'b0}},~(XZeroE|YZeroE),2'b0};
+    assign NegPreSum = AlignedAddendE + {NegProdManKilled, 2'b0} + {{(3*`NF+3){1'b0}},~(XZeroE|YZeroE|KillProdE),2'b0};
      
+    // Is the sum negitive
+    assign NegSumE = PreSum[3*`NF+6];
 
 endmodule
 
@@ -352,28 +354,32 @@ endmodule
 module loa( //https://ieeexplore.ieee.org/abstract/document/930098
     input logic  [3*`NF+6:0] A,     // addend
     input logic  [2*`NF+1:0] P,     // product
-    input logic              NegSumE, // is the sum negitive
     output logic [8:0]       NormCntE   // normalization shift count for the positive result
     ); 
     
-
     logic [3*`NF+6:0] T;
-    logic [3*`NF+5:0] G;
-    logic [3*`NF+5:0] Z;
+    logic [3*`NF+6:0] G;
+    logic [3*`NF+6:0] Z;
     assign T[3*`NF+6:2*`NF+4] = A[3*`NF+6:2*`NF+4];
-    assign G[3*`NF+5:2*`NF+4] = 0;
-    assign Z[3*`NF+5:2*`NF+4] = ~A[3*`NF+5:2*`NF+4];
+    assign G[3*`NF+6:2*`NF+4] = 0;
+    assign Z[3*`NF+6:2*`NF+4] = ~A[3*`NF+6:2*`NF+4];
     assign T[2*`NF+3:2] = A[2*`NF+3:2]^P;
     assign G[2*`NF+3:2] = A[2*`NF+3:2]&P;
     assign Z[2*`NF+3:2] = ~A[2*`NF+3:2]&~P;
     assign T[1:0] = A[1:0];
     assign G[1:0] = 0;
     assign Z[1:0] = ~A[1:0];
-    
+
 
     // Apply function to determine Leading pattern
+    //      - note: the paper linked above uses the numbering system where 0 is the most significant bit
+    //f[n] = ~T[n]&T[n-1]           note: n is the MSB
+    //f[i] = (T[i+1]&(G[i]&~Z[i-1] | Z[i]&~G[i-1])) | (~T[i+1]&(Z[i]&~Z[i-1] | G[i]&~G[i-1]))
     logic [3*`NF+6:0] f;
-    assign f = NegSumE ? T^{~G[3*`NF+5:0],1'b1} : T^{~Z[3*`NF+5:0], 1'b1};
+    assign f[3*`NF+6] = ~T[3*`NF+6]&T[3*`NF+5];
+    assign f[3*`NF+5:0] = (T[3*`NF+6:1]&(G[3*`NF+5:0]&{~Z[3*`NF+4:0], 1'b0} | Z[3*`NF+5:0]&{~G[3*`NF+4:0], 1'b1})) | (~T[3*`NF+6:1]&(Z[3*`NF+5:0]&{~Z[3*`NF+4:0], 1'b0} | G[3*`NF+5:0]&{~G[3*`NF+4:0], 1'b1}));
+
+
 
     lzc lzc(.f, .NormCntE);
   
@@ -426,7 +432,7 @@ module fma2(
 
     logic [`NF-1:0]     ResultFrac; // Result fraction
     logic [`NE-1:0]     ResultExp;  // Result exponent
-    logic               ResultSgn;  // Result sign
+    logic               ResultSgn, ResultSgnTmp;  // Result sign
     logic [`NE+1:0]     SumExp;     // exponent of the normalized sum
     logic [`NE+1:0]     FullResultExp;  // ResultExp with bits to determine sign and overflow
     logic [`NF+2:0]     NormSum;        // normalized sum
@@ -464,7 +470,7 @@ module fma2(
     // round to infinity
     // round to nearest max magnitude
 
-    fmaround fmaround(.FmtM, .FrmM, .Sticky, .UfSticky, .NormSum, .AddendStickyM, .NormSumSticky, .ZZeroM, .InvZM, .ResultSgn, .SumExp,
+    fmaround fmaround(.FmtM, .FrmM, .Sticky, .UfSticky, .NormSum, .AddendStickyM, .NormSumSticky, .ZZeroM, .InvZM, .ResultSgnTmp, .SumExp,
         .CalcPlus1, .Plus1, .UfPlus1, .Minus1, .FullResultExp, .ResultFrac, .ResultExp, .Round, .Guard, .UfLSBNormSum);
 
 
@@ -476,7 +482,7 @@ module fma2(
     ///////////////////////////////////////////////////////////////////////////////
 
  
-    resultsign resultsign(.FrmM, .PSgnM, .ZSgnEffM, .Underflow, .InvZM, .NegSumM, .SumZero, .ResultSgn);
+    resultsign resultsign(.FrmM, .PSgnM, .ZSgnEffM, .Underflow, .InvZM, .NegSumM, .SumZero, .ResultSgnTmp, .ResultSgn);
 
 
 
@@ -512,11 +518,12 @@ module resultsign(
     input logic         InvZM,
     input logic         NegSumM,
     input logic         SumZero,
+    output logic        ResultSgnTmp,
     output logic        ResultSgn
 );
 
     logic ZeroSgn;
-    logic ResultSgnTmp;
+    // logic ResultSgnTmp;
 
     // Determine the sign if the sum is zero
     //      if cancelation then 0 unless round to -infinity
@@ -554,15 +561,24 @@ module resultselect(
 );
     logic [`FLEN-1:0]   XNaNResult, YNaNResult, ZNaNResult, InvalidResult, OverflowResult, KillProdResult, UnderflowResult; // possible results
 
-    assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]};
-    assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]};
-    assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]};
+    generate if(`NANPAYLOAD) begin
+        assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, XManM[`NF-2:0]} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, XManM[50:29]};
+        assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, YManM[`NF-2:0]} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, YManM[50:29]};
+        assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, ZManM[`NF-2:0]} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, ZManM[50:29]};
+    end else begin
+        assign XNaNResult = FmtM ? {XSgnM, XExpM, 1'b1, 51'b0} : {{32{1'b1}}, XSgnM, XExpM[7:0], 1'b1, 22'b0};
+        assign YNaNResult = FmtM ? {YSgnM, YExpM, 1'b1, 51'b0} : {{32{1'b1}}, YSgnM, YExpM[7:0], 1'b1, 22'b0};
+        assign ZNaNResult = FmtM ? {ZSgnEffM, ZExpM, 1'b1, 51'b0} : {{32{1'b1}}, ZSgnEffM, ZExpM[7:0], 1'b1, 22'b0};
+    end
+    endgenerate
+    
+    
     assign OverflowResult =  FmtM ? ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {ResultSgn, {`NE-1{1'b1}}, 1'b0, {`NF{1'b1}}} :
                                                                                                                           {ResultSgn, {`NE{1'b1}}, {`NF{1'b0}}} :
                                     ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} :
                                                                                                                           {{32{1'b1}}, ResultSgn, 8'hff, 23'b0};
     assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0};
-    assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - {62'b0, (Minus1&AddendStickyM) + (Plus1&AddendStickyM)}} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
+    assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - {62'b0, (Minus1&AddendStickyM)} + {62'b0, (Plus1&AddendStickyM)}} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}};
     assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {63'b0,(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}};
     assign FMAResM = XNaNM ? XNaNResult :
                         YNaNM ? YNaNResult :
@@ -579,81 +595,6 @@ module resultselect(
 
 endmodule
 
-
-// module normalize(
-//     input logic  [3*`NF+5:0]    SumM,       // the positive sum
-//     input logic  [`NE-1:0]      ZExpM,      // exponent of Z
-//     input logic  [`NE+1:0]      ProdExpM,   // X exponent + Y exponent - bias
-//     input logic  [8:0]          NormCntM,   // normalization shift count
-//     input logic                 FmtM,       // precision 1 = double 0 = single
-//     input logic                 KillProdM,  // is the product set to zero
-//     input logic                 AddendStickyM,  // the sticky bit caclulated from the aligned addend
-//     input logic                 NegSumM,    // was the sum negitive
-//     output logic [`NF+2:0]      NormSum,        // normalized sum
-//     output logic                SumZero,        // is the sum zero
-//     output logic                NormSumSticky, UfSticky,    // sticky bits
-//     output logic [`NE+1:0]      SumExp,         // exponent of the normalized sum
-//     output logic                ResultDenorm    // is the result denormalized
-// );
-//     logic [`NE+1:0]     FracLen;            // length of the fraction
-//     logic [`NE+1:0]     SumExpTmp;          // exponent of the normalized sum not taking into account denormal or zero results
-//     logic [8:0]         DenormShift;        // right shift if the result is denormalized //***change this later
-//     logic [3*`NF+5:0]   CorrSumShifted;     // the shifted sum after LZA correction
-//     logic [3*`NF+7:0]   SumShifted;         // the shifted sum before LZA correction
-//     logic [`NE+1:0]     SumExpTmpTmp;       // the exponent of the normalized sum with the `FLEN bias
-//     logic               PreResultDenorm;    // is the result denormalized - calculated before LZA corection
-//     logic               PreResultDenorm2;    // is the result denormalized - calculated before LZA corection
-//     logic               LZAPlus1;           // add one to the sum's exponent due to LZA correction
-
-//     ///////////////////////////////////////////////////////////////////////////////
-//     // Normalization
-//     ///////////////////////////////////////////////////////////////////////////////
-
-//     // Determine if the sum is zero
-//     assign SumZero = ~(|SumM);
-
-//     // determine the length of the fraction based on precision
-//     assign FracLen = FmtM ? `NF+1 : 13'd24;
-
-//     // calculate the sum's exponent
-//     assign SumExpTmpTmp = KillProdM ? {2'b0, ZExpM} : ProdExpM + -({4'b0, NormCntM} + 1 - (`NF+4)); // ****try moving this into previous stage
-//     assign SumExpTmp = FmtM ? SumExpTmpTmp : (SumExpTmpTmp-1023+127)&{`NE+2{|SumExpTmpTmp}}; // ***move this ^ the subtraction by a constant isn't simplified
-    
-//     logic SumDLTEZ, SumDGEFL, SumSLTEZ, SumSGEFL;
-//     assign SumDLTEZ = SumExpTmpTmp[`NE+1] | ~|SumExpTmpTmp;
-//     assign SumDGEFL = ($signed(SumExpTmpTmp)>=$signed(-(13'd`NF+13'd1)));
-//     assign SumSLTEZ = $signed(SumExpTmpTmp) <= $signed(13'd1023-13'd127);
-//     assign SumSGEFL = ($signed(SumExpTmpTmp)>=$signed(-13'd24+13'd1023-13'd127)) | ~|SumExpTmpTmp;
-//     assign PreResultDenorm2 = (FmtM ? SumDLTEZ : SumSLTEZ) & (FmtM ? SumDGEFL : SumSGEFL) & ~SumZero; //***make sure math good
-//     // always_comb begin
-//     //     assert (PreResultDenorm == PreResultDenorm2) else $fatal ("PreResultDenorms not equal");
-//     // end
-
-
-
-//     // Determine if the result is denormal
-//     // assign PreResultDenorm = $signed(SumExpTmp)<=0 & ($signed(SumExpTmp)>=$signed(-FracLen)) & ~SumZero;
-
-//     // Determine the shift needed for denormal results
-//     //  - if not denorm add 1 to shift out the leading 1
-//     assign DenormShift = PreResultDenorm2 ? SumExpTmp[8:0] : 1; //*** change this when changing the size of DenormShift also change to an and opperation
-//     // Normalize the sum
-//     assign SumShifted = {2'b0, SumM} << NormCntM+DenormShift; //*** fix mux's with constants in them //***NormCnt can be simplified
-//     // LZA correction
-//     assign LZAPlus1 = SumShifted[3*`NF+7];
-//     assign CorrSumShifted =  LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
-//     assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3];
-//     // Calculate the sticky bit
-//     assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | (|CorrSumShifted[136:2*`NF+3]&~FmtM);
-//     assign UfSticky = AddendStickyM | NormSumSticky;
-
-//     // Determine sum's exponent
-//     assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}};
-//     // recalculate if the result is denormalized
-//     assign ResultDenorm = PreResultDenorm2&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7];
-
-// endmodule
-
 module normalize(
     input logic  [3*`NF+5:0]    SumM,       // the positive sum
     input logic  [`NE-1:0]      ZExpM,      // exponent of Z
@@ -733,7 +674,7 @@ module normalize(
     assign LZAPlus1 = SumShifted[3*`NF+7];
     assign LZAPlus2 = SumShifted[3*`NF+8];
 	// the only possible mantissa for a plus two is all zeroes - a one has to propigate all the way through a sum. so we can leave the bottom statement alone
-    assign CorrSumShifted =  LZAPlus1 ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
+    assign CorrSumShifted =  LZAPlus1&~KillProdM ? SumShifted[3*`NF+6:1] : SumShifted[3*`NF+5:0];
     assign NormSum = CorrSumShifted[3*`NF+5:2*`NF+3];
     // Calculate the sticky bit
     assign NormSumSticky = (|CorrSumShifted[2*`NF+2:0]) | (|CorrSumShifted[136:2*`NF+3]&~FmtM);
@@ -757,7 +698,7 @@ module fmaround(
     input logic             ZZeroM,         // is Z zero
     input logic             InvZM,          // invert Z
     input logic  [`NE+1:0]  SumExp,         // exponent of the normalized sum
-    input logic             ResultSgn,      // the result's sign
+    input logic             ResultSgnTmp,      // the result's sign
     output logic            CalcPlus1, Plus1, UfPlus1, Minus1,  // do you add or subtract on from the result
     output logic [`NE+1:0]  FullResultExp,      // ResultExp with bits to determine sign and overflow
     output logic [`NF-1:0]  ResultFrac,         // Result fraction
@@ -824,8 +765,8 @@ module fmaround(
         case (FrmM)
             3'b000: CalcPlus1 = Guard & (Round | ((Sticky)&~(~Round&SubBySmallNum)) | (~Round&~(Sticky)&LSBNormSum&~SubBySmallNum));//round to nearest even
             3'b001: CalcPlus1 = 0;//round to zero
-            3'b010: CalcPlus1 = ResultSgn & ~(SubBySmallNum & ~Guard & ~Round);//round down
-            3'b011: CalcPlus1 = ~ResultSgn & ~(SubBySmallNum & ~Guard & ~Round);//round up
+            3'b010: CalcPlus1 = ResultSgnTmp & ~(SubBySmallNum & ~Guard & ~Round);//round down
+            3'b011: CalcPlus1 = ~ResultSgnTmp & ~(SubBySmallNum & ~Guard & ~Round);//round up
             3'b100: CalcPlus1 = (Guard & (Round | ((Sticky)&~(~Round&SubBySmallNum)) | (~Round&~(Sticky)&~SubBySmallNum)));//round to nearest max magnitude
             default: CalcPlus1 = 1'bx;
         endcase
@@ -833,8 +774,8 @@ module fmaround(
         case (FrmM)
             3'b000: UfCalcPlus1 = UfGuard & (UfRound | (UfSticky&UfRound|~UfSubBySmallNum) | (~Sticky&UfLSBNormSum&~UfSubBySmallNum));//round to nearest even
             3'b001: UfCalcPlus1 = 0;//round to zero
-            3'b010: UfCalcPlus1 = ResultSgn & ~(UfSubBySmallNum & ~UfGuard & ~UfRound);//round down
-            3'b011: UfCalcPlus1 = ~ResultSgn & ~(UfSubBySmallNum & ~UfGuard & ~UfRound);//round up
+            3'b010: UfCalcPlus1 = ResultSgnTmp & ~(UfSubBySmallNum & ~UfGuard & ~UfRound);//round down
+            3'b011: UfCalcPlus1 = ~ResultSgnTmp & ~(UfSubBySmallNum & ~UfGuard & ~UfRound);//round up
             3'b100: UfCalcPlus1 = (UfGuard & (UfRound | (UfSticky&~(~UfRound&UfSubBySmallNum)) | (~Sticky&~UfSubBySmallNum)));//round to nearest max magnitude
             default: UfCalcPlus1 = 1'bx;
         endcase
@@ -842,8 +783,8 @@ module fmaround(
         case (FrmM)
             3'b000: CalcMinus1 = 0;//round to nearest even
             3'b001: CalcMinus1 = SubBySmallNum & ~Guard & ~Round;//round to zero
-            3'b010: CalcMinus1 = ~ResultSgn & ~Guard & ~Round & SubBySmallNum;//round down
-            3'b011: CalcMinus1 = ResultSgn & ~Guard & ~Round & SubBySmallNum;//round up
+            3'b010: CalcMinus1 = ~ResultSgnTmp & ~Guard & ~Round & SubBySmallNum;//round down
+            3'b011: CalcMinus1 = ResultSgnTmp & ~Guard & ~Round & SubBySmallNum;//round up
             3'b100: CalcMinus1 = 0;//round to nearest max magnitude
             default: CalcMinus1 = 1'bx;
         endcase

From 9e6c9c38c0e78eae6ad768fdd0b30a10c7f09a81 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Dec 2021 13:53:45 -0800
Subject: [PATCH 64/95] ALUControl cleanup

---
 wally-pipelined/src/ieu/controller.sv | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/ieu/controller.sv b/wally-pipelined/src/ieu/controller.sv
index b081d40f..040fa018 100644
--- a/wally-pipelined/src/ieu/controller.sv
+++ b/wally-pipelined/src/ieu/controller.sv
@@ -170,10 +170,10 @@ module controller(
   assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
   assign CSRWriteD = CSRReadD & !(CSRZeroSrcD && InstrD[13]); // Don't write if setting or clearing zeros
 
-  // ALU Decoding
+  // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
   assign sltD = (Funct3D == 3'b010);
   assign sltuD = (Funct3D == 3'b011);
-  assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);  // OpD[5] needed; ***explain why
+  assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]);  // OpD[5] needed to distinguish sub from addi
   assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
   assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu
   assign ALUControlD = {W64D, SubArithD, ALUOpD};
@@ -205,12 +205,11 @@ module controller(
   assign {eqE, ltE, ltuE} = FlagsE;
   mux4 #(1) branchflagmux(eqE, 1'b0, ltE, ltuE, Funct3E[2:1], BranchFlagE);
   assign BranchTakenE = BranchFlagE ^ Funct3E[0];
-    
   assign PCSrcE = JumpE | BranchE & BranchTakenE;
 
+  // Other execute stage controller signals
   assign MemReadE = MemRWE[1];
   assign SCE = (ResultSrcE == 3'b100);
-
   assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
   
   // Memory stage pipeline control register

From c9291655da312af2a3d98a387c9eb8ee7c89c765 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 16:12:31 -0600
Subject: [PATCH 65/95] Fixed bug most of the bugs related to the dcache
 changes, but the mmu tests don't pass.

---
 wally-pipelined/regression/wave.do     | 196 +++++------
 wally-pipelined/src/cache/dcache.sv    |  22 +-
 wally-pipelined/src/cache/dcachefsm.sv | 437 +------------------------
 wally-pipelined/src/lsu/lsu.sv         |  41 ++-
 wally-pipelined/src/lsu/lsuArb.sv      |   8 +-
 5 files changed, 139 insertions(+), 565 deletions(-)

diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index e7970db8..3e19f65b 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -103,15 +103,15 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
 add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
 add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
 add wave -noupdate -group {instruction pipeline} /testbench/InstrW
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
-add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
+add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
@@ -168,86 +168,86 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
-add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/WayHit
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/VictimWay
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
-add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
-add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
-add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
-add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
-add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
-add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/RAdr
-add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
-add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
-add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
-add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
-add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
-add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
-add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
-add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
-add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
+add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
+add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/RAdr
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
 add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
 add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
@@ -272,7 +272,6 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
 add wave -noupdate -expand -group lsu /testbench/dut/hart/hzu/LSUStall
 add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
@@ -341,10 +340,10 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
 add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
@@ -501,8 +500,13 @@ add wave -noupdate /testbench/dut/hart/lsu/CurrState
 add wave -noupdate /testbench/dut/hart/lsu/InterlockStall
 add wave -noupdate /testbench/dut/hart/ifu/icache/PCNextF
 add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
+add wave -noupdate /testbench/dut/hart/lsu/WalkerInstrPageFaultF
+add wave -noupdate /testbench/dut/hart/lsu/WalkerPageFaultM
+add wave -noupdate /testbench/dut/hart/lsu/dcache/RAdr
+add wave -noupdate /testbench/dut/hart/lsu/dcache/SelAdrM
+add wave -noupdate /testbench/dut/hart/lsu/SelReplayCPURequest
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {23208 ns} 0}
+WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {3615 ns} 0}
 quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
@@ -518,4 +522,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {23041 ns} {23377 ns}
+WaveRestoreZoom {3453 ns} {3729 ns}
diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 258337f8..ab870b64 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -36,7 +36,7 @@ module dcache
    input logic [6:0] 	       Funct7M,
    input logic [1:0] 	       AtomicM,
    input logic 		       FlushDCacheM,
-   input logic [11:0] 	       IEUAdrE, // virtual address, but we only use the lower 12 bits.
+   input logic [11:0] 	       MemAdrE, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0]  MemPAdrM, // physical address
    input logic [11:0] 	       VAdr, // when hptw writes dtlb we use this address to index SRAM.
 
@@ -50,15 +50,9 @@ module dcache
    // inputs from TLB and PMA/P
    input logic 		       ExceptionM,
    input logic 		       PendingInterruptM, 
-   input logic 		       DTLBMissM,
-   input logic 		       ITLBMissF,
    input logic 		       CacheableM,
-   input logic 		       DTLBWriteM,
-   input logic 		       ITLBWriteF,
-   input logic 		       WalkerInstrPageFaultF,
    // from ptw
-   input logic 		       SelPTW,
-   input logic 		       WalkerPageFaultM, 
+   input logic 		       IgnoreRequest,
    output logic 	       MemAfterIWalkDone,
    // ahb side
    (* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
@@ -147,8 +141,8 @@ module dcache
   // Read Path CPU (IEU) side
 
   mux4 #(INDEXLEN)
-  AdrSelMux(.d0(IEUAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
-	    .d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+  AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
+	    .d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** REMOVE
 	    .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 		//.d2(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
 	    .d3(FlushAdr),
@@ -354,14 +348,8 @@ module dcache
  		      .ExceptionM,
  		      .PendingInterruptM,
  		      .StallWtoDCache,
- 		      .DTLBMissM,
- 		      .ITLBMissF,
  		      .CacheableM,
- 		      .DTLBWriteM,
- 		      .ITLBWriteF,
- 		      .WalkerInstrPageFaultF,
- 		      .SelPTW,
- 		      .WalkerPageFaultM,
+			  .IgnoreRequest,
  		      .AHBAck, // from ahb
  		      .CacheHit,
  		      .FetchCountFlag,
diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index f6975758..b13ed264 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -36,16 +36,9 @@ module dcachefsm
    input logic 		  ExceptionM,
    input logic 		  PendingInterruptM,
    input logic 		  StallWtoDCache,
-   // mmu inputs
-   input logic 		  DTLBMissM,
-   input logic 		  ITLBMissF,
    input logic 		  CacheableM,
-   input logic 		  DTLBWriteM,
-   input logic 		  ITLBWriteF,
-   input logic 		  WalkerInstrPageFaultF,
    // hptw inputs
-   input logic 		  SelPTW,
-   input logic 		  WalkerPageFaultM,
+   input logic 		  IgnoreRequest,
    // Bus inputs
    input logic 		  AHBAck, // from ahb
    // dcache internals
@@ -101,36 +94,11 @@ module dcachefsm
 					   STATE_MISS_READ_WORD_DELAY,
 					   STATE_MISS_WRITE_WORD,
 
-					   STATE_PTW_READY,
-					   STATE_PTW_READ_MISS_FETCH_WDV,
-					   STATE_PTW_READ_MISS_FETCH_DONE,
-					   STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK,
-					   STATE_PTW_READ_MISS_EVICT_DIRTY,		
-					   STATE_PTW_READ_MISS_READ_WORD,
-					   STATE_PTW_READ_MISS_READ_WORD_DELAY,
-					   STATE_PTW_ACCESS_AFTER_WALK,		// dead state remove
-
 					   STATE_UNCACHED_WRITE,
 					   STATE_UNCACHED_WRITE_DONE,
 					   STATE_UNCACHED_READ,
 					   STATE_UNCACHED_READ_DONE,
 
-					   STATE_PTW_FAULT_READY,
-					   STATE_PTW_FAULT_CPU_BUSY,
-					   STATE_PTW_FAULT_MISS_FETCH_WDV,
-					   STATE_PTW_FAULT_MISS_FETCH_DONE,
-					   STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK,
-					   STATE_PTW_FAULT_MISS_READ_WORD,
-					   STATE_PTW_FAULT_MISS_READ_WORD_DELAY,
-					   STATE_PTW_FAULT_MISS_WRITE_WORD,
-					   STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY,
-					   STATE_PTW_FAULT_MISS_EVICT_DIRTY,
-
-					   STATE_PTW_FAULT_UNCACHED_WRITE,
-					   STATE_PTW_FAULT_UNCACHED_WRITE_DONE,
-					   STATE_PTW_FAULT_UNCACHED_READ,
-					   STATE_PTW_FAULT_UNCACHED_READ_DONE,
-
 					   STATE_CPU_BUSY,
 					   STATE_CPU_BUSY_FINISH_AMO,
   
@@ -191,18 +159,16 @@ module dcachefsm
 		LRUWriteEn = 1'b0;
 		CommittedM = 1'b0;
 
-
 		// TLB Miss	
-		if(((AnyCPUReqM & DTLBMissM) | ITLBMissF) & ~(ExceptionM | PendingInterruptM)) begin
+		if(IgnoreRequest) begin
 		  // the LSU arbiter has not yet selected the PTW.
 		  // The CPU needs to be stalled until that happens.
 		  // If we set DCacheStall for 1 cycle before going to
 		  // PTW ready the CPU will stall.
 		  // The page table walker asserts it's control 1 cycle
 		  // after the TLBs miss.
-		  CommittedM = 1'b1;
-		  DCacheStall = 1'b1;
-		  NextState = STATE_PTW_READY;
+		  // CommittedM = 1'b1; ??? *** Not Sure yet.
+		  NextState = STATE_READY;
 		end
 
 		// Flush dcache to next level of memory
@@ -215,7 +181,7 @@ module dcachefsm
 		end
 		
 		// amo hit
-		else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
 		  SelAdrM = 2'b10;
 		  DCacheStall = 1'b0;
 		  
@@ -231,7 +197,7 @@ module dcachefsm
 		  end
 		end
 		// read hit valid cached
-		else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
 		  DCacheStall = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  
@@ -244,7 +210,7 @@ module dcachefsm
 	      end
 		end
 		// write hit valid cached
-		else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit & ~DTLBMissM) begin
+		else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
 		  SelAdrM = 2'b10;
 		  DCacheStall = 1'b0;
 		  SRAMWordWriteEnableM = 1'b1;
@@ -260,27 +226,27 @@ module dcachefsm
 		  end
 		end
 		// read or write miss valid cached
-		else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit & ~DTLBMissM) begin
+		else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit) begin
 		  NextState = STATE_MISS_FETCH_WDV;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		end
 		// uncached write
-		else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
 		  NextState = STATE_UNCACHED_WRITE;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		  AHBWrite = 1'b1;
 		end
 		// uncached read
-		else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
 		  NextState = STATE_UNCACHED_READ;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		  AHBRead = 1'b1;	  
 		end
 		// fault
-		else if(AnyCPUReqM & (ExceptionM | PendingInterruptM) & ~DTLBMissM) begin
+		else if(AnyCPUReqM & (ExceptionM | PendingInterruptM)) begin
 		  NextState = STATE_READY;
 		end
 		else NextState = STATE_READY;
@@ -394,144 +360,7 @@ module dcachefsm
 		end	  
       end
 
-      STATE_PTW_READY: begin
-		// now all output connect to PTW instead of CPU.
-		CommittedM = 1'b1;
-		SelAdrM = 2'b00;
-		DCacheStall = 1'b0;
-		LRUWriteEn = 1'b0;
-		CntReset = 1'b0;
 
-		// In this branch we remove stall and go back to ready.  There is no request for memory from the
-		// datapath or the walker had a fault.
-		// types 3b, 4a, 4b, and 7c.
-		if ((DTLBMissM & WalkerPageFaultM) | // 3b or 7c (can have either itlb miss or not)
-			(ITLBMissF & (WalkerInstrPageFaultF | ITLBWriteF) & ~AnyCPUReqM & ~DTLBMissM) | // 4a and 4b
-			(DTLBMissM & ITLBMissF & WalkerPageFaultM)) begin // 7c  *** BUG redundant with first condiction.
-		  NextState = STATE_READY;
-		  DCacheStall = 1'b0;
-		end
-		// in this branch we go back to ready, but there is a memory operation from
-		// the datapath so we MUST stall and replay the operation.
-		// types 3a and 5a
-		else if ((DTLBMissM & DTLBWriteM) |  // 3a
-				 (ITLBMissF & ITLBWriteF & AnyCPUReqM)) begin // 5a
-		  NextState = STATE_READY;
-		  DCacheStall = 1'b1;
-		  SelAdrM = 2'b01;
-		end
-
-		// like 5a we want to stall and go to the ready state, but we also have to save
-		// the WalkerInstrPageFaultF so it is held until the end of the memory operation
-		// from the datapath.
-		// types 5b
-		else if (ITLBMissF & WalkerInstrPageFaultF & AnyCPUReqM) begin // 5b
-		  NextState = STATE_PTW_FAULT_READY;
-		  DCacheStall = 1'b1;
-		  SelAdrM = 2'b01;
-		end
-
-		// in this branch we stay in ptw_ready because we are doing an itlb walk
-		// after a dtlb walk.
-		// types 7a and 7b.
-		else if (DTLBMissM & DTLBWriteM & ITLBMissF)begin
-		  NextState = STATE_PTW_READY;
-		  DCacheStall = 1'b0;
-		  
-		  // read hit valid cached
-		end else if(MemRWM[1] & CacheableM & ~ExceptionM & CacheHit) begin
-		  NextState = STATE_PTW_READY;
-		  DCacheStall = 1'b0;
-		  LRUWriteEn = 1'b1;
-		end
-
-		// read miss valid cached
-		else if(SelPTW & MemRWM[1] & CacheableM & ~ExceptionM & ~CacheHit) begin
-		  NextState = STATE_PTW_READ_MISS_FETCH_WDV;
-		  CntReset = 1'b1;
-		  DCacheStall = 1'b1;
-		end
-
-		else begin
-		  NextState = STATE_PTW_READY;
-		  DCacheStall = 1'b0;
-		end
-      end
-
-      STATE_PTW_READ_MISS_FETCH_WDV: begin
-		DCacheStall = 1'b1;
-        PreCntEn = 1'b1;
-		AHBRead = 1'b1;
-		SelAdrM = 2'b10;
-		CommittedM = 1'b1;
-		
-        if(FetchCountFlag & AHBAck) begin
-          NextState = STATE_PTW_READ_MISS_FETCH_DONE;
-        end else begin
-          NextState = STATE_PTW_READ_MISS_FETCH_WDV;
-        end
-      end
-
-      STATE_PTW_READ_MISS_FETCH_DONE: begin
-		DCacheStall = 1'b1;
-		SelAdrM = 2'b10;
-        CntReset = 1'b1;
-		CommittedM = 1'b1;
-        CntReset = 1'b1;
-		if(VictimDirty) begin
-		  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
-		end else begin
-		  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
-		end
-      end
-
-      STATE_PTW_READ_MISS_EVICT_DIRTY: begin
-		DCacheStall = 1'b1;
-        PreCntEn = 1'b1;
-		AHBWrite = 1'b1;
-		SelAdrM = 2'b10;
-		CommittedM = 1'b1;
-		SelEvict = 1'b1;
-		if(FetchCountFlag & AHBAck) begin
-		  NextState = STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK;
-		end else begin
-		  NextState = STATE_PTW_READ_MISS_EVICT_DIRTY;
-		end	  
-      end
-      
-
-      STATE_PTW_READ_MISS_WRITE_CACHE_BLOCK: begin
-		SRAMBlockWriteEnableM = 1'b1;
-		DCacheStall = 1'b1;
-		NextState = STATE_PTW_READ_MISS_READ_WORD;
-		SelAdrM = 2'b10;
-		SetValid = 1'b1;
-		ClearDirty = 1'b1;
-		CommittedM = 1'b1;
-		//LRUWriteEn = 1'b1;
-      end
-
-      STATE_PTW_READ_MISS_READ_WORD: begin
-		SelAdrM = 2'b10;
-		DCacheStall = 1'b1;
-		CommittedM = 1'b1;
-		NextState = STATE_PTW_READ_MISS_READ_WORD_DELAY;
-      end
-
-      STATE_PTW_READ_MISS_READ_WORD_DELAY: begin
-		SelAdrM = 2'b10;
-		NextState = STATE_PTW_READY;
-		CommittedM = 1'b1;
-      end
-      
-      STATE_PTW_ACCESS_AFTER_WALK: begin
-		DCacheStall = 1'b1;
-		SelAdrM = 2'b10;
-		CommittedM = 1'b1;
-		LRUWriteEn = 1'b1;
-		NextState = STATE_READY;
-      end
-      
       STATE_CPU_BUSY: begin
 		CommittedM = 1'b1;
 		SelAdrM = 2'b00;
@@ -608,250 +437,6 @@ module dcachefsm
 		end 
       end
 
-
-      // itlb => instruction page fault states with memory request.
-      STATE_PTW_FAULT_READY: begin
-		DCacheStall = 1'b0;
-		LRUWriteEn = 1'b0;
-		SelAdrM = 2'b00;
-		MemAfterIWalkDone = 1'b0;
-		SetDirty = 1'b0;
-		LRUWriteEn = 1'b0;
-		CntReset = 1'b0;
-		AHBWrite = 1'b0;
-		AHBRead = 1'b0;
-		CommittedM = 1'b1;
-		NextState = STATE_READY;
-		
-		/// *** BUG BUG BUG missing AMO states.
-
-		// read hit valid cached
-		if(MemRWM[1] & CacheableM & CacheHit & ~DTLBMissM) begin
-		  DCacheStall = 1'b0;
-		  LRUWriteEn = 1'b1;
-		  
-		  if(StallWtoDCache) begin
-			NextState = STATE_PTW_FAULT_CPU_BUSY;
-            SelAdrM = 2'b10;
-		  end
-		  else begin
-			MemAfterIWalkDone = 1'b1;
-			NextState = STATE_READY;
-		  end
-		end
-		
-		// write hit valid cached
-		else if (MemRWM[0] & CacheableM & CacheHit & ~DTLBMissM) begin
-		  SelAdrM = 2'b10;
-		  DCacheStall = 1'b0;
-		  SRAMWordWriteEnableM = 1'b1;
-		  SetDirty = 1'b1;
-		  LRUWriteEn = 1'b1;
-		  
-		  if(StallWtoDCache) begin 
-			NextState = STATE_PTW_FAULT_CPU_BUSY;
-			SelAdrM = 2'b10;
-		  end
-		  else begin
-			MemAfterIWalkDone = 1'b1;
-			NextState = STATE_READY;
-		  end
-		end
-		// read or write miss valid cached
-		else if((|MemRWM) & CacheableM & ~CacheHit & ~DTLBMissM) begin
-		  NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
-		  CntReset = 1'b1;
-		  DCacheStall = 1'b1;
-		end
-		// uncached write
-		else if(MemRWM[0] & ~CacheableM & ~DTLBMissM) begin
-		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
-		  CntReset = 1'b1;
-		  DCacheStall = 1'b1;
-		  AHBWrite = 1'b1;
-		end
-		// uncached read
-		else if(MemRWM[1] & ~CacheableM & ~DTLBMissM) begin
-		  NextState = STATE_PTW_FAULT_UNCACHED_READ;
-		  CntReset = 1'b1;
-		  DCacheStall = 1'b1;
-		  AHBRead = 1'b1;	  
-		  MemAfterIWalkDone = 1'b0;
-		end
-		// fault
-		else  begin
-		  MemAfterIWalkDone = 1'b1;
-		  NextState = STATE_READY;
-		end
-      end
-      
-      STATE_PTW_FAULT_CPU_BUSY: begin
-		CommittedM = 1'b1;
-		if(StallWtoDCache) begin
-		  NextState = STATE_PTW_FAULT_CPU_BUSY;
-		  MemAfterIWalkDone = 1'b0;
-		  SelAdrM = 2'b10;
-		end
-		else begin
-		  MemAfterIWalkDone = 1'b1;
-		  NextState = STATE_READY;
-		  SelAdrM = 2'b00;
-		end
-      end
-
-      STATE_PTW_FAULT_MISS_FETCH_WDV: begin
-		DCacheStall = 1'b1;
-        PreCntEn = 1'b1;
-		AHBRead = 1'b1;
-		SelAdrM = 2'b10;
-		CommittedM = 1'b1;
-		
-        if(FetchCountFlag & AHBAck) begin
-          NextState = STATE_PTW_FAULT_MISS_FETCH_DONE;
-        end else begin
-          NextState = STATE_PTW_FAULT_MISS_FETCH_WDV;
-        end
-      end
-
-      STATE_PTW_FAULT_MISS_FETCH_DONE: begin
-		DCacheStall = 1'b1;
-		SelAdrM = 2'b10;
-        CntReset = 1'b1;
-		CommittedM = 1'b1;
-		if(VictimDirty) begin
-		  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
-		end else begin
-		  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
-		end
-      end
-
-      STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK: begin
-		SRAMBlockWriteEnableM = 1'b1;
-		DCacheStall = 1'b1;
-		NextState = STATE_PTW_FAULT_MISS_READ_WORD;
-		SelAdrM = 2'b10;
-		SetValid = 1'b1;
-		ClearDirty = 1'b1;
-		CommittedM = 1'b1;
-		//LRUWriteEn = 1'b1;  // DO not update LRU on SRAM fetch update.  Wait for subsequent read/write
-      end
-
-      STATE_PTW_FAULT_MISS_READ_WORD: begin
-		SelAdrM = 2'b10;
-		DCacheStall = 1'b1;
-		CommittedM = 1'b1;
-		if(MemRWM[1]) begin
-		  NextState = STATE_PTW_FAULT_MISS_READ_WORD_DELAY;
-		  // delay state is required as the read signal MemRWM[1] is still high when we
-		  // return to the ready state because the cache is stalling the cpu.
-		end else begin
-		  NextState = STATE_PTW_FAULT_MISS_WRITE_WORD;
-		end
-      end
-
-      STATE_PTW_FAULT_MISS_READ_WORD_DELAY: begin
-		CommittedM = 1'b1;
-		LRUWriteEn = 1'b1;
-		if(StallWtoDCache) begin 
-		  NextState = STATE_PTW_FAULT_CPU_BUSY;
-		  SelAdrM = 2'b10;
-		  MemAfterIWalkDone = 1'b0;
-		end
-		else begin
-		  MemAfterIWalkDone = 1'b1;
-		  NextState = STATE_READY;
-		  SelAdrM = 2'b00;
-		end
-      end
-
-      STATE_PTW_FAULT_MISS_WRITE_WORD: begin
-		SRAMWordWriteEnableM = 1'b1;
-		SetDirty = 1'b1;
-		SelAdrM = 2'b10;
-		DCacheStall = 1'b1;
-		CommittedM = 1'b1;
-		LRUWriteEn = 1'b1;
-		NextState = STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY;
-      end
-
-      STATE_PTW_FAULT_MISS_WRITE_WORD_DELAY: begin
-		CommittedM = 1'b1;
-		if(StallWtoDCache) begin 
-		  NextState = STATE_PTW_FAULT_CPU_BUSY;
-		  MemAfterIWalkDone = 1'b0;
-		  SelAdrM = 2'b10;
-		end
-		else begin
-		  MemAfterIWalkDone = 1'b1;
-		  NextState = STATE_READY;
-		  SelAdrM = 2'b00;
-		end
-      end
-
-      STATE_PTW_FAULT_MISS_EVICT_DIRTY: begin
-		DCacheStall = 1'b1;
-        PreCntEn = 1'b1;
-		AHBWrite = 1'b1;
-		SelAdrM = 2'b10;
-		CommittedM = 1'b1;
-		SelEvict = 1'b1;
-		if(FetchCountFlag & AHBAck) begin
-		  NextState = STATE_PTW_FAULT_MISS_WRITE_CACHE_BLOCK;
-		end else begin
-		  NextState = STATE_PTW_FAULT_MISS_EVICT_DIRTY;
-		end	  
-      end
-
-
-      STATE_PTW_FAULT_UNCACHED_WRITE : begin
-		DCacheStall = 1'b1;	
-		AHBWrite = 1'b1;
-		CommittedM = 1'b1;
-		if(AHBAck) begin
-		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE_DONE;
-		end else begin
-		  NextState = STATE_PTW_FAULT_UNCACHED_WRITE;
-		end
-      end
-
-      STATE_PTW_FAULT_UNCACHED_READ : begin
-		DCacheStall = 1'b1;	
-		AHBRead = 1'b1;
-		CommittedM = 1'b1;
-		if(AHBAck) begin
-		  NextState = STATE_PTW_FAULT_UNCACHED_READ_DONE;
-		end else begin
-		  NextState = STATE_PTW_FAULT_UNCACHED_READ;
-		end
-      end
-      
-      STATE_PTW_FAULT_UNCACHED_WRITE_DONE: begin
-		CommittedM = 1'b1;
-		if(StallWtoDCache) begin
-		  NextState = STATE_PTW_FAULT_CPU_BUSY;
-		  MemAfterIWalkDone = 1'b0;
-		  SelAdrM = 2'b10;
-		end
-		else begin
-		  MemAfterIWalkDone = 1'b1;
-		  NextState = STATE_READY;
-		  SelAdrM = 2'b00;
-		end
-      end
-
-      STATE_PTW_FAULT_UNCACHED_READ_DONE: begin
-		CommittedM = 1'b1;
-		SelUncached = 1'b1;
-		if(StallWtoDCache) begin 
-		  NextState = STATE_PTW_FAULT_CPU_BUSY;
-		  SelAdrM = 2'b10;
-		end
-		else begin
-		  MemAfterIWalkDone = 1'b1;
-		  NextState = STATE_READY;
-		end 
-      end
-
       STATE_FLUSH: begin
 		DCacheStall = 1'b1;
 		CommittedM = 1'b1;
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 65772a71..38374cb3 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -107,8 +107,8 @@ module lsu
   logic [1:0] 		       MemRWMtoLRSC;
   logic [2:0] 		       Funct3MtoDCache;
   logic [1:0] 		       AtomicMtoDCache;
-  logic [`PA_BITS-1:0] 	       MemPAdrMtoDCache;
-  logic [11:0] 		       MemAdrEtoDCache;  
+  logic [`PA_BITS-1:0] 	       MemPAdrNoTranslate;
+  logic [11:0] 		       MemAdrE, MemAdrE_RENAME;  
   logic 		       StallWtoDCache;
   logic 		       MemReadM;
   logic 		       DataMisalignedMfromDCache;
@@ -127,9 +127,6 @@ module lsu
   logic 		       AnyCPUReqM;
   logic 		       MemAfterIWalkDone;
 
-  assign AnyCPUReqM = (|MemRWM)  | (|AtomicM);
-
-
   typedef enum {STATE_T0_READY,
 				STATE_T0_REPLAY,
 				STATE_T0_FAULT_REPLAY,				
@@ -142,8 +139,11 @@ module lsu
   logic 	   InterlockStall;
   logic SelReplayCPURequest;
   logic WalkerInstrPageFaultRaw;
+  logic IgnoreRequest;
   
-  
+
+  assign AnyCPUReqM = (|MemRWM)  | (|AtomicM);
+
   always_ff @(posedge clk)
     if (reset)    CurrState <= #1 STATE_T0_READY;
     else CurrState <= #1 NextState;
@@ -226,9 +226,10 @@ module lsu
 						  (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
   
   // When replaying CPU memory request after PTW select the IEUAdrM for correct address.
-  assign SelReplayCPURequest = NextState == STATE_T0_READY;
+  assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;
   assign SelPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
 				  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
+  assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
   
   
 
@@ -284,8 +285,8 @@ module lsu
 		 .MemRWMtoLRSC(MemRWMtoLRSC),
 		 .Funct3MtoDCache(Funct3MtoDCache),
 		 .AtomicMtoDCache(AtomicMtoDCache),
-		 .MemPAdrMtoDCache(MemPAdrMtoDCache),
-		 .MemAdrEtoDCache(MemAdrEtoDCache),
+		 .MemPAdrNoTranslate(MemPAdrNoTranslate),
+		 .MemAdrE(MemAdrE),
 		 .StallWtoDCache(StallWtoDCache),
 		 .DataMisalignedMfromDCache(DataMisalignedMfromDCache),
 		 .CommittedMfromDCache(CommittedMfromDCache),
@@ -295,7 +296,7 @@ module lsu
   mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
   dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
        .PrivilegeModeW, .DisableTranslation(DisableTranslation),
-       .PAdr(MemPAdrMtoDCache),
+       .PAdr(MemPAdrNoTranslate),
        .VAdr(IEUAdrM),
        .Size(Funct3MtoDCache[1:0]),
        .PTE(PTE),
@@ -334,9 +335,9 @@ module lsu
   always_comb
     case(Funct3MtoDCache[1:0]) 
       2'b00:  DataMisalignedMfromDCache = 0;                       // lb, sb, lbu
-      2'b01:  DataMisalignedMfromDCache = MemPAdrMtoDCache[0];              // lh, sh, lhu
-      2'b10:  DataMisalignedMfromDCache = MemPAdrMtoDCache[1] | MemPAdrMtoDCache[0]; // lw, sw, flw, fsw, lwu
-      2'b11:  DataMisalignedMfromDCache = |MemPAdrMtoDCache[2:0];           // ld, sd, fld, fsd
+      2'b01:  DataMisalignedMfromDCache = MemPAdrNoTranslate[0];              // lh, sh, lhu
+      2'b10:  DataMisalignedMfromDCache = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu
+      2'b11:  DataMisalignedMfromDCache = |MemPAdrNoTranslate[2:0];           // ld, sd, fld, fsd
     endcase 
 
   // Determine if address is valid
@@ -347,6 +348,8 @@ module lsu
   // 1. ram // controlled by `MEM_DTIM
   // 2. cache `MEM_DCACHE
   // 3. wire pass-through
+  assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0];
+  
   dcache dcache(.clk(clk),
 		.reset(reset),
 		.StallWtoDCache(StallWtoDCache),
@@ -355,9 +358,9 @@ module lsu
 		.Funct7M(Funct7M),
 		.FlushDCacheM,
 		.AtomicM(AtomicMtoDCache),
-		.IEUAdrE(MemAdrEtoDCache),
+		.MemAdrE(MemAdrE_RENAME),
 		.MemPAdrM(MemPAdrM),
-		.VAdr(IEUAdrM[11:0]),		
+		.VAdr(IEUAdrM[11:0]),	 // this will be removed once the dcache hptw interlock is removed.
 		.WriteDataM(WriteDataM),
 		.ReadDataM(ReadDataM),
 		.DCacheStall(DCacheStall),
@@ -365,16 +368,10 @@ module lsu
 		.DCacheMiss,
 		.DCacheAccess,		
 		.ExceptionM(ExceptionM),
+		.IgnoreRequest,
 		.PendingInterruptM(PendingInterruptMtoDCache),
-		.DTLBMissM(DTLBMissM),
 		.CacheableM(CacheableMtoDCache), 
-		.DTLBWriteM(DTLBWriteM),
-		.ITLBWriteF(ITLBWriteF),
-		.ITLBMissF,
 		.MemAfterIWalkDone,
-		.SelPTW,
-		.WalkerPageFaultM(WalkerPageFaultM),
-		.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
 
 		// AHB connection
 		.AHBPAdr(DCtoAHBPAdrM),
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
index 498f0682..91c5f75f 100644
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ b/wally-pipelined/src/lsu/lsuArb.sv
@@ -52,8 +52,8 @@ module lsuArb
    output logic [1:0] 	       MemRWMtoLRSC,
    output logic [2:0] 	       Funct3MtoDCache,
    output logic [1:0] 	       AtomicMtoDCache,
-   output logic [`PA_BITS-1:0] MemPAdrMtoDCache,
-   output logic [11:0] 	       MemAdrEtoDCache, 
+   output logic [`PA_BITS-1:0] MemPAdrNoTranslate,   // THis name is very bad. need a better name. This is the raw address from either the ieu or the hptw.
+   output logic [11:0] 	       MemAdrE, 
    output logic 	       StallWtoDCache,
    output logic 	       PendingInterruptMtoDCache,
    
@@ -83,8 +83,8 @@ module lsuArb
 
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
   assign IEUAdrMExt = {2'b00, IEUAdrM};
-  assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0]; 
-  assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];  
+  assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0]; 
+  assign MemAdrE = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];  
   assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.
   assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;

From c453b285dc1f13b0b23c055ef2697420d550ecf0 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 17:01:13 -0600
Subject: [PATCH 66/95] Fixed bug where icache did not replay PCF on itlb miss.

---
 wally-pipelined/src/cache/icachefsm.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 96bea67c..dd4e2e4a 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -144,6 +144,7 @@ module icachefsm
  -----/\----- EXCLUDED -----/\----- */
 		if(ITLBMissF) begin
 		  NextState = STATE_READY;
+		  SelAdr = 2'b01;
 		  ICacheStallF = 1'b0;
 		end
 		else if (hit & ~spill) begin

From fe5c05eb8d28bd0b29c2aa0c0481d43d6e12089e Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 17:53:13 -0600
Subject: [PATCH 67/95] Created hack to get around imperas64mmu unknown (value
 = x) bug.

---
 wally-pipelined/src/lsu/lsu.sv | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 38374cb3..669b5ee5 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -221,9 +221,12 @@ module lsu
   end // always_comb
 
   // signal to CPU it needs to wait on HPTW.
-  assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
+  assign InterlockStall_BUG = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
 						  (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultF) |
 						  (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
+
+  assign InterlockStall = InterlockStall_BUG === 1'bx ? 1'b0 : InterlockStall_BUG;
+  
   
   // When replaying CPU memory request after PTW select the IEUAdrM for correct address.
   assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;

From eceb41805637ebde60650065a0e74aad8172bddc Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 17:57:12 -0600
Subject: [PATCH 68/95] Implemented what I think is the last required change
 for the lsu state machine.

---
 wally-pipelined/src/lsu/lsu.sv | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 669b5ee5..cff0a417 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -222,8 +222,8 @@ module lsu
 
   // signal to CPU it needs to wait on HPTW.
   assign InterlockStall_BUG = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
-						  (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultF) |
-						  (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultF) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
+						  (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) |
+						  (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
 
   assign InterlockStall = InterlockStall_BUG === 1'bx ? 1'b0 : InterlockStall_BUG;
   
@@ -234,6 +234,7 @@ module lsu
 				  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
   assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
   
+  assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY;
   
 
   flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, IEUAdrM);
@@ -259,7 +260,7 @@ module lsu
 		.HPTWStall,
 	    .AnyCPUReqM,
 	    .MemAfterIWalkDone,
-	    .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
+	    .WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
 	    .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
 	    .WalkerStorePageFaultM(WalkerStorePageFaultM));
 

From a39b47d2262e626399fae8cce3c7d2f6aae94f6d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 18:16:08 -0600
Subject: [PATCH 69/95] Switched to using an always block for lsu stall logic. 
 This avoids the problematic x propagation.

---
 wally-pipelined/src/lsu/lsu.sv | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index cff0a417..2fbd9f67 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -221,11 +221,26 @@ module lsu
   end // always_comb
 
   // signal to CPU it needs to wait on HPTW.
-  assign InterlockStall_BUG = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
+/* -----\/----- EXCLUDED -----\/-----
+  // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction.  InterlockStall becomes x and it propagates
+  // everywhere.  The case statement below implements the same logic but any x on the inputs will resolve to 0.
+  assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
 						  (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) |
 						  (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
 
-  assign InterlockStall = InterlockStall_BUG === 1'bx ? 1'b0 : InterlockStall_BUG;
+ -----/\----- EXCLUDED -----/\----- */
+
+  always_comb begin
+	InterlockStall = 1'b0;
+	case(CurrState) 
+	  STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
+	  STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
+	  STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
+	  STATE_T5_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
+	  STATE_T7_DITLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
+	  default: InterlockStall = 1'b0;
+	endcase
+  end
   
   
   // When replaying CPU memory request after PTW select the IEUAdrM for correct address.

From d9cc9afd4952b48fd366497fcbb917145bb4a702 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 18:24:40 -0600
Subject: [PATCH 70/95] Changes to buildroot to support MemAdrM to IEUAdrM name
 changes.

---
 wally-pipelined/testbench/testbench-linux.sv | 22 ++++++++++----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index a64ca434..0a329d95 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -93,14 +93,14 @@ module testbench();
   logic [`XLEN-1:0] PCW;
   logic [31:0]      InstrW;
   logic             InstrValidW;
-  logic [`XLEN-1:0] MemAdrW, WriteDataW;
+  logic [`XLEN-1:0] IEUAdrW, WriteDataW;
   logic             TrapW;
   `define FLUSHW dut.hart.FlushW
   `define STALLW dut.hart.StallW
   flopenrc #(`XLEN)         PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW);
   flopenr #(32)          InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW);
   flopenrc #(1)        controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW);
-  flopenrc #(`XLEN)     MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.MemAdrM, MemAdrW);
+  flopenrc #(`XLEN)     IEUAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.IEUAdrM, IEUAdrW);
   flopenrc #(`XLEN)  WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW);  
   flopenr #(1)            TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);
 
@@ -134,7 +134,7 @@ module testbench();
       string            RegWrite``STAGE; \
       integer           ExpectedRegAdr``STAGE; \
       logic [`XLEN-1:0] ExpectedRegValue``STAGE; \
-      logic [`XLEN-1:0] ExpectedMemAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
+      logic [`XLEN-1:0] ExpectedIEUAdr``STAGE, ExpectedMemReadData``STAGE, ExpectedMemWriteData``STAGE; \
       string            ExpectedCSRArray``STAGE[10:0]; \
       logic [`XLEN-1:0] ExpectedCSRArrayValue``STAGE[10:0];
   `DECLARE_TRACE_SCANNER_SIGNALS(E)
@@ -155,7 +155,7 @@ module testbench();
   integer           ExpectedRegAdrW;
   logic [`XLEN-1:0] ExpectedRegValueW;
   string            MemOpW;
-  logic [`XLEN-1:0] ExpectedMemAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
+  logic [`XLEN-1:0] ExpectedIEUAdrW, ExpectedMemReadDataW, ExpectedMemWriteDataW;
   integer           NumCSRW;
   string            ExpectedCSRArrayW[10:0];
   logic [`XLEN-1:0] ExpectedCSRArrayValueW[10:0];
@@ -411,7 +411,7 @@ module testbench();
         // parse memory address, read data, and/or write data \
         end else if(ExpectedTokens``STAGE[MarkerIndex``STAGE].substr(0, 2) == "Mem") begin \
           MemOp``STAGE = ExpectedTokens``STAGE[MarkerIndex``STAGE]; \
-          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedMemAdr``STAGE); \
+          matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+1], "%x", ExpectedIEUAdr``STAGE); \
           matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+2], "%x", ExpectedMemWriteData``STAGE); \
           matchCount``STAGE = $sscanf(ExpectedTokens``STAGE[MarkerIndex``STAGE+3], "%x", ExpectedMemReadData``STAGE); \
           MarkerIndex``STAGE += 4; \
@@ -509,7 +509,7 @@ module testbench();
       RegWriteW <= "";
       ExpectedRegAdrW <= '0;
       ExpectedRegValueW <= '0;
-      ExpectedMemAdrW <= '0;
+      ExpectedIEUAdrW <= '0;
       MemOpW <= "";
       ExpectedMemWriteDataW <= '0;
       ExpectedMemReadDataW <= '0;
@@ -522,7 +522,7 @@ module testbench();
         RegWriteW <= "";
         ExpectedRegAdrW <= '0;
         ExpectedRegValueW <= '0;
-        ExpectedMemAdrW <= '0;
+        ExpectedIEUAdrW <= '0;
         MemOpW <= "";
         ExpectedMemWriteDataW <= '0;
         ExpectedMemReadDataW <= '0;
@@ -534,7 +534,7 @@ module testbench();
         RegWriteW <= RegWriteM;
         ExpectedRegAdrW <= ExpectedRegAdrM;
         ExpectedRegValueW <= ExpectedRegValueM;
-        ExpectedMemAdrW <= ExpectedMemAdrM;
+        ExpectedIEUAdrW <= ExpectedIEUAdrM;
         MemOpW <= MemOpM;
         ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
         ExpectedMemReadDataW <= ExpectedMemReadDataM;
@@ -551,7 +551,7 @@ module testbench();
           //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
           release dut.uncore.clint.clint.MTIME;
         end 
-        //if (ExpectedMemAdrM == 'h10000005) begin
+        //if (ExpectedIEUAdrM == 'h10000005) begin
           //$display("%tns, %d instrs: releasing force of ReadDataM.", $time, InstrCountW);
           //release dut.hart.ieu.dp.ReadDataM;
         //end
@@ -588,8 +588,8 @@ module testbench();
           `checkEQ(name, dut.hart.ieu.dp.regf.rf[ExpectedRegAdrW], ExpectedRegValueW)
         end
         if (MemOpW.substr(0,2) == "Mem") begin
-          if(`DEBUG_TRACE >= 4) $display("\tMemAdrW: %016x ? expected: %016x", MemAdrW, ExpectedMemAdrW);
-          `checkEQ("MemAdrW",MemAdrW,ExpectedMemAdrW)
+          if(`DEBUG_TRACE >= 4) $display("\tIEUAdrW: %016x ? expected: %016x", IEUAdrW, ExpectedIEUAdrW);
+          `checkEQ("IEUAdrW",IEUAdrW,ExpectedIEUAdrW)
           if(MemOpW == "MemR" || MemOpW == "MemRW") begin
             if(`DEBUG_TRACE >= 4) $display("\tReadDataW: %016x ? expected: %016x", dut.hart.ieu.dp.ReadDataW, ExpectedMemReadDataW);
             `checkEQ("ReadDataW",dut.hart.ieu.dp.ReadDataW,ExpectedMemReadDataW)

From 3c3bfd055e589e348e57554069d82855e453b25e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Sun, 19 Dec 2021 16:53:41 -0800
Subject: [PATCH 71/95] Moved generate statements for optional units into
 wallypipelinedhart

---
 wally-pipelined/src/fpu/fpu.sv                | 474 +++++++++---------
 wally-pipelined/src/muldiv/muldiv.sv          |  93 ++--
 wally-pipelined/src/privileged/csr.sv         | 108 ++--
 wally-pipelined/src/privileged/privileged.sv  |   2 -
 .../src/wally/wallypipelinedhart.sv           | 156 +++---
 .../sdc/tb => testbench/sdc}/ram2sdLoad.py    |   0
 .../sdc/tb => testbench/sdc}/ramdisk2.hex     |   0
 .../{src/sdc/tb => testbench/sdc}/run_tb.do   |   0
 .../sdc/tb => testbench/sdc}/sd_top_tb.sv     |   0
 .../{src/sdc/tb => testbench/sdc}/wave.do     |   0
 wally-pipelined/testbench/testbench-linux.sv  |  54 +-
 wally-pipelined/testbench/testbench.sv        |   4 +-
 12 files changed, 424 insertions(+), 467 deletions(-)
 rename wally-pipelined/{src/sdc/tb => testbench/sdc}/ram2sdLoad.py (100%)
 rename wally-pipelined/{src/sdc/tb => testbench/sdc}/ramdisk2.hex (100%)
 rename wally-pipelined/{src/sdc/tb => testbench/sdc}/run_tb.do (100%)
 rename wally-pipelined/{src/sdc/tb => testbench/sdc}/sd_top_tb.sv (100%)
 rename wally-pipelined/{src/sdc/tb => testbench/sdc}/wave.do (100%)

diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv
index 0ba61c6c..7b9680ed 100755
--- a/wally-pipelined/src/fpu/fpu.sv
+++ b/wally-pipelined/src/fpu/fpu.sv
@@ -44,258 +44,244 @@ module fpu (
   output logic [4:0] 	   SetFflagsM        // FPU flags (to privileged unit)
   );
 
-  //*** make everything FLEN at some point
-  //*** add the 128 bit support to the if statement when needed
-  //*** make new tests for fp using testfloat that include flag checking and all rounding modes
-  //*** what is the format for 16-bit - finding conflicting info online can't find anything specified in spec
-  //*** only fma/mul and fp <-> int convert flags have been tested. test the others.
+   //*** make everything FLEN at some point
+   //*** add the 128 bit support to the if statement when needed
+   //*** make new tests for fp using testfloat that include flag checking and all rounding modes
+   //*** what is the format for 16-bit - finding conflicting info online can't find anything specified in spec
+   //*** only fma/mul and fp <-> int convert flags have been tested. test the others.
 
-  // FPU specifics:
-  //    - uses NaN-blocking format
-  //        - if there are any unsused bits the most significant bits are filled with 1s
-  //                single stored in a double: | 32 1s | single precision value |
-  //    - sets the underflow after rounding
+   // FPU specifics:
+   //    - uses NaN-blocking format
+   //        - if there are any unsused bits the most significant bits are filled with 1s
+   //                single stored in a double: | 32 1s | single precision value |
+   //    - sets the underflow after rounding
   
-  generate if (`F_SUPPORTED | `D_SUPPORTED) begin : fpu
+   // control signals
+   logic 		  FRegWriteD, FRegWriteE, FRegWriteW; // FP register write enable
+   logic [2:0] 	  FrmD, FrmE, FrmM;                   // FP rounding mode
+   logic 		  FmtD, FmtE, FmtM, FmtW;             // FP precision 0-single 1-double
+   logic 		  FDivStartD, FDivStartE;             // Start division or squareroot
+   logic 		  FWriteIntD;                         // Write to integer register
+   logic [1:0] 	  FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals
+   logic [1:0] 	  FResultSelD, FResultSelE;           // Select the result written to FP register
+   logic [1:0] 	  FResultSelM, FResultSelW;           // Select the result written to FP register
+   logic [2:0] 	  FOpCtrlD, FOpCtrlE;       // Select which opperation to do in each component
+   logic [2:0] 	  FResSelD, FResSelE;       // Select one of the results that finish in the memory stage
+   logic [1:0] 	  FIntResSelD, FIntResSelE;           // Select the result written to the integer resister
+   logic [4:0] 	  Adr1E, Adr2E, Adr3E;                // adresses of each input
 
-     // control signals
-     logic 		  FRegWriteD, FRegWriteE, FRegWriteW; // FP register write enable
-     logic [2:0] 	  FrmD, FrmE, FrmM;                   // FP rounding mode
-     logic 		  FmtD, FmtE, FmtM, FmtW;             // FP precision 0-single 1-double
-     logic 		  FDivStartD, FDivStartE;             // Start division or squareroot
-     logic 		  FWriteIntD;                         // Write to integer register
-     logic [1:0] 	  FForwardXE, FForwardYE, FForwardZE; // forwarding mux control signals
-     logic [1:0] 	  FResultSelD, FResultSelE;           // Select the result written to FP register
-     logic [1:0] 	  FResultSelM, FResultSelW;           // Select the result written to FP register
-     logic [2:0] 	  FOpCtrlD, FOpCtrlE;       // Select which opperation to do in each component
-     logic [2:0] 	  FResSelD, FResSelE;       // Select one of the results that finish in the memory stage
-     logic [1:0] 	  FIntResSelD, FIntResSelE;           // Select the result written to the integer resister
-     logic [4:0] 	  Adr1E, Adr2E, Adr3E;                // adresses of each input
-     
-     // regfile signals
-     logic [63:0] 	  FRD1D, FRD2D, FRD3D;                // Read Data from FP register - decode stage
-     logic [63:0] 	  FRD1E, FRD2E, FRD3E;                // Read Data from FP register - execute stage
-     logic [63:0] 	  FSrcXE;                             // Input 1 to the various units (after forwarding)
-     logic [63:0] 	  FPreSrcYE, FSrcYE;                  // Input 2 to the various units (after forwarding)
-     logic [63:0] 	  FPreSrcZE, FSrcZE;                  // Input 3 to the various units (after forwarding)
-     
-     // unpacking signals
-     logic 		  XSgnE, YSgnE, ZSgnE;                // input's sign - execute stage
-     logic 		  XSgnM, YSgnM;                       // input's sign - memory stage
-     logic [10:0] 	  XExpE, YExpE, ZExpE;                // input's exponent - execute stage
-     logic [10:0] 	  XExpM, YExpM, ZExpM;                // input's exponent - memory stage
-     logic [52:0] 	  XManE, YManE, ZManE;                // input's fraction - execute stage
-     logic [52:0] 	  XManM, YManM, ZManM;                // input's fraction - memory stage
-     logic [10:0] 	  BiasE;                              // bias based on precision (single=7f double=3ff)
-     logic 		  XNaNE, YNaNE, ZNaNE;                // is the input a NaN - execute stage
-     logic 		  XNaNM, YNaNM, ZNaNM;                // is the input a NaN - memory stage
-     logic 		  XNaNQ, YNaNQ;                       // is the input a NaN - divide
-     logic 		  XSNaNE, YSNaNE, ZSNaNE;             // is the input a signaling NaN - execute stage
-     logic 		  XSNaNM, YSNaNM, ZSNaNM;             // is the input a signaling NaN - memory stage
-     logic 		  XDenormE, YDenormE, ZDenormE;       // is the input denormalized
-     logic 		  XZeroE, YZeroE, ZZeroE;             // is the input zero - execute stage
-     logic 		  XZeroM, YZeroM, ZZeroM;             // is the input zero - memory stage
-     logic 		  XZeroQ, YZeroQ;                     // is the input zero - divide
-     logic 		  XInfE, YInfE, ZInfE;                // is the input infinity - execute stage
-     logic 		  XInfM, YInfM, ZInfM;                // is the input infinity - memory stage
-     logic 		  XInfQ, YInfQ;                       // is the input infinity - divide
-     logic 		  XExpMaxE;                           // is the exponent all ones (max value)
-     logic 		  XNormE;                             // is normal
-     logic 		  FmtQ;
-     logic 		  FOpCtrlQ;     
-     
-     // result and flag signals
-     logic [63:0] 	  FDivResM, FDivResW;                 // divide/squareroot result
-     logic [4:0] 	  FDivFlgM;                 // divide/squareroot flags  
-     logic [63:0] 	  FMAResM, FMAResW;                   // FMA/multiply result
-     logic [4:0] 	  FMAFlgM;                   // FMA/multiply result	
-     logic [63:0] 	  ReadResW;                           // read result (load instruction)
-     logic [63:0] 	  CvtFpResE;    // add/FP -> FP convert result
-     logic [4:0] 	  CvtFpFlgE;    // add/FP -> FP convert flags
-     logic [63:0] 	  CvtResE;                   // FP <-> int convert result
-     logic [4:0] 	  CvtFlgE;                   // FP <-> int convert flags //*** trim this	
-     logic [63:0] 	  ClassResE;               // classify result
-     logic [63:0] 	  CmpResE;                   // compare result
-     logic 		  CmpNVE;                     // compare invalid flag (Not Valid)     
-     logic [63:0] 	  SgnResE;                   // sign injection result
-     logic 		  SgnNVE;                     // sign injection invalid flag (Not Valid)     
-     logic [63:0] 	  FResE, FResM, FResW;                // selected result that is ready in the memory stage
-     logic [4:0] 	  FFlgE, FFlgM;                       // selected flag that is ready in the memory stage     
-     logic [`XLEN-1:0] 	  FIntResE;     
-     logic [63:0] 	  FPUResultW;                         // final FP result being written to the FP register     
-     // other signals
-     logic 		  FDivSqrtDoneE;                      // is divide done
-     logic [63:0] 	  DivInput1E, DivInput2E;             // inputs to divide/squareroot unit
-     logic 		  load_preload;                       // enable for FF on fpdivsqrt     
-     logic [63:0] 	  AlignedSrcAE;                       // align SrcA to the floating point format
+   // regfile signals
+   logic [63:0] 	  FRD1D, FRD2D, FRD3D;                // Read Data from FP register - decode stage
+   logic [63:0] 	  FRD1E, FRD2E, FRD3E;                // Read Data from FP register - execute stage
+   logic [63:0] 	  FSrcXE;                             // Input 1 to the various units (after forwarding)
+   logic [63:0] 	  FPreSrcYE, FSrcYE;                  // Input 2 to the various units (after forwarding)
+   logic [63:0] 	  FPreSrcZE, FSrcZE;                  // Input 3 to the various units (after forwarding)
 
-     // DECODE STAGE
-     
-     // calculate FP control signals
-     fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .FRM_REGW,
-		  .IllegalFPUInstrD, .FRegWriteD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD, 
-		  .FIntResSelD, .FmtD, .FrmD, .FWriteIntD);
-	
-     // FP register file
-     fregfile fregfile (.clk, .reset, .we4(FRegWriteW),
-			.a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
-			.a4(RdW), .wd4(FPUResultW),
-			.rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));	
+   // unpacking signals
+   logic 		  XSgnE, YSgnE, ZSgnE;                // input's sign - execute stage
+   logic 		  XSgnM, YSgnM;                       // input's sign - memory stage
+   logic [10:0] 	  XExpE, YExpE, ZExpE;                // input's exponent - execute stage
+   logic [10:0] 	  XExpM, YExpM, ZExpM;                // input's exponent - memory stage
+   logic [52:0] 	  XManE, YManE, ZManE;                // input's fraction - execute stage
+   logic [52:0] 	  XManM, YManM, ZManM;                // input's fraction - memory stage
+   logic [10:0] 	  BiasE;                              // bias based on precision (single=7f double=3ff)
+   logic 		  XNaNE, YNaNE, ZNaNE;                // is the input a NaN - execute stage
+   logic 		  XNaNM, YNaNM, ZNaNM;                // is the input a NaN - memory stage
+   logic 		  XNaNQ, YNaNQ;                       // is the input a NaN - divide
+   logic 		  XSNaNE, YSNaNE, ZSNaNE;             // is the input a signaling NaN - execute stage
+   logic 		  XSNaNM, YSNaNM, ZSNaNM;             // is the input a signaling NaN - memory stage
+   logic 		  XDenormE, YDenormE, ZDenormE;       // is the input denormalized
+   logic 		  XZeroE, YZeroE, ZZeroE;             // is the input zero - execute stage
+   logic 		  XZeroM, YZeroM, ZZeroM;             // is the input zero - memory stage
+   logic 		  XZeroQ, YZeroQ;                     // is the input zero - divide
+   logic 		  XInfE, YInfE, ZInfE;                // is the input infinity - execute stage
+   logic 		  XInfM, YInfM, ZInfM;                // is the input infinity - memory stage
+   logic 		  XInfQ, YInfQ;                       // is the input infinity - divide
+   logic 		  XExpMaxE;                           // is the exponent all ones (max value)
+   logic 		  XNormE;                             // is normal
+   logic 		  FmtQ;
+   logic 		  FOpCtrlQ;     
 
-     // D/E pipeline registers
-     flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
-     flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
-     flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
-     flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, 
-                             {Adr1E, Adr2E, Adr3E});
-     flopenrc #(17) DECtrlReg3(clk, reset, FlushE, ~StallE, 
-			       {FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD, FDivStartD},
-			       {FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE, FDivStartE});
+   // result and flag signals
+   logic [63:0] 	  FDivResM, FDivResW;                 // divide/squareroot result
+   logic [4:0] 	  FDivFlgM;                 // divide/squareroot flags  
+   logic [63:0] 	  FMAResM, FMAResW;                   // FMA/multiply result
+   logic [4:0] 	  FMAFlgM;                   // FMA/multiply result	
+   logic [63:0] 	  ReadResW;                           // read result (load instruction)
+   logic [63:0] 	  CvtFpResE;    // add/FP -> FP convert result
+   logic [4:0] 	  CvtFpFlgE;    // add/FP -> FP convert flags
+   logic [63:0] 	  CvtResE;                   // FP <-> int convert result
+   logic [4:0] 	  CvtFlgE;                   // FP <-> int convert flags //*** trim this	
+   logic [63:0] 	  ClassResE;               // classify result
+   logic [63:0] 	  CmpResE;                   // compare result
+   logic 		  CmpNVE;                     // compare invalid flag (Not Valid)     
+   logic [63:0] 	  SgnResE;                   // sign injection result
+   logic 		  SgnNVE;                     // sign injection invalid flag (Not Valid)     
+   logic [63:0] 	  FResE, FResM, FResW;                // selected result that is ready in the memory stage
+   logic [4:0] 	  FFlgE, FFlgM;                       // selected flag that is ready in the memory stage     
+   logic [`XLEN-1:0] 	  FIntResE;     
+   logic [63:0] 	  FPUResultW;                         // final FP result being written to the FP register     
+   // other signals
+   logic 		  FDivSqrtDoneE;                      // is divide done
+   logic [63:0] 	  DivInput1E, DivInput2E;             // inputs to divide/squareroot unit
+   logic 		  load_preload;                       // enable for FF on fpdivsqrt     
+   logic [63:0] 	  AlignedSrcAE;                       // align SrcA to the floating point format
 
-     // EXECUTION STAGE
-     // Hazard unit for FPU  
-     //    - determines if any forwarding or stalls are needed
-     fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResultSelM, 
-                     .FStallD, .FForwardXE, .FForwardYE, .FForwardZE);
-     
-     // forwarding muxs
-     mux3  #(64)  fxemux (FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
-     mux3  #(64)  fyemux (FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE);
-     mux3  #(64)  fzemux (FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
-     mux3  #(64)  fyaddmux (FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0}, 
-			    {2'b0, {10{1'b1}}, 52'b0}, 
-			    {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)}, 
-			    FSrcYE); // Force Z to be 0 for multiply instructions
-     // Force Z to be 0 for multiply instructions     
-     mux3  #(64)  fzmulmux (FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
-       
-     // unpacking unit
-     //    - splits FP inputs into their various parts
-     //    - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
-     unpacking unpacking (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, 
-			  .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, 
-			  .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, 
-			  .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
-     
-     // FMA
-     //   - two stage FMA
-     //   - execute stage - multiplication and addend shifting
-     //   - memory stage  - addition and rounding
-     //   - handles FMA and multiply instructions
-     fma fma (.clk, .reset, .FlushM, .StallM, 
-	      .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, 
-	      .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
-	      .XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, 
-	      .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, 
-	      .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
-	      .FOpCtrlE,
-	      .FmtE, .FmtM, .FrmM, 
-	      .FMAFlgM, .FMAResM);
-     
-     // fpdivsqrt using Goldschmidt's iteration
-     flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
-				.clear(FDivSqrtDoneE), .en(load_preload),
-				.reset(reset),  .clk(clk));
-     flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
-			      .clear(FDivSqrtDoneE), .en(load_preload),
-			      .reset(reset),  .clk(clk));
-     flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}), 
-			     .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}),
-			     .clear(FDivSqrtDoneE), .en(load_preload),
-			     .reset(reset),  .clk(clk));
-     fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ), 
-			  .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1),
-			  .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
-			  .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
+   // DECODE STAGE
 
-     // convert from signle to double and vice versa
-     cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
-     
-     // compare unit
-     //    - computation is done in one stage
-     //    - writes to FP file durring min/max instructions
-     //    - other comparisons write a 1 or 0 to the integer register
-     fcmp fcmp (.op1({XSgnE,XExpE,XManE[`NF-1:0]}), .op2({YSgnE,YExpE,YManE[`NF-1:0]}), 
-		.FSrcXE, .FSrcYE, .FOpCtrlE, 
-		.FmtE, .XNaNE, .YNaNE, .XZeroE, .YZeroE, 
-		.Invalid(CmpNVE), .CmpResE);
-     
-     // sign injection unit
-     fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE,
-		.SgnNVE, .SgnResE);
-     
-     // classify
-     fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, 
-			  .XSNaNE, .ClassResE);
+   // calculate FP control signals
+   fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .FRM_REGW,
+      .IllegalFPUInstrD, .FRegWriteD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD, 
+      .FIntResSelD, .FmtD, .FrmD, .FWriteIntD);
 
-     // Convert
-     fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
-		.CvtResE, .CvtFlgE);
-     
-     // data to be stored in memory - to IEU
-     //    - FP uses NaN-blocking format
-     //        - if there are any unsused bits the most significant bits are filled with 1s
-     assign FWriteDataE = FSrcYE[`XLEN-1:0];     
-     
-     // Align SrcA to MSB when single precicion
-     mux2  #(64)  SrcAMux({{32{1'b1}}, ForwardedSrcAE[31:0]}, {{64-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
-     
-     // select a result that may be written to the FP register
-     mux5  #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE);
-     mux5  #(5)  FFlgMux(5'b0, {4'b0, SgnNVE}, {4'b0, CmpNVE}, CvtFlgE, CvtFpFlgE, FResSelE, FFlgE);
-     
-     // select the result that may be written to the integer register - to IEU
-     mux4  #(`XLEN)  IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0], 
-			       CvtResE[`XLEN-1:0], FIntResSelE, FIntResE);
-     
-     // E/M pipe registers
+   // FP register file
+   fregfile fregfile (.clk, .reset, .we4(FRegWriteW),
+      .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), 
+      .a4(RdW), .wd4(FPUResultW),
+      .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D));	
 
-     // flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM);
-     flopenrc #(65) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM});
-     flopenrc #(65) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM});
-     flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM});
-     flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM, 
-			      {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
-			      {XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});     
-     flopenrc #(64) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM); 
-     flopenrc #(5)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, FFlgE, FFlgM);      
-     flopenrc #(`XLEN) EMRegSgnRes (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
-     flopenrc #(7) EMCtrlReg (clk, reset, FlushM, ~StallM,
-			       {FRegWriteE, FResultSelE, FrmE, FmtE},
-			       {FRegWriteM, FResultSelM, FrmM, FmtM});
-     
-     // BEGIN MEMORY STAGE
-     
-     // FPU flag selection - to privileged
-     mux4  #(5)  FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
-  
-     // M/W pipe registers
-     flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); 
-     flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); 
-     flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
-     flopenrc #(4)  MWCtrlReg(clk, reset, FlushW, ~StallW,
-			      {FRegWriteM, FResultSelM, FmtM},
-			      {FRegWriteW, FResultSelW, FmtW});
-     
-     // BEGIN WRITEBACK STAGE
-     
-     // put ReadData into NaN-blocking format
-     //    - if there are any unsused bits the most significant bits are filled with 1s
-     //    - for load instruction
-     mux2  #(64)  ReadResMux ({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
-     
-     // select the result to be written to the FP register
-     mux4  #(64)  FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW);
+   // D/E pipeline registers
+   flopenrc #(64) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E);
+   flopenrc #(64) DEReg2(clk, reset, FlushE, ~StallE, FRD2D, FRD2E);
+   flopenrc #(64) DEReg3(clk, reset, FlushE, ~StallE, FRD3D, FRD3E);
+   flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, 
+                           {Adr1E, Adr2E, Adr3E});
+   flopenrc #(17) DECtrlReg3(clk, reset, FlushE, ~StallE, 
+               {FRegWriteD, FResultSelD, FResSelD, FIntResSelD, FrmD, FmtD, FOpCtrlD, FWriteIntD, FDivStartD},
+               {FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, FOpCtrlE, FWriteIntE, FDivStartE});
 
-  end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
-     assign FStallD = 0;
-     assign FWriteIntE = 0; 
-     assign FWriteDataE = 0;
-     assign FIntResM = 0;
-     assign FDivBusyE = 0;
-     assign IllegalFPUInstrD = 1;
-     assign SetFflagsM = 0;
-  end
-  endgenerate 
-   
+   // EXECUTION STAGE
+   // Hazard unit for FPU  
+   //    - determines if any forwarding or stalls are needed
+   fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResultSelM, 
+                  .FStallD, .FForwardXE, .FForwardYE, .FForwardZE);
+
+   // forwarding muxs
+   mux3  #(64)  fxemux (FRD1E, FPUResultW, FResM, FForwardXE, FSrcXE);
+   mux3  #(64)  fyemux (FRD2E, FPUResultW, FResM, FForwardYE, FPreSrcYE);
+   mux3  #(64)  fzemux (FRD3E, FPUResultW, FResM, FForwardZE, FPreSrcZE);
+   mux3  #(64)  fyaddmux (FPreSrcYE, {{32{1'b1}}, 2'b0, {7{1'b1}}, 23'b0}, 
+            {2'b0, {10{1'b1}}, 52'b0}, 
+            {FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01), ~FmtE&FOpCtrlE[2]&FOpCtrlE[1]&(FResultSelE==2'b01)}, 
+            FSrcYE); // Force Z to be 0 for multiply instructions
+   // Force Z to be 0 for multiply instructions     
+   mux3  #(64)  fzmulmux (FPreSrcZE, 64'b0, FPreSrcYE, {FOpCtrlE[2]&FOpCtrlE[1], FOpCtrlE[2]&~FOpCtrlE[1]}, FSrcZE);
+      
+   // unpacking unit
+   //    - splits FP inputs into their various parts
+   //    - does some classifications (SNaN, NaN, Denorm, Norm, Zero, Infifnity)
+   unpacking unpacking (.X(FSrcXE), .Y(FSrcYE), .Z(FSrcZE), .FOpCtrlE, .FmtE, 
+         .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, 
+         .XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE, 
+         .XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
+
+   // FMA
+   //   - two stage FMA
+   //   - execute stage - multiplication and addend shifting
+   //   - memory stage  - addition and rounding
+   //   - handles FMA and multiply instructions
+   fma fma (.clk, .reset, .FlushM, .StallM, 
+      .XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE, 
+      .XDenormE, .YDenormE, .ZDenormE, .XZeroE, .YZeroE, .ZZeroE,
+      .XSgnM, .YSgnM, .XExpM, .YExpM, .ZExpM, .XManM, .YManM, .ZManM, 
+      .XNaNM, .YNaNM, .ZNaNM, .XZeroM, .YZeroM, .ZZeroM, 
+      .XInfM, .YInfM, .ZInfM, .XSNaNM, .YSNaNM, .ZSNaNM,
+      .FOpCtrlE,
+      .FmtE, .FmtM, .FrmM, 
+      .FMAFlgM, .FMAResM);
+
+   // fpdivsqrt using Goldschmidt's iteration
+   flopenrc #(64) reg_input1 (.d({XSgnE, XExpE, XManE[51:0]}), .q(DivInput1E),
+         .clear(FDivSqrtDoneE), .en(load_preload),
+         .reset(reset),  .clk(clk));
+   flopenrc #(64) reg_input2 (.d({YSgnE, YExpE, YManE[51:0]}), .q(DivInput2E),
+            .clear(FDivSqrtDoneE), .en(load_preload),
+            .reset(reset),  .clk(clk));
+   flopenrc #(8) reg_input3 (.d({XNaNE, YNaNE, XInfE, YInfE, XZeroE, YZeroE, FmtE, FOpCtrlE[0]}), 
+            .q({XNaNQ, YNaNQ, XInfQ, YInfQ, XZeroQ, YZeroQ, FmtQ, FOpCtrlQ}),
+            .clear(FDivSqrtDoneE), .en(load_preload),
+            .reset(reset),  .clk(clk));
+   fpdiv_pipe fdivsqrt (.op1(DivInput1E), .op2(DivInput2E), .rm(FrmE[1:0]), .op_type(FOpCtrlQ), 
+         .reset, .clk(clk), .start(FDivStartE), .P(~FmtQ), .OvEn(1'b1), .UnEn(1'b1),
+         .XNaNQ, .YNaNQ, .XInfQ, .YInfQ, .XZeroQ, .YZeroQ, .load_preload,
+         .FDivBusyE, .done(FDivSqrtDoneE), .AS_Result(FDivResM), .Flags(FDivFlgM));
+
+   // convert from signle to double and vice versa
+   cvtfp cvtfp (.XExpE, .XManE, .XSgnE, .XZeroE, .XDenormE, .XInfE, .XNaNE, .XSNaNE, .FrmE, .FmtE, .CvtFpResE, .CvtFpFlgE);
+
+   // compare unit
+   //    - computation is done in one stage
+   //    - writes to FP file durring min/max instructions
+   //    - other comparisons write a 1 or 0 to the integer register
+   fcmp fcmp (.op1({XSgnE,XExpE,XManE[`NF-1:0]}), .op2({YSgnE,YExpE,YManE[`NF-1:0]}), 
+   .FSrcXE, .FSrcYE, .FOpCtrlE, 
+   .FmtE, .XNaNE, .YNaNE, .XZeroE, .YZeroE, 
+   .Invalid(CmpNVE), .CmpResE);
+
+   // sign injection unit
+   fsgn fsgn (.SgnOpCodeE(FOpCtrlE[1:0]), .XSgnE, .YSgnE, .FSrcXE, .FmtE, .XExpMaxE,
+   .SgnNVE, .SgnResE);
+
+   // classify
+   fclassify fclassify (.XSgnE, .XDenormE, .XZeroE, .XNaNE, .XInfE, .XNormE, 
+         .XSNaNE, .ClassResE);
+
+   // Convert
+   fcvt fcvt (.XSgnE, .XExpE, .XManE, .XZeroE, .XNaNE, .XInfE, .XDenormE, .BiasE, .ForwardedSrcAE, .FOpCtrlE, .FmtE, .FrmE,
+   .CvtResE, .CvtFlgE);
+
+   // data to be stored in memory - to IEU
+   //    - FP uses NaN-blocking format
+   //        - if there are any unsused bits the most significant bits are filled with 1s
+   assign FWriteDataE = FSrcYE[`XLEN-1:0];     
+
+   // Align SrcA to MSB when single precicion
+   mux2  #(64)  SrcAMux({{32{1'b1}}, ForwardedSrcAE[31:0]}, {{64-`XLEN{1'b1}}, ForwardedSrcAE}, FmtE, AlignedSrcAE);
+
+   // select a result that may be written to the FP register
+   mux5  #(64) FResMux(AlignedSrcAE, SgnResE, CmpResE, CvtResE, CvtFpResE, FResSelE, FResE);
+   mux5  #(5)  FFlgMux(5'b0, {4'b0, SgnNVE}, {4'b0, CmpNVE}, CvtFlgE, CvtFpFlgE, FResSelE, FFlgE);
+
+   // select the result that may be written to the integer register - to IEU
+   mux4  #(`XLEN)  IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0], 
+               CvtResE[`XLEN-1:0], FIntResSelE, FIntResE);
+
+   // E/M pipe registers
+
+   // flopenrc #(64) EMFpReg1(clk, reset, FlushM, ~StallM, FSrcXE, FSrcXM);
+   flopenrc #(65) EMFpReg2 (clk, reset, FlushM, ~StallM, {XSgnE,XExpE,XManE}, {XSgnM,XExpM,XManM});
+   flopenrc #(65) EMFpReg3 (clk, reset, FlushM, ~StallM, {YSgnE,YExpE,YManE}, {YSgnM,YExpM,YManM});
+   flopenrc #(64) EMFpReg4 (clk, reset, FlushM, ~StallM, {ZExpE,ZManE}, {ZExpM,ZManM});
+   flopenrc #(12) EMFpReg5 (clk, reset, FlushM, ~StallM, 
+            {XZeroE, YZeroE, ZZeroE, XInfE, YInfE, ZInfE, XNaNE, YNaNE, ZNaNE, XSNaNE, YSNaNE, ZSNaNE},
+            {XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM});     
+   flopenrc #(64) EMRegCmpRes (clk, reset, FlushM, ~StallM, FResE, FResM); 
+   flopenrc #(5)  EMRegCmpFlg (clk, reset, FlushM, ~StallM, FFlgE, FFlgM);      
+   flopenrc #(`XLEN) EMRegSgnRes (clk, reset, FlushM, ~StallM, FIntResE, FIntResM);
+   flopenrc #(7) EMCtrlReg (clk, reset, FlushM, ~StallM,
+               {FRegWriteE, FResultSelE, FrmE, FmtE},
+               {FRegWriteM, FResultSelM, FrmM, FmtM});
+
+   // BEGIN MEMORY STAGE
+
+   // FPU flag selection - to privileged
+   mux4  #(5)  FPUFlgMux (5'b0, FMAFlgM, FDivFlgM, FFlgM, FResultSelM, SetFflagsM);
+
+   // M/W pipe registers
+   flopenrc #(64) MWRegFma(clk, reset, FlushW, ~StallW, FMAResM, FMAResW); 
+   flopenrc #(64) MWRegDiv(clk, reset, FlushW, ~StallW, FDivResM, FDivResW); 
+   flopenrc #(64) MWRegClass(clk, reset, FlushW, ~StallW, FResM, FResW);
+   flopenrc #(4)  MWCtrlReg(clk, reset, FlushW, ~StallW,
+            {FRegWriteM, FResultSelM, FmtM},
+            {FRegWriteW, FResultSelW, FmtW});
+
+   // BEGIN WRITEBACK STAGE
+
+   // put ReadData into NaN-blocking format
+   //    - if there are any unsused bits the most significant bits are filled with 1s
+   //    - for load instruction
+   mux2  #(64)  ReadResMux ({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
+
+   // select the result to be written to the FP register
+   mux4  #(64)  FPUResultMux (ReadResW, FMAResW, FDivResW, FResW, FResultSelW, FPUResultW);
 endmodule // fpu
diff --git a/wally-pipelined/src/muldiv/muldiv.sv b/wally-pipelined/src/muldiv/muldiv.sv
index b3bf4e83..a1e76616 100644
--- a/wally-pipelined/src/muldiv/muldiv.sv
+++ b/wally-pipelined/src/muldiv/muldiv.sv
@@ -40,65 +40,50 @@ module muldiv (
 	       input logic 		StallM, StallW, FlushM, FlushW 
 	       );
 
-   generate
-      if (`M_SUPPORTED) begin
-	 logic [`XLEN-1:0] MulDivResultM;
-	 logic [`XLEN-1:0] PrelimResultM;
-	 logic [`XLEN-1:0] QuotM, RemM;
-	 logic [`XLEN*2-1:0] ProdM; 
+	logic [`XLEN-1:0] MulDivResultM;
+	logic [`XLEN-1:0] PrelimResultM;
+	logic [`XLEN-1:0] QuotM, RemM;
+	logic [`XLEN*2-1:0] ProdM; 
 
-	 logic 		     DivE;
-	 logic 		     DivSignedE;	
-	 logic           W64M; 
-	 
-	 // Multiplier
-	 mul mul(
-	 .clk, .reset,
-  	 .StallM, .FlushM,
-	    // .SrcAE, .SrcBE,
-	 .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-	 .Funct3E,
-  	 .ProdM
-	 );
+	logic 		     DivE;
+	logic 		     DivSignedE;	
+	logic           W64M; 
 
-	 // Divide
-	 // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
-	 assign DivE = MulDivE & Funct3E[2];
-	 assign DivSignedE = ~Funct3E[0];
-	 intdivrestoring div(.clk, .reset, .StallM,
-	   .DivSignedE, .W64E, .DivE, .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
-	 	 
-	 // Result multiplexer
-	 always_comb
-           case (Funct3M)	   
-             3'b000: PrelimResultM = ProdM[`XLEN-1:0];
-             3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
-             3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
-             3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
-             3'b100: PrelimResultM = QuotM;
-             3'b101: PrelimResultM = QuotM;
-             3'b110: PrelimResultM = RemM;
-             3'b111: PrelimResultM = RemM;
-           endcase 
-	 
-	 // Handle sign extension for W-type instructions
-	 flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M);
-	 if (`XLEN == 64) begin // RV64 has W-type instructions
-            assign MulDivResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM;
-	 end else begin // RV32 has no W-type instructions
-            assign MulDivResultM = PrelimResultM;
-	 end
+	// Multiplier
+	mul mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
 
-     // Writeback stage pipeline register
+	// Divide
+	// Start a divide when a new division instruction is received and the divider isn't already busy or finishing
+	assign DivE = MulDivE & Funct3E[2];
+	assign DivSignedE = ~Funct3E[0];
+	intdivrestoring div(.clk, .reset, .StallM, .DivSignedE, .W64E, .DivE, 
+	                    .ForwardedSrcAE, .ForwardedSrcBE, .DivBusyE, .QuotM, .RemM);
+		
+	// Result multiplexer
+	always_comb
+		case (Funct3M)	   
+			3'b000: PrelimResultM = ProdM[`XLEN-1:0];
+			3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
+			3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
+			3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN];
+			3'b100: PrelimResultM = QuotM;
+			3'b101: PrelimResultM = QuotM;
+			3'b110: PrelimResultM = RemM;
+			3'b111: PrelimResultM = RemM;
+		endcase 
 
-	 flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW);	 
-
-      end else begin // no M instructions supported
-	 	assign MulDivResultW = 0; 
-		assign DivBusyE = 0;
-      end
-   endgenerate
+	// Handle sign extension for W-type instructions
+	flopenrc #(1) W64MReg(clk, reset, FlushM, ~StallM, W64E, W64M);
+	generate
+		if (`XLEN == 64) begin:resmux // RV64 has W-type instructions
+			assign MulDivResultM = W64M ? {{32{PrelimResultM[31]}}, PrelimResultM[31:0]} : PrelimResultM;
+		end else begin:resmux // RV32 has no W-type instructions
+			assign MulDivResultM = PrelimResultM;
+		end
+	endgenerate
 
+	// Writeback stage pipeline register
+	flopenrc #(`XLEN) MulDivResultWReg(clk, reset, FlushW, ~StallW, MulDivResultM, MulDivResultW);	 
 endmodule // muldiv
 
 
diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv
index 440045d3..63d0a583 100644
--- a/wally-pipelined/src/privileged/csr.sv
+++ b/wally-pipelined/src/privileged/csr.sv
@@ -86,76 +86,48 @@ module csr #(parameter
   logic        IllegalCSRCAccessM, IllegalCSRMAccessM, IllegalCSRSAccessM, IllegalCSRUAccessM, IllegalCSRNAccessM, InsufficientCSRPrivilegeM;
   logic IllegalCSRMWriteReadonlyM;
   
-  generate
-    if (`ZICSR_SUPPORTED) begin
-      // modify CSRs
-      always_comb begin
-        // Choose either rs1 or uimm[4:0] as source
-        CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
-        // Compute AND/OR modification
-        CSRRWM = CSRSrcM;
-        CSRRSM = CSRReadValM | CSRSrcM;
-        CSRRCM = CSRReadValM & ~CSRSrcM;
-        case (InstrM[13:12])
-          2'b01:  CSRWriteValM = CSRRWM;
-          2'b10:  CSRWriteValM = CSRRSM;
-          2'b11:  CSRWriteValM = CSRRCM;
-          default: CSRWriteValM = CSRReadValM;
-        endcase
-      end
+  // modify CSRs
+  always_comb begin
+    // Choose either rs1 or uimm[4:0] as source
+    CSRSrcM = InstrM[14] ? {{(`XLEN-5){1'b0}}, InstrM[19:15]} : SrcAM;
+    // Compute AND/OR modification
+    CSRRWM = CSRSrcM;
+    CSRRSM = CSRReadValM | CSRSrcM;
+    CSRRCM = CSRReadValM & ~CSRSrcM;
+    case (InstrM[13:12])
+      2'b01:  CSRWriteValM = CSRRWM;
+      2'b10:  CSRWriteValM = CSRRSM;
+      2'b11:  CSRWriteValM = CSRRCM;
+      default: CSRWriteValM = CSRReadValM;
+    endcase
+  end
 
-      // write CSRs
-      assign CSRAdrM = InstrM[31:20];
-      assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
-      assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
-      assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
-      assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
-      assign CSRMWriteM = CSRWriteM && (PrivilegeModeW == `M_MODE);
-      assign CSRSWriteM = CSRWriteM && (|PrivilegeModeW);
-      assign CSRUWriteM = CSRWriteM;  
+  // write CSRs
+  assign CSRAdrM = InstrM[31:20];
+  assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
+  assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
+  assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
+  assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
+  assign CSRMWriteM = CSRWriteM && (PrivilegeModeW == `M_MODE);
+  assign CSRSWriteM = CSRWriteM && (|PrivilegeModeW);
+  assign CSRUWriteM = CSRWriteM;  
 
-      csri  csri(.*);
-      csrsr csrsr(.*);
-      csrc  counters(.*);
-      csrm  csrm(.*); // Machine Mode CSRs
-      csrs  csrs(.*);
-      csrn  csrn(.CSRNWriteM(CSRUWriteM), .*);  // User Mode Exception Registers
-      csru  csru(.*); // Floating Point Flags are part of User MOde
+  csri  csri(.*);
+  csrsr csrsr(.*);
+  csrc  counters(.*);
+  csrm  csrm(.*); // Machine Mode CSRs
+  csrs  csrs(.*);
+  csrn  csrn(.CSRNWriteM(CSRUWriteM), .*);  // User Mode Exception Registers
+  csru  csru(.*); // Floating Point Flags are part of User MOde
 
-      // merge CSR Reads
-      assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; 
-      // *** add W stall 2/22/21 dh to try fixing memory stalls
-//      floprc #(`XLEN) CSRValWReg(clk, reset, FlushW, CSRReadValM, CSRReadValW);
-      flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
+  // merge CSR Reads
+  assign CSRReadValM = CSRUReadValM | CSRSReadValM | CSRMReadValM | CSRCReadValM | CSRNReadValM; 
+  flopenrc #(`XLEN) CSRValWReg(clk, reset, FlushW, ~StallW, CSRReadValM, CSRReadValW);
 
-      // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
-      assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 && PrivilegeModeW != `M_MODE) ||
-                                        (CSRAdrM[9:8] == 2'b01 && PrivilegeModeW == `U_MODE);
-      assign IllegalCSRAccessM = ((IllegalCSRCAccessM && IllegalCSRMAccessM && 
-        IllegalCSRSAccessM && IllegalCSRUAccessM  && IllegalCSRNAccessM ||
-        InsufficientCSRPrivilegeM) && CSRReadM) || IllegalCSRMWriteReadonlyM;
-    end else begin // CSRs not implemented
-      assign STATUS_MPP = 2'b11;
-      assign STATUS_SPP = 2'b0;
-      assign STATUS_TSR = 0;
-      assign MEPC_REGW = 0;
-      assign SEPC_REGW = 0;
-      assign UEPC_REGW = 0;
-      assign UTVEC_REGW = 0;
-      assign STVEC_REGW = 0;
-      assign MTVEC_REGW = 0;
-      assign MEDELEG_REGW = 0;
-      assign MIDELEG_REGW = 0;
-      assign SEDELEG_REGW = 0;
-      assign SIDELEG_REGW = 0;
-      assign SATP_REGW = 0;
-      assign MIP_REGW = 0;
-      assign MIE_REGW = 0;
-      assign STATUS_MIE = 0;
-      assign STATUS_SIE = 0;
-      assign FRM_REGW = 0;
-      assign CSRReadValM = 0;
-      assign IllegalCSRAccessM = CSRReadM;
-    end
-  endgenerate
+  // merge illegal accesses: illegal if none of the CSR addresses is legal or privilege is insufficient
+  assign InsufficientCSRPrivilegeM = (CSRAdrM[9:8] == 2'b11 && PrivilegeModeW != `M_MODE) ||
+                                    (CSRAdrM[9:8] == 2'b01 && PrivilegeModeW == `U_MODE);
+  assign IllegalCSRAccessM = ((IllegalCSRCAccessM && IllegalCSRMAccessM && 
+    IllegalCSRSAccessM && IllegalCSRUAccessM  && IllegalCSRNAccessM ||
+    InsufficientCSRPrivilegeM) && CSRReadM) || IllegalCSRMWriteReadonlyM;
 endmodule
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index c5bc8a45..c84a9d27 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -239,8 +239,6 @@ module privileged (
             .ExceptionM,
             .PendingInterruptM,
             .PrivilegedNextPCM, .CauseM, .NextFaultMtvalM);
-
-
 endmodule
 
 
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 7be5b8c6..304ac1a9 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -198,7 +198,6 @@ module wallypipelinedhart (
 	  
 	  ); // instruction fetch unit: PC, branch prediction, instruction cache
     
-
   ieu ieu(
      .clk, .reset,
 
@@ -276,7 +275,7 @@ module wallypipelinedhart (
 	.LSUStall);                     // change to LSUStall
 
 
-  
+   // *** Ross: please make EBU conditional when only supporting internal memories
 
   ahblite ebu(// IFU connections
      .clk, .reset,
@@ -295,22 +294,7 @@ module wallypipelinedhart (
      .HWRITED);
 
   
-  muldiv mdu(
-     .clk, .reset,
-	// Execute Stage interface
-	//   .SrcAE, .SrcBE,
-	.ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
-	.Funct3E, .Funct3M,
-     .MulDivE, .W64E,
-	// Writeback stage
-     .MulDivResultW,
-     // Divide Done
-	.DivBusyE, 
-	// hazards
-	.StallM, .StallW, .FlushM, .FlushW 
-  ); // multiply and divide unit
-  
-  hazard     hzu(
+   hazard     hzu(
      .BPPredWrongE, .CSRWritePendingDEM, .RetM, .TrapM,
      .LoadStallD, .StoreStallD, .MulDivStallD, .CSRRdStallD,
      .LSUStall, .ICacheStallF,
@@ -323,57 +307,89 @@ module wallypipelinedhart (
 	.FlushF, .FlushD, .FlushE, .FlushM, .FlushW
      );	// global stall and flush control
 
-  // Priveleged block operates in M and W stages, handling CSRs and exceptions
-  privileged priv(
-     .clk, .reset,
-     .FlushD, .FlushE, .FlushM, .FlushW, 
-     .StallD, .StallE, .StallM, .StallW,
-     .CSRReadM, .CSRWriteM, .SrcAM, .PCM,
-     .InstrM, .CSRReadValW, .PrivilegedNextPCM,
-     .RetM, .TrapM, 
-     .ITLBFlushF, .DTLBFlushM,
-     .InstrValidM, .CommittedM,
-     .FRegWriteM, .LoadStallD,
-     .BPPredDirWrongM, .BTBPredPCWrongM,
-     .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
-     .InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
-     .ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
-     .WalkerInstrPageFaultF, .WalkerLoadPageFaultM, .WalkerStorePageFaultM,
-     .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
-     .LoadMisalignedFaultM, .StoreMisalignedFaultM,
-     .TimerIntM, .ExtIntM, .SwIntM,
-     .MTIME_CLINT, .MTIMECMP_CLINT,
-     .InstrMisalignedAdrM, .MemAdrM,
-     .SetFflagsM,
-     // Trap signals from pmp/pma in mmu
-     // *** do these need to be split up into one for dmem and one for ifu?
-     // instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
-     .InstrAccessFaultF, .LoadAccessFaultM, .StoreAccessFaultM,
-     .ExceptionM, .PendingInterruptM, .IllegalFPUInstrE,
-     .PrivilegeModeW, .SATP_REGW,
-     .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
-     .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-     .FRM_REGW,.BreakpointFaultM, .EcallFaultM
-  );
-  
+   generate
+      if (`ZICSR_SUPPORTED) begin:priv
+         privileged priv(
+            .clk, .reset,
+            .FlushD, .FlushE, .FlushM, .FlushW, 
+            .StallD, .StallE, .StallM, .StallW,
+            .CSRReadM, .CSRWriteM, .SrcAM, .PCM,
+            .InstrM, .CSRReadValW, .PrivilegedNextPCM,
+            .RetM, .TrapM, 
+            .ITLBFlushF, .DTLBFlushM,
+            .InstrValidM, .CommittedM,
+            .FRegWriteM, .LoadStallD,
+            .BPPredDirWrongM, .BTBPredPCWrongM,
+            .RASPredPCWrongM, .BPPredClassNonCFIWrongM,
+            .InstrClassM, .DCacheMiss, .DCacheAccess, .PrivilegedM,
+            .ITLBInstrPageFaultF, .DTLBLoadPageFaultM, .DTLBStorePageFaultM,
+            .WalkerInstrPageFaultF, .WalkerLoadPageFaultM, .WalkerStorePageFaultM,
+            .InstrMisalignedFaultM, .IllegalIEUInstrFaultD, .IllegalFPUInstrD,
+            .LoadMisalignedFaultM, .StoreMisalignedFaultM,
+            .TimerIntM, .ExtIntM, .SwIntM,
+            .MTIME_CLINT, .MTIMECMP_CLINT,
+            .InstrMisalignedAdrM, .MemAdrM,
+            .SetFflagsM,
+            // Trap signals from pmp/pma in mmu
+            // *** do these need to be split up into one for dmem and one for ifu?
+            // instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
+            .InstrAccessFaultF, .LoadAccessFaultM, .StoreAccessFaultM,
+            .ExceptionM, .PendingInterruptM, .IllegalFPUInstrE,
+            .PrivilegeModeW, .SATP_REGW,
+            .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
+            .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
+            .FRM_REGW,.BreakpointFaultM, .EcallFaultM
+         );
+      end else begin
+         assign CSRReadValW = 0;
+         assign PrivilegedNextPCM = 0;
+         assign RetM = 0;
+         assign TrapM = 0;
+         assign ITLBFlushF = 0;
+         assign DTLBFlushM = 0;
+      end
+      if (`M_SUPPORTED) begin:mdu
+         muldiv mdu(
+            .clk, .reset,
+            .ForwardedSrcAE, .ForwardedSrcBE, 
+            .Funct3E, .Funct3M, .MulDivE, .W64E,
+            .MulDivResultW, .DivBusyE, 
+            .StallM, .StallW, .FlushM, .FlushW 
+         ); 
+      end else begin // no M instructions supported
+         assign MulDivResultW = 0; 
+         assign DivBusyE = 0;
+      end
 
-  fpu fpu(
-     .clk, .reset,
-     .FRM_REGW, // Rounding mode from CSR
-     .InstrD, // instruction from IFU
-     .ReadDataW,// Read data from memory
-     .ForwardedSrcAE, // Integer input being processed (from IEU)
-     .StallE, .StallM, .StallW, // stall signals from HZU
-     .FlushE, .FlushM, .FlushW, // flush signals from HZU
-     .RdM, .RdW, // which FP register to write to (from IEU)
-     .FRegWriteM, // FP register write enable
-     .FStallD, // Stall the decode stage
-     .FWriteIntE, // integer register write enable
-     .FWriteDataE, // Data to be written to memory
-     .FIntResM, // data to be written to integer register
-     .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
-     .IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
-     .SetFflagsM        // FPU flags (to privileged unit)
-  ); // floating point unit
-  
+      if (`F_SUPPORTED) begin:fpu
+         fpu fpu(
+            .clk, .reset,
+            .FRM_REGW, // Rounding mode from CSR
+            .InstrD, // instruction from IFU
+            .ReadDataW,// Read data from memory
+            .ForwardedSrcAE, // Integer input being processed (from IEU)
+            .StallE, .StallM, .StallW, // stall signals from HZU
+            .FlushE, .FlushM, .FlushW, // flush signals from HZU
+            .RdM, .RdW, // which FP register to write to (from IEU)
+            .FRegWriteM, // FP register write enable
+            .FStallD, // Stall the decode stage
+            .FWriteIntE, // integer register write enable
+            .FWriteDataE, // Data to be written to memory
+            .FIntResM, // data to be written to integer register
+            .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
+            .IllegalFPUInstrD, // Is the instruction an illegal fpu instruction
+            .SetFflagsM        // FPU flags (to privileged unit)
+         ); // floating point unit
+      end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
+         assign FStallD = 0;
+         assign FWriteIntE = 0; 
+         assign FWriteDataE = 0;
+         assign FIntResM = 0;
+         assign FDivBusyE = 0;
+         assign IllegalFPUInstrD = 1;
+         assign SetFflagsM = 0;
+      end
+
+   endgenerate
+  // Priveleged block operates in M and W stages, handling CSRs and exceptions  
 endmodule
diff --git a/wally-pipelined/src/sdc/tb/ram2sdLoad.py b/wally-pipelined/testbench/sdc/ram2sdLoad.py
similarity index 100%
rename from wally-pipelined/src/sdc/tb/ram2sdLoad.py
rename to wally-pipelined/testbench/sdc/ram2sdLoad.py
diff --git a/wally-pipelined/src/sdc/tb/ramdisk2.hex b/wally-pipelined/testbench/sdc/ramdisk2.hex
similarity index 100%
rename from wally-pipelined/src/sdc/tb/ramdisk2.hex
rename to wally-pipelined/testbench/sdc/ramdisk2.hex
diff --git a/wally-pipelined/src/sdc/tb/run_tb.do b/wally-pipelined/testbench/sdc/run_tb.do
similarity index 100%
rename from wally-pipelined/src/sdc/tb/run_tb.do
rename to wally-pipelined/testbench/sdc/run_tb.do
diff --git a/wally-pipelined/src/sdc/tb/sd_top_tb.sv b/wally-pipelined/testbench/sdc/sd_top_tb.sv
similarity index 100%
rename from wally-pipelined/src/sdc/tb/sd_top_tb.sv
rename to wally-pipelined/testbench/sdc/sd_top_tb.sv
diff --git a/wally-pipelined/src/sdc/tb/wave.do b/wally-pipelined/testbench/sdc/wave.do
similarity index 100%
rename from wally-pipelined/src/sdc/tb/wave.do
rename to wally-pipelined/testbench/sdc/wave.do
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index a64ca434..41e9480b 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -174,7 +174,7 @@ module testbench();
   // Useful Aliases
   `define RF          dut.hart.ieu.dp.regf.rf
   `define PC          dut.hart.ifu.pcreg.q
-  `define CSR_BASE    dut.hart.priv.csr.genblk1
+  `define CSR_BASE    dut.hart.priv.priv.csr
   `define HPMCOUNTER  `CSR_BASE.counters.genblk1.HPMCOUNTER_REGW
   `define PMP_BASE    `CSR_BASE.csrm.genblk4
   `define PMPCFG      genblk2.PMPCFGreg.q
@@ -210,8 +210,8 @@ module testbench();
   `define STATUS_MIE  `CSR_BASE.csrsr.STATUS_MIE
   `define STATUS_SIE  `CSR_BASE.csrsr.STATUS_SIE
   `define STATUS_UIE  `CSR_BASE.csrsr.STATUS_UIE
-  `define PRIV        dut.hart.priv.privmodereg.q
-  `define INSTRET     dut.hart.priv.csr.genblk1.counters.genblk1.genblk2.INSTRETreg.q
+  `define PRIV        dut.hart.priv.priv.privmodereg.q
+  `define INSTRET     dut.hart.priv.priv.csr.counters.genblk1.genblk2.INSTRETreg.q
   // Common Macros
   `define checkCSR(CSR) \
     begin \
@@ -308,9 +308,9 @@ module testbench();
   integer ramFile;
   integer readResult;
   initial begin
-    force dut.hart.priv.SwIntM = 0;
-    force dut.hart.priv.TimerIntM = 0;
-    force dut.hart.priv.ExtIntM = 0;    
+    force dut.hart.priv.priv.SwIntM = 0;
+    force dut.hart.priv.priv.TimerIntM = 0;
+    force dut.hart.priv.priv.ExtIntM = 0;    
     $readmemh({`LINUX_TEST_VECTORS,"bootmem.txt"}, dut.uncore.bootrom.bootrom.RAM, 'h1000 >> 3);
     $readmemb(`TWO_BIT_PRELOAD, dut.hart.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
     $readmemb(`BTB_PRELOAD, dut.hart.ifu.bpred.bpred.TargetPredictor.memory.mem);
@@ -365,7 +365,7 @@ module testbench();
   // on the next falling edge the expected state is compared to the wally state.
 
   // step 0: read the expected state
-  assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.trap.InstrPageFaultM & ~dut.hart.priv.trap.InterruptM & ~dut.hart.StallM;
+  assign checkInstrM = dut.hart.ieu.InstrValidM & ~dut.hart.priv.priv.trap.InstrPageFaultM & ~dut.hart.priv.priv.trap.InterruptM & ~dut.hart.StallM;
   `define SCAN_NEW_INSTR_FROM_TRACE(STAGE) \
     // always check PC, instruction bits \
     if (checkInstrM) begin \
@@ -479,7 +479,7 @@ module testbench();
       end else begin // update MIP immediately
         $display("%tns: Updating MIP to %x",$time,NextMIPexpected);
         MIPexpected = NextMIPexpected;
-        force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
+        force dut.hart.priv.priv.csr.csri.MIP_REGW = MIPexpected;
       end
       // $display("%tn: ExpectedCSRArrayM = %p",$time,ExpectedCSRArrayM);
       // $display("%tn: ExpectedCSRArrayValueM = %p",$time,ExpectedCSRArrayValueM);
@@ -491,11 +491,11 @@ module testbench();
       // $display("%tn: ExpectedCSRArrayValueM[NumCSRM] %x",$time,ExpectedCSRArrayValueM[NumCSRM]);
     end
     if(RequestDelayedMIP & checkInstrM) begin
-      $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW);
+      $display("%tns: Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.priv.csr.csrm.MEPC_REGW);
       $display("%tns: Updating MIP to %x",$time,NextMIPexpected);
       MIPexpected = NextMIPexpected;
-      force dut.hart.priv.csr.genblk1.csri.MIP_REGW = MIPexpected;
-      $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.csr.genblk1.csrm.MEPC_REGW);
+      force dut.hart.priv.priv.csr.csri.MIP_REGW = MIPexpected;
+      $display("%tns: Finished Executing Delayed MIP. Current MEPC value is %x",$time,dut.hart.priv.priv.csr.csrm.MEPC_REGW);
       RequestDelayedMIP = 0;
     end
   end
@@ -576,7 +576,7 @@ module testbench();
         `checkEQ("PCW",PCW,ExpectedPCW)
         //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
         // compressed to uncompressed conversion
-        `checkEQ("Instr Count",dut.hart.priv.csr.genblk1.counters.genblk1.INSTRET_REGW,InstrCountW)
+        `checkEQ("Instr Count",dut.hart.priv.priv.csr.counters.genblk1.INSTRET_REGW,InstrCountW)
         #2; // delay 2 ns.
         if(`DEBUG_TRACE >= 5) begin
           $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, InstrCountW, dut.hart.ieu.dp.regf.a3, ExpectedRegAdrW);
@@ -601,19 +601,19 @@ module testbench();
         // check csr
         for(NumCSRPostWIndex = 0; NumCSRPostWIndex < NumCSRW; NumCSRPostWIndex++) begin
           case(ExpectedCSRArrayW[NumCSRPostWIndex])
-            "mhartid": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MHARTID_REGW)
-            "mstatus": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MSTATUS_REGW)
-            "mtvec":   `checkCSR(dut.hart.priv.csr.genblk1.csrm.MTVEC_REGW)
-            "mip":     `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIP_REGW)
-            "mie":     `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIE_REGW)
-            "mideleg": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MIDELEG_REGW)
-            "medeleg": `checkCSR(dut.hart.priv.csr.genblk1.csrm.MEDELEG_REGW)
-            "mepc":    `checkCSR(dut.hart.priv.csr.genblk1.csrm.MEPC_REGW)
-            "mtval":   `checkCSR(dut.hart.priv.csr.genblk1.csrm.MTVAL_REGW)
-            "sepc":    `checkCSR(dut.hart.priv.csr.genblk1.csrs.SEPC_REGW)
-            "scause":  `checkCSR(dut.hart.priv.csr.genblk1.csrs.genblk1.SCAUSE_REGW)
-            "stvec":   `checkCSR(dut.hart.priv.csr.genblk1.csrs.STVEC_REGW)
-            "stval":   `checkCSR(dut.hart.priv.csr.genblk1.csrs.genblk1.STVAL_REGW)
+            "mhartid": `checkCSR(dut.hart.priv.priv.csr.csrm.MHARTID_REGW)
+            "mstatus": `checkCSR(dut.hart.priv.priv.csr.csrm.MSTATUS_REGW)
+            "mtvec":   `checkCSR(dut.hart.priv.priv.csr.csrm.MTVEC_REGW)
+            "mip":     `checkCSR(dut.hart.priv.priv.csr.csrm.MIP_REGW)
+            "mie":     `checkCSR(dut.hart.priv.priv.csr.csrm.MIE_REGW)
+            "mideleg": `checkCSR(dut.hart.priv.priv.csr.csrm.MIDELEG_REGW)
+            "medeleg": `checkCSR(dut.hart.priv.priv.csr.csrm.MEDELEG_REGW)
+            "mepc":    `checkCSR(dut.hart.priv.priv.csr.csrm.MEPC_REGW)
+            "mtval":   `checkCSR(dut.hart.priv.priv.csr.csrm.MTVAL_REGW)
+            "sepc":    `checkCSR(dut.hart.priv.priv.csr.csrs.SEPC_REGW)
+            "scause":  `checkCSR(dut.hart.priv.priv.csr.csrs.genblk1.SCAUSE_REGW)
+            "stvec":   `checkCSR(dut.hart.priv.priv.csr.csrs.STVEC_REGW)
+            "stval":   `checkCSR(dut.hart.priv.priv.csr.csrs.genblk1.STVAL_REGW)
           endcase
         end
         if (fault == 1) begin
@@ -667,7 +667,7 @@ module testbench();
     begin
       int i;
       // Grab the SATP register from privileged unit
-      SATP = dut.hart.priv.csr.SATP_REGW;
+      SATP = dut.hart.priv.priv.csr.SATP_REGW;
       // Split the virtual address into page number segments and offset
       VPN[2] = adrIn[38:30];
       VPN[1] = adrIn[29:21];
@@ -677,7 +677,7 @@ module testbench();
       SvMode = SATP[63];
       // Only perform translation if translation is on and the processor is not
       // in machine mode
-      if (SvMode && (dut.hart.priv.PrivilegeModeW != `M_MODE)) begin
+      if (SvMode && (dut.hart.priv.priv.PrivilegeModeW != `M_MODE)) begin
         BaseAdr = SATP[43:0] << 12;
         for (i = 2; i >= 0; i--) begin
           PAdr = BaseAdr + (VPN[i] << 3);
diff --git a/wally-pipelined/testbench/testbench.sv b/wally-pipelined/testbench/testbench.sv
index 7301f454..ef0c0692 100644
--- a/wally-pipelined/testbench/testbench.sv
+++ b/wally-pipelined/testbench/testbench.sv
@@ -287,7 +287,7 @@ logic [3:0] dummy;
 
   // Termination condition
   // terminate on a specific ECALL for Imperas tests, or on a jump to self infinite loop for RISC-V Arch tests
-  assign DCacheFlushStart = dut.hart.priv.EcallFaultM && 
+  assign DCacheFlushStart = dut.hart.priv.priv.EcallFaultM && 
 			    (dut.hart.ieu.dp.regf.rf[3] == 1 || 
 			     (dut.hart.ieu.dp.regf.we3 && 
 			      dut.hart.ieu.dp.regf.a3 == 3 && 
@@ -318,7 +318,7 @@ module riscvassertions;
   initial begin
     assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64");
     assert (`DIV_BITSPERCYCLE == 1 || `DIV_BITSPERCYCLE==2 || `DIV_BITSPERCYCLE==4) else $error("Illegal number of divider bits/cycle: DIV_BITSPERCYCLE must be 1, 2, or 4");
-    assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float");
+    assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double (D) without supporting float (F)");
     assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32");
     assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
     assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled");

From 596cc4fde418b4e7624fad81ac9130afa44219b3 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 20:11:32 -0600
Subject: [PATCH 72/95] Moved convert2bin.py to the tests directory.  This file
 converts the qemu ram.txt output into a binary for copy to flash card. mv
 qemu patches to tests directory.

---
 .../linux-testgen/linux-testvectors/convert2bin.py                | 0
 .../linux-testgen/qemu-build-instructions.md                      | 0
 {wally-pipelined => tests}/linux-testgen/wallyVirtIO.patch        | 0
 3 files changed, 0 insertions(+), 0 deletions(-)
 rename {wally-pipelined => tests}/linux-testgen/linux-testvectors/convert2bin.py (100%)
 rename {wally-pipelined => tests}/linux-testgen/qemu-build-instructions.md (100%)
 rename {wally-pipelined => tests}/linux-testgen/wallyVirtIO.patch (100%)

diff --git a/wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py b/tests/linux-testgen/linux-testvectors/convert2bin.py
similarity index 100%
rename from wally-pipelined/linux-testgen/linux-testvectors/convert2bin.py
rename to tests/linux-testgen/linux-testvectors/convert2bin.py
diff --git a/wally-pipelined/linux-testgen/qemu-build-instructions.md b/tests/linux-testgen/qemu-build-instructions.md
similarity index 100%
rename from wally-pipelined/linux-testgen/qemu-build-instructions.md
rename to tests/linux-testgen/qemu-build-instructions.md
diff --git a/wally-pipelined/linux-testgen/wallyVirtIO.patch b/tests/linux-testgen/wallyVirtIO.patch
similarity index 100%
rename from wally-pipelined/linux-testgen/wallyVirtIO.patch
rename to tests/linux-testgen/wallyVirtIO.patch

From cc5c5da8bc4121ab924d7b6876a6d9c8e6fd87ae Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 20:31:55 -0600
Subject: [PATCH 73/95] Added file showing how to compile riscv toolchain for
 different extension combinations.

---
 benchmarks/riscv-coremark/multilib.txt | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 benchmarks/riscv-coremark/multilib.txt

diff --git a/benchmarks/riscv-coremark/multilib.txt b/benchmarks/riscv-coremark/multilib.txt
new file mode 100644
index 00000000..6070e42a
--- /dev/null
+++ b/benchmarks/riscv-coremark/multilib.txt
@@ -0,0 +1,3 @@
+If you need to compile for different abi, below is an example of how to configure the gnu riscv toolchain.
+
+./configure --prefix=/import/eager1/ross/riscv-multilib-bin --enable-multilib --multilib-generate="rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv64ic-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--"

From 138da1fefa4480a14ae03594aefa1481076ee043 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 21:34:40 -0600
Subject: [PATCH 74/95] Removed lsuArb and placed remaining logic in lsu.sv.
 Removed after itlb walk signal as the dcache no longer has any need for this.
 Formated lsu.sv

---
 wally-pipelined/src/cache/dcache.sv    |   2 -
 wally-pipelined/src/cache/dcachefsm.sv |   3 -
 wally-pipelined/src/lsu/lsu.sv         | 334 ++++++++++++-------------
 wally-pipelined/src/lsu/lsuArb.sv      | 105 --------
 wally-pipelined/src/mmu/hptw.sv        |   9 +-
 5 files changed, 167 insertions(+), 286 deletions(-)
 delete mode 100644 wally-pipelined/src/lsu/lsuArb.sv

diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index ab870b64..949e2eb9 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -53,7 +53,6 @@ module dcache
    input logic 		       CacheableM,
    // from ptw
    input logic 		       IgnoreRequest,
-   output logic 	       MemAfterIWalkDone,
    // ahb side
    (* mark_debug = "true" *)output logic [`PA_BITS-1:0] AHBPAdr, // to ahb
    (* mark_debug = "true" *)output logic 	       AHBRead,
@@ -358,7 +357,6 @@ module dcache
 		      .CommittedM,
 		      .DCacheMiss,
 		      .DCacheAccess,
-		      .MemAfterIWalkDone,
 		      .AHBRead,
 		      .AHBWrite,
 		      .SelAdrM,
diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index b13ed264..607b747f 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -53,8 +53,6 @@ module dcachefsm
    // counter outputs
    output logic 	  DCacheMiss,
    output logic 	  DCacheAccess,
-   // hptw outputs
-   output logic 	  MemAfterIWalkDone,
    // Bus outputs
    output logic 	  AHBRead,
    output logic 	  AHBWrite,
@@ -137,7 +135,6 @@ module dcachefsm
     SelUncached = 1'b0;
     SelEvict = 1'b0;
     LRUWriteEn = 1'b0;
-    MemAfterIWalkDone = 1'b0;
     SelFlush = 1'b0;
     FlushAdrCntEn = 1'b0;
     FlushWayCntEn = 1'b0;
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 2fbd9f67..ff35f5b0 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -30,116 +30,114 @@
 // *** Ross Thompson amo misalignment check?
 module lsu 
   (
-   input logic 		       clk, reset,
-   input logic 		       StallM, FlushM, StallW, FlushW,
-   output logic 	       LSUStall,
+   input logic 				   clk, reset,
+   input logic 				   StallM, FlushM, StallW, FlushW,
+   output logic 			   LSUStall,
    // Memory Stage
 
    // connected to cpu (controls)
-   input logic [1:0] 	       MemRWM,
-   input logic [2:0] 	       Funct3M,
-   input logic [6:0] 	       Funct7M, 
-   input logic [1:0] 	       AtomicM,
-   input logic 		       ExceptionM,
-   input logic 		       PendingInterruptM,
-   input logic           FlushDCacheM,
-   output logic 	       CommittedM, 
-   output logic 	       SquashSCW,
-   output logic 	       DCacheMiss,
-   output logic 	       DCacheAccess,
+   input logic [1:0] 		   MemRWM,
+   input logic [2:0] 		   Funct3M,
+   input logic [6:0] 		   Funct7M, 
+   input logic [1:0] 		   AtomicM,
+   input logic 				   ExceptionM,
+   input logic 				   PendingInterruptM,
+   input logic 				   FlushDCacheM,
+   output logic 			   CommittedM, 
+   output logic 			   SquashSCW,
+   output logic 			   DCacheMiss,
+   output logic 			   DCacheAccess,
 
    // address and write data
-   input  logic [`XLEN-1:0]    IEUAdrE,
+   input logic [`XLEN-1:0] 	   IEUAdrE,
    output logic [`XLEN-1:0]    IEUAdrM,
-   input  logic [`XLEN-1:0]    WriteDataM, 
+   input logic [`XLEN-1:0] 	   WriteDataM, 
    output logic [`XLEN-1:0]    ReadDataM,
 
    // cpu privilege
-   input logic [1:0] 	       PrivilegeModeW,
-   input logic 		       DTLBFlushM,
+   input logic [1:0] 		   PrivilegeModeW,
+   input logic 				   DTLBFlushM,
    // faults
-   output logic 	       DTLBLoadPageFaultM, DTLBStorePageFaultM,
-   output logic 	       LoadMisalignedFaultM, LoadAccessFaultM,
+   output logic 			   DTLBLoadPageFaultM, DTLBStorePageFaultM,
+   output logic 			   LoadMisalignedFaultM, LoadAccessFaultM,
    // cpu hazard unit (trap)
-   output logic 	       StoreMisalignedFaultM, StoreAccessFaultM,
+   output logic 			   StoreMisalignedFaultM, StoreAccessFaultM,
 
    // connect to ahb
    output logic [`PA_BITS-1:0] DCtoAHBPAdrM,
-   output logic 	       DCtoAHBReadM, 
-   output logic 	       DCtoAHBWriteM,
-   input logic 		       DCfromAHBAck,
-   input logic [`XLEN-1:0]     DCfromAHBReadData,
+   output logic 			   DCtoAHBReadM, 
+   output logic 			   DCtoAHBWriteM,
+   input logic 				   DCfromAHBAck,
+   input logic [`XLEN-1:0] 	   DCfromAHBReadData,
    output logic [`XLEN-1:0]    DCtoAHBWriteData,
-   output logic [2:0] 	       DCtoAHBSizeM, 
+   output logic [2:0] 		   DCtoAHBSizeM, 
 
    // mmu management
 
    // page table walker
-   input logic [`XLEN-1:0]     SATP_REGW, // from csr
-   input logic 		       STATUS_MXR, STATUS_SUM, STATUS_MPRV,
-   input logic [1:0] 	       STATUS_MPP,
+   input logic [`XLEN-1:0] 	   SATP_REGW, // from csr
+   input logic 				   STATUS_MXR, STATUS_SUM, STATUS_MPRV,
+   input logic [1:0] 		   STATUS_MPP,
 
-   input logic [`XLEN-1:0]     PCF,
-   input logic 		       ITLBMissF,
+   input logic [`XLEN-1:0] 	   PCF,
+   input logic 				   ITLBMissF,
    output logic [`XLEN-1:0]    PTE,
-   output logic [1:0] 	       PageType,
-   output logic 	       ITLBWriteF,
-   output logic 	       WalkerInstrPageFaultF,
-   output logic 	       WalkerLoadPageFaultM,
-   output logic 	       WalkerStorePageFaultM,
+   output logic [1:0] 		   PageType,
+   output logic 			   ITLBWriteF,
+   output logic 			   WalkerInstrPageFaultF,
+   output logic 			   WalkerLoadPageFaultM,
+   output logic 			   WalkerStorePageFaultM,
 
-   input 		       var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
-   input 		       var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
+   input 					   var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
+   input 					   var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // *** this one especially has a large note attached to it in pmpchecker.
    );
 
-  logic 		       DTLBPageFaultM;
-  logic 	         DataMisalignedM;
+  logic 					   DTLBPageFaultM;
 
   
-  logic [`PA_BITS-1:0] 	       MemPAdrM;  // from mmu to dcache
- 
-  logic 		       DTLBMissM;
-  logic 		       DTLBWriteM;
-  logic 		       HPTWStall;  
-  logic [`PA_BITS-1:0] 	       TranslationPAdr;
-  logic 		       HPTWRead;
-  logic [1:0] 		       MemRWMtoDCache;
-  logic [1:0] 		       MemRWMtoLRSC;
-  logic [2:0] 		       Funct3MtoDCache;
-  logic [1:0] 		       AtomicMtoDCache;
-  logic [`PA_BITS-1:0] 	       MemPAdrNoTranslate;
-  logic [11:0] 		       MemAdrE, MemAdrE_RENAME;  
-  logic 		       StallWtoDCache;
-  logic 		       MemReadM;
-  logic 		       DataMisalignedMfromDCache;
-  logic 		       DisableTranslation;  // used to stop intermediate PTE physical addresses being saved to TLB.
-  logic 		       DCacheStall;
+  logic [`PA_BITS-1:0] 		   MemPAdrM;  // from mmu to dcache
+  
+  logic 					   DTLBMissM;
+  logic 					   DTLBWriteM;
+  logic 					   HPTWStall;  
+  logic [`PA_BITS-1:0] 		   TranslationPAdr;
+  logic 					   HPTWRead;
+  logic [1:0] 				   MemRWMtoDCache;
+  logic [1:0] 				   MemRWMtoLRSC;
+  logic [2:0] 				   Funct3MtoDCache;
+  logic [1:0] 				   AtomicMtoDCache;
+  logic [`PA_BITS-1:0] 		   MemPAdrNoTranslate;
+  logic [11:0] 				   MemAdrE, MemAdrE_RENAME;  
+  logic 					   StallWtoDCache;
+  logic 					   MemReadM;
+  logic 					   DataMisalignedM;
+  logic 					   DCacheStall;
 
-  logic 		       CacheableM;
-  logic 		       CacheableMtoDCache;
-  logic 		       SelPTW;
+  logic 					   CacheableM;
+  logic 					   CacheableMtoDCache;
+  logic 					   SelPTW;
 
-  logic 		       CommittedMfromDCache;
-  logic 		       PendingInterruptMtoDCache;
-//  logic 		       FlushWtoDCache;
-  logic 		       WalkerPageFaultM;
+  logic 					   CommittedMfromDCache;
+  logic 					   PendingInterruptMtoDCache;
+  //  logic 		       FlushWtoDCache;
+  logic 					   WalkerPageFaultM;
 
-  logic 		       AnyCPUReqM;
-  logic 		       MemAfterIWalkDone;
+  logic 					   AnyCPUReqM;
+  logic 					   MemAfterIWalkDone;
 
-  typedef enum {STATE_T0_READY,
-				STATE_T0_REPLAY,
-				STATE_T0_FAULT_REPLAY,				
-				STATE_T3_DTLB_MISS,
-				STATE_T4_ITLB_MISS,
-				STATE_T5_ITLB_MISS,
-				STATE_T7_DITLB_MISS} statetype;
+  typedef enum 				   {STATE_T0_READY,
+								STATE_T0_REPLAY,
+								STATE_T0_FAULT_REPLAY,				
+								STATE_T3_DTLB_MISS,
+								STATE_T4_ITLB_MISS,
+								STATE_T5_ITLB_MISS,
+								STATE_T7_DITLB_MISS} statetype;
 
   statetype CurrState, NextState;
-  logic 	   InterlockStall;
-  logic SelReplayCPURequest;
-  logic WalkerInstrPageFaultRaw;
-  logic IgnoreRequest;
+  logic 					   InterlockStall;
+  logic 					   SelReplayCPURequest;
+  logic 					   WalkerInstrPageFaultRaw;
+  logic 					   IgnoreRequest;
   
 
   assign AnyCPUReqM = (|MemRWM)  | (|AtomicM);
@@ -221,14 +219,14 @@ module lsu
   end // always_comb
 
   // signal to CPU it needs to wait on HPTW.
-/* -----\/----- EXCLUDED -----\/-----
-  // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction.  InterlockStall becomes x and it propagates
-  // everywhere.  The case statement below implements the same logic but any x on the inputs will resolve to 0.
-  assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
-						  (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) |
-						  (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
+  /* -----\/----- EXCLUDED -----\/-----
+   // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction.  InterlockStall becomes x and it propagates
+   // everywhere.  The case statement below implements the same logic but any x on the inputs will resolve to 0.
+   assign InterlockStall = (CurrState == STATE_T0_READY & (DTLBMissM | ITLBMissF)) | 
+   (CurrState == STATE_T3_DTLB_MISS & ~WalkerPageFaultM) | (CurrState == STATE_T4_ITLB_MISS & ~WalkerInstrPageFaultRaw) |
+   (CurrState == STATE_T5_ITLB_MISS & ~WalkerInstrPageFaultRaw) | (CurrState == STATE_T7_DITLB_MISS & ~WalkerPageFaultM);
 
- -----/\----- EXCLUDED -----/\----- */
+   -----/\----- EXCLUDED -----/\----- */
 
   always_comb begin
 	InterlockStall = 1'b0;
@@ -257,64 +255,61 @@ module lsu
   // *** add generate to conditionally create hptw, lsuArb, and mmu
   // based on `MEM_VIRTMEM
   hptw hptw(.clk(clk),
-	    .reset(reset),
-	    .SATP_REGW(SATP_REGW),
-	    .PCF(PCF),
-	    .IEUAdrM(IEUAdrM),
-	    .ITLBMissF(ITLBMissF & ~PendingInterruptM),
-	    .DTLBMissM(DTLBMissM & ~PendingInterruptM),
-	    .MemRWM(MemRWM),
-	    .PTE(PTE),
-	    .PageType,
-	    .ITLBWriteF(ITLBWriteF),
-	    .DTLBWriteM(DTLBWriteM),
-	    .HPTWReadPTE(ReadDataM),
-	    .DCacheStall(DCacheStall),
-        .TranslationPAdr,			  
-	    .HPTWRead(HPTWRead),
-		.HPTWStall,
-	    .AnyCPUReqM,
-	    .MemAfterIWalkDone,
-	    .WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
-	    .WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
-	    .WalkerStorePageFaultM(WalkerStorePageFaultM));
+			.reset(reset),
+			.SATP_REGW(SATP_REGW),
+			.PCF(PCF),
+			.IEUAdrM(IEUAdrM),
+			.ITLBMissF(ITLBMissF & ~PendingInterruptM),
+			.DTLBMissM(DTLBMissM & ~PendingInterruptM),
+			.MemRWM(MemRWM),
+			.PTE(PTE),
+			.PageType,
+			.ITLBWriteF(ITLBWriteF),
+			.DTLBWriteM(DTLBWriteM),
+			.HPTWReadPTE(ReadDataM),
+			.DCacheStall(DCacheStall),
+			.TranslationPAdr,			  
+			.HPTWRead(HPTWRead),
+			.AnyCPUReqM,
+			.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
+			.WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
+			.WalkerStorePageFaultM(WalkerStorePageFaultM));
 
   assign LSUStall = DCacheStall | InterlockStall;
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
   // arbiter between IEU and hptw
-  lsuArb arbiter(.clk(clk),
-		 // HPTW connection
-		 .SelPTW,
-		 .HPTWRead(HPTWRead),
-		 .TranslationPAdrE(TranslationPAdr),
-		 // CPU connection
-		 .MemRWM(MemRWM),
-		 .Funct3M(Funct3M),
-		 .AtomicM(AtomicM),
-		 .IEUAdrM(IEUAdrM),
-		 .IEUAdrE(IEUAdrE[11:0]),		 
-		 .CommittedM(CommittedM),
-		 .PendingInterruptM(PendingInterruptM),		
-		 .StallW(StallW),
-		 .DataMisalignedM(DataMisalignedM),
-		 // DCACHE
-		 .DisableTranslation(DisableTranslation),
-		 .MemRWMtoLRSC(MemRWMtoLRSC),
-		 .Funct3MtoDCache(Funct3MtoDCache),
-		 .AtomicMtoDCache(AtomicMtoDCache),
-		 .MemPAdrNoTranslate(MemPAdrNoTranslate),
-		 .MemAdrE(MemAdrE),
-		 .StallWtoDCache(StallWtoDCache),
-		 .DataMisalignedMfromDCache(DataMisalignedMfromDCache),
-		 .CommittedMfromDCache(CommittedMfromDCache),
-		 .PendingInterruptMtoDCache(PendingInterruptMtoDCache),
-		 .DCacheStall(DCacheStall));
+  logic [2:0] PTWSize;
+  logic [`PA_BITS-1:0]  TranslationPAdrM;
+  logic [`XLEN+1:0]  IEUAdrMExt;
+  
+  // multiplex the outputs to LSU
+  assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
+  
+  generate
+    assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
+  endgenerate
+  mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
+
+  // this is for the d cache SRAM.
+  flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
+
+  assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
+  assign IEUAdrMExt = {2'b00, IEUAdrM};
+  assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0]; 
+  assign MemAdrE = SelPTW ? TranslationPAdr[11:0] : IEUAdrE[11:0];  
+  assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
+  // always block interrupts when using the hardware page table walker.
+  assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
+
+
+  assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
+  
   
   mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
   dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
-       .PrivilegeModeW, .DisableTranslation(DisableTranslation),
+       .PrivilegeModeW, .DisableTranslation(SelPTW),
        .PAdr(MemPAdrNoTranslate),
        .VAdr(IEUAdrM),
        .Size(Funct3MtoDCache[1:0]),
@@ -353,15 +348,15 @@ module lsu
   // Determine if an Unaligned access is taking place
   always_comb
     case(Funct3MtoDCache[1:0]) 
-      2'b00:  DataMisalignedMfromDCache = 0;                       // lb, sb, lbu
-      2'b01:  DataMisalignedMfromDCache = MemPAdrNoTranslate[0];              // lh, sh, lhu
-      2'b10:  DataMisalignedMfromDCache = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu
-      2'b11:  DataMisalignedMfromDCache = |MemPAdrNoTranslate[2:0];           // ld, sd, fld, fsd
+      2'b00:  DataMisalignedM = 0;                       // lb, sb, lbu
+      2'b01:  DataMisalignedM = MemPAdrNoTranslate[0];              // lh, sh, lhu
+      2'b10:  DataMisalignedM = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu
+      2'b11:  DataMisalignedM = |MemPAdrNoTranslate[2:0];           // ld, sd, fld, fsd
     endcase 
 
   // Determine if address is valid
-  assign LoadMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[1];
-  assign StoreMisalignedFaultM = DataMisalignedMfromDCache & MemRWMtoLRSC[0];
+  assign LoadMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[1];
+  assign StoreMisalignedFaultM = DataMisalignedM & MemRWMtoLRSC[0];
 
   // conditional
   // 1. ram // controlled by `MEM_DTIM
@@ -370,37 +365,36 @@ module lsu
   assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0];
   
   dcache dcache(.clk(clk),
-		.reset(reset),
-		.StallWtoDCache(StallWtoDCache),
-		.MemRWM(MemRWMtoDCache),
-		.Funct3M(Funct3MtoDCache),
-		.Funct7M(Funct7M),
-		.FlushDCacheM,
-		.AtomicM(AtomicMtoDCache),
-		.MemAdrE(MemAdrE_RENAME),
-		.MemPAdrM(MemPAdrM),
-		.VAdr(IEUAdrM[11:0]),	 // this will be removed once the dcache hptw interlock is removed.
-		.WriteDataM(WriteDataM),
-		.ReadDataM(ReadDataM),
-		.DCacheStall(DCacheStall),
-		.CommittedM(CommittedMfromDCache),
-		.DCacheMiss,
-		.DCacheAccess,		
-		.ExceptionM(ExceptionM),
-		.IgnoreRequest,
-		.PendingInterruptM(PendingInterruptMtoDCache),
-		.CacheableM(CacheableMtoDCache), 
-		.MemAfterIWalkDone,
+				.reset(reset),
+				.StallWtoDCache(StallWtoDCache),
+				.MemRWM(MemRWMtoDCache),
+				.Funct3M(Funct3MtoDCache),
+				.Funct7M(Funct7M),
+				.FlushDCacheM,
+				.AtomicM(AtomicMtoDCache),
+				.MemAdrE(MemAdrE_RENAME),
+				.MemPAdrM(MemPAdrM),
+				.VAdr(IEUAdrM[11:0]),	 // this will be removed once the dcache hptw interlock is removed.
+				.WriteDataM(WriteDataM),
+				.ReadDataM(ReadDataM),
+				.DCacheStall(DCacheStall),
+				.CommittedM(CommittedMfromDCache),
+				.DCacheMiss,
+				.DCacheAccess,		
+				.ExceptionM(ExceptionM),
+				.IgnoreRequest,
+				.PendingInterruptM(PendingInterruptMtoDCache),
+				.CacheableM(CacheableMtoDCache), 
 
-		// AHB connection
-		.AHBPAdr(DCtoAHBPAdrM),
-		.AHBRead(DCtoAHBReadM),
-		.AHBWrite(DCtoAHBWriteM),
-		.AHBAck(DCfromAHBAck),
-		.HWDATA(DCtoAHBWriteData),
-		.HRDATA(DCfromAHBReadData),
-		.DCtoAHBSizeM
-		);
+				// AHB connection
+				.AHBPAdr(DCtoAHBPAdrM),
+				.AHBRead(DCtoAHBReadM),
+				.AHBWrite(DCtoAHBWriteM),
+				.AHBAck(DCfromAHBAck),
+				.HWDATA(DCtoAHBWriteData),
+				.HRDATA(DCfromAHBReadData),
+				.DCtoAHBSizeM
+				);
 
 endmodule
 
diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv
deleted file mode 100644
index 91c5f75f..00000000
--- a/wally-pipelined/src/lsu/lsuArb.sv
+++ /dev/null
@@ -1,105 +0,0 @@
-///////////////////////////////////////////
-// lsuArb.sv
-//
-// Written: Ross THompson and Kip Macsai-Goren
-// Modified: kmacsaigoren@hmc.edu June 23, 2021
-//
-// Purpose: LSU arbiter between the CPU's demand request for data memory and
-//          the page table walker
-// 
-// A component of the Wally configurable RISC-V project.
-// 
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software 
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-`include "wally-config.vh"
-
-module lsuArb 
-  (input  logic clk,
-
-   // from page table walker
-   input logic 		       SelPTW,
-   input logic 		       HPTWRead,
-   input logic [`PA_BITS-1:0]  TranslationPAdrE,
-
-   // from CPU
-   input logic [1:0] 	       MemRWM,
-   input logic [2:0] 	       Funct3M,
-   input logic [1:0] 	       AtomicM,
-   input logic [`XLEN-1:0]     IEUAdrM,
-   input logic [11:0] 	       IEUAdrE,
-   input logic 		       StallW,
-   input logic 		       PendingInterruptM,
-   // to CPU
-   output logic 	       DataMisalignedM,
-   output logic 	       CommittedM,
-   //output logic 	       LSUStall, 
-  
-   // to D Cache
-   output logic 	       DisableTranslation, 
-   output logic [1:0] 	       MemRWMtoLRSC,
-   output logic [2:0] 	       Funct3MtoDCache,
-   output logic [1:0] 	       AtomicMtoDCache,
-   output logic [`PA_BITS-1:0] MemPAdrNoTranslate,   // THis name is very bad. need a better name. This is the raw address from either the ieu or the hptw.
-   output logic [11:0] 	       MemAdrE, 
-   output logic 	       StallWtoDCache,
-   output logic 	       PendingInterruptMtoDCache,
-   
-
-   // from D Cache
-   input logic 		       CommittedMfromDCache,
-   input logic 		       DataMisalignedMfromDCache,
-   input logic 		       DCacheStall
-  
-   );
-
-  logic [2:0] PTWSize;
-  logic [`PA_BITS-1:0]  TranslationPAdrM;
-  logic [`XLEN+1:0]  IEUAdrMExt;
-  
-  // multiplex the outputs to LSU
-  assign DisableTranslation = SelPTW;  // change names between SelPTW would be confusing in DTLB.
-  assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
-  
-  generate
-    assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
-  endgenerate
-  mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
-
-  // this is for the d cache SRAM.
-  flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdrE, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
-
-  assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
-  assign IEUAdrMExt = {2'b00, IEUAdrM};
-  assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0]; 
-  assign MemAdrE = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0];  
-  assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
-  // always block interrupts when using the hardware page table walker.
-  assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
-
-  // demux the inputs from LSU to walker or cpu's data port.
-
-  // works without the demux 7/18/21 dh.  Suggest deleting these and removing fromDCache suffix
-  assign DataMisalignedM = /*SelPTW ? 1'b0 : */DataMisalignedMfromDCache;
-  // *** need to rename DcacheStall and Datastall.
-  // not clear at all.  I think it should be LSUStall from the LSU,
-  // which is demuxed to HPTWStall and CPUDataStall? (not sure on this last one).
-  //assign HPTWStall = SelPTW ? DCacheStall : 1'b1;  
-
-  assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
-
-  //assign LSUStall = SelPTW ? 1'b1 : DCacheStall; // *** this is probably going to change.
-  
-endmodule
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index d2a5fa1a..b436162f 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -39,7 +39,6 @@ module hptw
    input logic [1:0] 	       MemRWM, // 10 = read, 01 = write
    input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU
    input logic 		       DCacheStall, // stall from LSU
-   input logic 		       MemAfterIWalkDone,
    input logic 		       AnyCPUReqM,
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0] 	       PageType, // page type to TLBs
@@ -54,7 +53,7 @@ module hptw
 				     L1_ADR, L1_RD, 
 				     L2_ADR, L2_RD, 
 				     L3_ADR, L3_RD, 
-				     LEAF, LEAF_DELAY, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
+				     LEAF, IDLE, FAULT} statetype; // *** placed outside generate statement to remove synthesis errors
 
   generate
     if (`MEM_VIRTMEM) begin
@@ -198,10 +197,8 @@ module hptw
 	      			else 			NextWalkerState = LEAF;
 //	    LEVEL0: if (ValidLeafPTE) 	NextWalkerState = LEAF;
 //				else 				NextWalkerState = FAULT;
-	    LEAF: 	if (DTLBWalk)		NextWalkerState = IDLE; // updates TLB
-		        else                NextWalkerState = IDLE;
-	    LEAF_DELAY: 				NextWalkerState = IDLE;		 // give time to allow address translation
-	    FAULT: if (ITLBMissF & AnyCPUReqM & ~MemAfterIWalkDone) NextWalkerState = FAULT;
+	    LEAF:                       NextWalkerState = IDLE; // updates TLB
+	    FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT;
  	                        else NextWalkerState = IDLE;
 	    default: begin
 	      // synthesis translate_off

From dc95896303421bdb9988ffc7553a0f7d2eb3b5fc Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 21:36:54 -0600
Subject: [PATCH 75/95] Removed HPTWStall.  Not needed as InterlockStall from
 the LSU provides the equivalent.

---
 wally-pipelined/src/mmu/hptw.sv | 2 --
 1 file changed, 2 deletions(-)

diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index b436162f..02de969f 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -43,7 +43,6 @@ module hptw
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0] 	       PageType, // page type to TLBs
    output logic 	       ITLBWriteF, DTLBWriteM, // write TLB with new entry
-   output logic            HPTWStall,
    output logic [`PA_BITS-1:0] TranslationPAdr,
    output logic 	       HPTWRead, // HPTW requesting to read memory
    output logic 	       WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
@@ -99,7 +98,6 @@ module hptw
 	  // Enable and select signals based on states
       assign StartWalk = (WalkerState == IDLE) & TLBMiss;
 	  assign HPTWRead = (WalkerState == L3_RD) | (WalkerState == L2_RD) | (WalkerState == L1_RD) | (WalkerState == L0_RD);
-	  assign HPTWStall = (WalkerState != IDLE) & (WalkerState != FAULT);
 	  assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
 	  assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
 

From dc82d44f9e53e3346bf19ea3d434057c525e2737 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 22:00:28 -0600
Subject: [PATCH 76/95] Hardware reductions in the lsu.

---
 wally-pipelined/src/lsu/lsu.sv  | 37 ++++++++++-----------------------
 wally-pipelined/src/mmu/hptw.sv | 34 +++++++++++++++++-------------
 2 files changed, 30 insertions(+), 41 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index ff35f5b0..096b1b85 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -101,6 +101,7 @@ module lsu
   logic 					   DTLBWriteM;
   logic 					   HPTWStall;  
   logic [`PA_BITS-1:0] 		   TranslationPAdr;
+  //logic [`PA_BITS-1:0] 		   TranslationPAdrM;
   logic 					   HPTWRead;
   logic [1:0] 				   MemRWMtoDCache;
   logic [1:0] 				   MemRWMtoLRSC;
@@ -116,6 +117,8 @@ module lsu
   logic 					   CacheableM;
   logic 					   CacheableMtoDCache;
   logic 					   SelPTW;
+  logic [2:0] 				   HPTWSize;
+
 
   logic 					   CommittedMfromDCache;
   logic 					   PendingInterruptMtoDCache;
@@ -254,50 +257,32 @@ module lsu
 
   // *** add generate to conditionally create hptw, lsuArb, and mmu
   // based on `MEM_VIRTMEM
-  hptw hptw(.clk(clk),
-			.reset(reset),
-			.SATP_REGW(SATP_REGW),
-			.PCF(PCF),
-			.IEUAdrM(IEUAdrM),
+  hptw hptw(.clk, .reset, .SATP_REGW, .PCF, .IEUAdrM,
 			.ITLBMissF(ITLBMissF & ~PendingInterruptM),
 			.DTLBMissM(DTLBMissM & ~PendingInterruptM),
-			.MemRWM(MemRWM),
-			.PTE(PTE),
-			.PageType,
-			.ITLBWriteF(ITLBWriteF),
-			.DTLBWriteM(DTLBWriteM),
+			.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
 			.HPTWReadPTE(ReadDataM),
-			.DCacheStall(DCacheStall),
-			.TranslationPAdr,			  
-			.HPTWRead(HPTWRead),
-			.AnyCPUReqM,
+			.DCacheStall, .TranslationPAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM,
 			.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
-			.WalkerLoadPageFaultM(WalkerLoadPageFaultM),  
-			.WalkerStorePageFaultM(WalkerStorePageFaultM));
+			.WalkerLoadPageFaultM, .WalkerStorePageFaultM);
 
   assign LSUStall = DCacheStall | InterlockStall;
   
   assign WalkerPageFaultM = WalkerStorePageFaultM | WalkerLoadPageFaultM;
 
   // arbiter between IEU and hptw
-  logic [2:0] PTWSize;
-  logic [`PA_BITS-1:0]  TranslationPAdrM;
-  logic [`XLEN+1:0]  IEUAdrMExt;
   
   // multiplex the outputs to LSU
   assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
   
-  generate
-    assign PTWSize = (`XLEN==32 ? 3'b010 : 3'b011); // 32 or 64-bit access from htpw
-  endgenerate
-  mux2 #(3) sizemux(Funct3M, PTWSize, SelPTW, Funct3MtoDCache);
+  mux2 #(3) sizemux(Funct3M, HPTWSize, SelPTW, Funct3MtoDCache);
 
   // this is for the d cache SRAM.
-  flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
+  // turns out because we cannot pipeline hptw requests we don't need this register
+  //flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
 
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
-  assign IEUAdrMExt = {2'b00, IEUAdrM};
-  assign MemPAdrNoTranslate = SelPTW ? TranslationPAdrM : IEUAdrMExt[`PA_BITS-1:0]; 
+  assign MemPAdrNoTranslate = SelPTW ? TranslationPAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; 
   assign MemAdrE = SelPTW ? TranslationPAdr[11:0] : IEUAdrE[11:0];  
   assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index 02de969f..fa8043d8 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -32,20 +32,21 @@
 
 module hptw
   (
-   input logic 		       clk, reset,
-   input logic [`XLEN-1:0]     SATP_REGW, // includes SATP.MODE to determine number of levels in page table
-   input logic [`XLEN-1:0]     PCF, IEUAdrM, // addresses to translate
-   input logic 		       ITLBMissF, DTLBMissM, // TLB Miss
-   input logic [1:0] 	       MemRWM, // 10 = read, 01 = write
-   input logic [`XLEN-1:0]     HPTWReadPTE, // page table entry from LSU
-   input logic 		       DCacheStall, // stall from LSU
-   input logic 		       AnyCPUReqM,
+   input logic 				   clk, reset,
+   input logic [`XLEN-1:0] 	   SATP_REGW, // includes SATP.MODE to determine number of levels in page table
+   input logic [`XLEN-1:0] 	   PCF, IEUAdrM, // addresses to translate
+   input logic 				   ITLBMissF, DTLBMissM, // TLB Miss
+   input logic [1:0] 		   MemRWM, // 10 = read, 01 = write
+   input logic [`XLEN-1:0] 	   HPTWReadPTE, // page table entry from LSU
+   input logic 				   DCacheStall, // stall from LSU
+   input logic 				   AnyCPUReqM,
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
-   output logic [1:0] 	       PageType, // page type to TLBs
-   output logic 	       ITLBWriteF, DTLBWriteM, // write TLB with new entry
+   output logic [1:0] 		   PageType, // page type to TLBs
+   output logic 			   ITLBWriteF, DTLBWriteM, // write TLB with new entry
    output logic [`PA_BITS-1:0] TranslationPAdr,
-   output logic 	       HPTWRead, // HPTW requesting to read memory
-   output logic 	       WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
+   output logic 			   HPTWRead, // HPTW requesting to read memory
+   output logic [2:0] 		   HPTWSize, // 32 or 64 bit access.
+   output logic 			   WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
 );
 
       typedef enum  {L0_ADR, L0_RD, 
@@ -123,7 +124,8 @@ module hptw
 		logic [`PPN_BITS-1:0] PPN;
 		assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
 		assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; 
-		assign TranslationPAdr = {PPN, VPN, 2'b00}; 
+		assign TranslationPAdr = {PPN, VPN, 2'b00};
+		assign HPTWSize = 3'b010;
 	  end else begin // RV64
 		logic [8:0] VPN;
 		logic [`PPN_BITS-1:0] PPN;
@@ -136,7 +138,8 @@ module hptw
 			endcase
 		assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | 
 		              (SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
-		assign TranslationPAdr = {PPN, VPN, 3'b000}; 
+		assign TranslationPAdr = {PPN, VPN, 3'b000};
+		assign HPTWSize = 3'b011;
 	  end
 
 	  // Initial state and misalignment for RV32/64
@@ -208,7 +211,8 @@ module hptw
     end else begin // No Virtual memory supported; tie HPTW outputs to 0
       assign HPTWRead = 0;
       assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
-      assign TranslationPAdr = 0; 
+      assign TranslationPAdr = 0;
+	  assign HPTWSize = 3'b000;
     end
   endgenerate
 endmodule

From 8feb36b926cb160727629bb1437026d032cbf770 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 22:21:03 -0600
Subject: [PATCH 77/95] Signal renames.

---
 wally-pipelined/src/cache/dcache.sv    |  4 ++--
 wally-pipelined/src/cache/dcachefsm.sv | 22 +++++++++++-----------
 wally-pipelined/src/lsu/lrsc.sv        |  4 ++--
 wally-pipelined/src/lsu/lsu.sv         | 21 ++++++++++-----------
 wally-pipelined/src/mmu/hptw.sv        | 12 ++++++------
 5 files changed, 31 insertions(+), 32 deletions(-)

diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv
index 949e2eb9..1936705e 100644
--- a/wally-pipelined/src/cache/dcache.sv
+++ b/wally-pipelined/src/cache/dcache.sv
@@ -28,7 +28,7 @@
 module dcache
   (input logic clk,
    input logic 		       reset,
-   input logic 		       StallWtoDCache,
+   input logic 		       CPUBusy,
 
    // cpu side
    input logic [1:0] 	       MemRWM,
@@ -346,7 +346,7 @@ module dcache
 		      .AtomicM,
  		      .ExceptionM,
  		      .PendingInterruptM,
- 		      .StallWtoDCache,
+ 		      .CPUBusy,
  		      .CacheableM,
 			  .IgnoreRequest,
  		      .AHBAck, // from ahb
diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index 607b747f..eb191b9a 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -35,7 +35,7 @@ module dcachefsm
    // hazard inputs
    input logic 		  ExceptionM,
    input logic 		  PendingInterruptM,
-   input logic 		  StallWtoDCache,
+   input logic 		  CPUBusy,
    input logic 		  CacheableM,
    // hptw inputs
    input logic 		  IgnoreRequest,
@@ -182,7 +182,7 @@ module dcachefsm
 		  SelAdrM = 2'b10;
 		  DCacheStall = 1'b0;
 		  
-		  if(StallWtoDCache) begin 
+		  if(CPUBusy) begin 
 			NextState = STATE_CPU_BUSY_FINISH_AMO;
 			SelAdrM = 2'b10;
 		  end
@@ -198,7 +198,7 @@ module dcachefsm
 		  DCacheStall = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  
-		  if(StallWtoDCache) begin
+		  if(CPUBusy) begin
 			NextState = STATE_CPU_BUSY;
             SelAdrM = 2'b10;
 		  end
@@ -214,7 +214,7 @@ module dcachefsm
 		  SetDirty = 1'b1;
 		  LRUWriteEn = 1'b1;
 		  
-		  if(StallWtoDCache) begin 
+		  if(CPUBusy) begin 
 			NextState = STATE_CPU_BUSY;
 			SelAdrM = 2'b10;
 		  end
@@ -307,7 +307,7 @@ module dcachefsm
 		LRUWriteEn = 1'b0;
 		if(&MemRWM & AtomicM[1]) begin // amo write
 		  SelAdrM = 2'b10;
-		  if(StallWtoDCache) begin 
+		  if(CPUBusy) begin 
 			NextState = STATE_CPU_BUSY_FINISH_AMO;
 		  end
 		  else begin
@@ -318,7 +318,7 @@ module dcachefsm
 		  end
 		end else begin
 		  LRUWriteEn = 1'b1;
-		  if(StallWtoDCache) begin 
+		  if(CPUBusy) begin 
 			NextState = STATE_CPU_BUSY;
 			SelAdrM = 2'b10;
 		  end
@@ -334,7 +334,7 @@ module dcachefsm
 		SelAdrM = 2'b10;
 		CommittedM = 1'b1;
 		LRUWriteEn = 1'b1;
-		if(StallWtoDCache) begin 
+		if(CPUBusy) begin 
 		  NextState = STATE_CPU_BUSY;
 		  SelAdrM = 2'b10;
 		end
@@ -361,7 +361,7 @@ module dcachefsm
       STATE_CPU_BUSY: begin
 		CommittedM = 1'b1;
 		SelAdrM = 2'b00;
-		if(StallWtoDCache) begin
+		if(CPUBusy) begin
 		  NextState = STATE_CPU_BUSY;
 		  SelAdrM = 2'b10;
 		end
@@ -376,7 +376,7 @@ module dcachefsm
 		SRAMWordWriteEnableM = 1'b0;
 		SetDirty = 1'b0;
 		LRUWriteEn = 1'b0;
-		if(StallWtoDCache) begin
+		if(CPUBusy) begin
 		  NextState = STATE_CPU_BUSY_FINISH_AMO;
 		end
 		else begin
@@ -412,7 +412,7 @@ module dcachefsm
       STATE_UNCACHED_WRITE_DONE: begin
 		CommittedM = 1'b1;
 		SelAdrM = 2'b00;
-		if(StallWtoDCache) begin
+		if(CPUBusy) begin
 		  NextState = STATE_CPU_BUSY;
 		  SelAdrM = 2'b10;
 		end
@@ -425,7 +425,7 @@ module dcachefsm
 		CommittedM = 1'b1;
 		SelUncached = 1'b1;
 		SelAdrM = 2'b00;
-		if(StallWtoDCache) begin 
+		if(CPUBusy) begin 
 		  NextState = STATE_CPU_BUSY;
 		  SelAdrM = 2'b10;
 		end
diff --git a/wally-pipelined/src/lsu/lrsc.sv b/wally-pipelined/src/lsu/lrsc.sv
index 64bdbdd4..a98b7dd5 100644
--- a/wally-pipelined/src/lsu/lrsc.sv
+++ b/wally-pipelined/src/lsu/lrsc.sv
@@ -29,7 +29,7 @@
 module lrsc
   (
     input  logic                clk, reset,
-    input  logic                FlushW, StallWtoDCache,
+    input  logic                FlushW, CPUBusy,
     input  logic                MemReadM,
     input  logic [1:0]          MemRWMtoLRSC,
     output logic [1:0]          MemRWMtoDCache,
@@ -57,7 +57,7 @@ module lrsc
       end
       flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
       flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
-      flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCW);
+      flopenrc #(1) squashreg(clk, reset, FlushW, ~CPUBusy, SquashSCM, SquashSCW);
     end else begin // Atomic operations not supported
       assign SquashSCW = 0;
       assign MemRWMtoDCache = MemRWMtoLRSC;
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 096b1b85..7b0f564e 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -27,7 +27,6 @@
 
 `include "wally-config.vh"
 
-// *** Ross Thompson amo misalignment check?
 module lsu 
   (
    input logic 				   clk, reset,
@@ -100,8 +99,8 @@ module lsu
   logic 					   DTLBMissM;
   logic 					   DTLBWriteM;
   logic 					   HPTWStall;  
-  logic [`PA_BITS-1:0] 		   TranslationPAdr;
-  //logic [`PA_BITS-1:0] 		   TranslationPAdrM;
+  logic [`PA_BITS-1:0] 		   HPTWAdr;
+  //logic [`PA_BITS-1:0] 		   HPTWAdrM;
   logic 					   HPTWRead;
   logic [1:0] 				   MemRWMtoDCache;
   logic [1:0] 				   MemRWMtoLRSC;
@@ -109,7 +108,7 @@ module lsu
   logic [1:0] 				   AtomicMtoDCache;
   logic [`PA_BITS-1:0] 		   MemPAdrNoTranslate;
   logic [11:0] 				   MemAdrE, MemAdrE_RENAME;  
-  logic 					   StallWtoDCache;
+  logic 					   CPUBusy;
   logic 					   MemReadM;
   logic 					   DataMisalignedM;
   logic 					   DCacheStall;
@@ -262,7 +261,7 @@ module lsu
 			.DTLBMissM(DTLBMissM & ~PendingInterruptM),
 			.MemRWM, .PTE, .PageType, .ITLBWriteF, .DTLBWriteM,
 			.HPTWReadPTE(ReadDataM),
-			.DCacheStall, .TranslationPAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM,
+			.DCacheStall, .HPTWAdr, .HPTWRead, .HPTWSize, .AnyCPUReqM,
 			.WalkerInstrPageFaultF(WalkerInstrPageFaultRaw),
 			.WalkerLoadPageFaultM, .WalkerStorePageFaultM);
 
@@ -279,12 +278,12 @@ module lsu
 
   // this is for the d cache SRAM.
   // turns out because we cannot pipeline hptw requests we don't need this register
-  //flop #(`PA_BITS) TranslationPAdrMReg(clk, TranslationPAdr, TranslationPAdrM);   // delay TranslationPAdrM by a cycle
+  //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM);   // delay HPTWAdrM by a cycle
 
   assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
-  assign MemPAdrNoTranslate = SelPTW ? TranslationPAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; 
-  assign MemAdrE = SelPTW ? TranslationPAdr[11:0] : IEUAdrE[11:0];  
-  assign StallWtoDCache = SelPTW ? 1'b0 : StallW;
+  assign MemPAdrNoTranslate = SelPTW ? HPTWAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; 
+  assign MemAdrE = SelPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];  
+  assign CPUBusy = SelPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.
   assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
 
@@ -318,7 +317,7 @@ module lsu
 
   // Move generate from lrsc to outside this module.
   assign MemReadM = MemRWMtoLRSC[1] & ~(ExceptionM | PendingInterruptMtoDCache) & ~DTLBMissM; // & ~NonBusTrapM & ~DTLBMissM & CurrState != STATE_STALLED;
-  lrsc lrsc(.clk, .reset, .FlushW, .StallWtoDCache, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
+  lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .MemRWMtoLRSC, .AtomicMtoDCache, .MemPAdrM,
             .SquashSCW, .MemRWMtoDCache);
 
   // *** BUG, this is most likely wrong
@@ -351,7 +350,7 @@ module lsu
   
   dcache dcache(.clk(clk),
 				.reset(reset),
-				.StallWtoDCache(StallWtoDCache),
+				.CPUBusy(CPUBusy),
 				.MemRWM(MemRWMtoDCache),
 				.Funct3M(Funct3MtoDCache),
 				.Funct7M(Funct7M),
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index fa8043d8..462ee7d3 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -5,7 +5,7 @@
 // Modified:  david_harris@hmc.edu 18 July 2021 cleanup and simplification
 //            kmacsaigoren@hmc.edu 1 June 2021
 //            implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
-//            adding support for terapage encoding, and for setting the TranslationPAdr using the new level,
+//            adding support for terapage encoding, and for setting the HPTWAdr using the new level,
 //            adding the internal SvMode signal
 //
 // Purpose: Page Table Walker
@@ -43,7 +43,7 @@ module hptw
    output logic [`XLEN-1:0]    PTE, // page table entry to TLBs
    output logic [1:0] 		   PageType, // page type to TLBs
    output logic 			   ITLBWriteF, DTLBWriteM, // write TLB with new entry
-   output logic [`PA_BITS-1:0] TranslationPAdr,
+   output logic [`PA_BITS-1:0] HPTWAdr,
    output logic 			   HPTWRead, // HPTW requesting to read memory
    output logic [2:0] 		   HPTWSize, // 32 or 64 bit access.
    output logic 			   WalkerInstrPageFaultF, WalkerLoadPageFaultM,WalkerStorePageFaultM // faults
@@ -118,13 +118,13 @@ module hptw
 			default: NextPageType = PageType;
 		endcase
 
-	  // TranslationPAdr muxing
+	  // HPTWAdr muxing
 	  if (`XLEN==32) begin // RV32
 		logic [9:0] VPN;
 		logic [`PPN_BITS-1:0] PPN;
 		assign VPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? TranslationVAdr[31:22] : TranslationVAdr[21:12]; // select VPN field based on HPTW state
 		assign PPN = ((WalkerState == L1_ADR) | (WalkerState == L1_RD)) ? BasePageTablePPN : CurrentPPN; 
-		assign TranslationPAdr = {PPN, VPN, 2'b00};
+		assign HPTWAdr = {PPN, VPN, 2'b00};
 		assign HPTWSize = 3'b010;
 	  end else begin // RV64
 		logic [8:0] VPN;
@@ -138,7 +138,7 @@ module hptw
 			endcase
 		assign PPN = ((WalkerState == L3_ADR) | (WalkerState == L3_RD) | 
 		              (SvMode != `SV48 & ((WalkerState == L2_ADR) | (WalkerState == L2_RD)))) ? BasePageTablePPN : CurrentPPN;
-		assign TranslationPAdr = {PPN, VPN, 3'b000};
+		assign HPTWAdr = {PPN, VPN, 3'b000};
 		assign HPTWSize = 3'b011;
 	  end
 
@@ -211,7 +211,7 @@ module hptw
     end else begin // No Virtual memory supported; tie HPTW outputs to 0
       assign HPTWRead = 0;
       assign WalkerInstrPageFaultF = 0; assign WalkerLoadPageFaultM = 0; assign WalkerStorePageFaultM = 0;
-      assign TranslationPAdr = 0;
+      assign HPTWAdr = 0;
 	  assign HPTWSize = 3'b000;
     end
   endgenerate

From d3c3422d120a9f54704e4cee66513da79cadb94c Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 22:24:07 -0600
Subject: [PATCH 78/95] Rename of SelPTW to SelHPTW.

---
 wally-pipelined/regression/linux-wave.do |   2 +-
 wally-pipelined/regression/wave.do       | 279 ++++++++++++-----------
 wally-pipelined/src/lsu/lsu.sv           |  24 +-
 3 files changed, 153 insertions(+), 152 deletions(-)

diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index 4bf8bf7e..60723d6d 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -239,7 +239,7 @@ add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3
 add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
 add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
 add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
-add wave -noupdate -expand -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
+add wave -noupdate -expand -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelHPTW
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do
index 3e19f65b..13319708 100644
--- a/wally-pipelined/regression/wave.do
+++ b/wally-pipelined/regression/wave.do
@@ -4,7 +4,7 @@ add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/test
 add wave -noupdate /testbench/memfilename
-add wave -noupdate /testbench/dut/hart/SATP_REGW
+add wave -noupdate /testbench/dut/hart/lsu/SATP_REGW
 add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
 add wave -noupdate -group {Execution Stage} /testbench/InstrEName
 add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
@@ -15,41 +15,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
 add wave -noupdate /testbench/dut/hart/ieu/dp/ResultM
 add wave -noupdate /testbench/dut/hart/ieu/dp/ResultW
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
-add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
+add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
+add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
 add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
 add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
@@ -103,22 +103,22 @@ add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
 add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
 add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
 add wave -noupdate -group {instruction pipeline} /testbench/InstrW
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
-add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredPCF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext0F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
+add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
 add wave -noupdate -group {Decode Stage} /testbench/InstrDName
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
-add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
 add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
@@ -151,12 +151,12 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
-add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/hart/PCF
-add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
-add wave -noupdate -group PCS /testbench/dut/hart/PCE
-add wave -noupdate -group PCS /testbench/dut/hart/PCM
-add wave -noupdate -group PCS /testbench/PCW
+add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -expand -group PCS /testbench/dut/hart/PCF
+add wave -noupdate -expand -group PCS /testbench/dut/hart/ifu/PCD
+add wave -noupdate -expand -group PCS /testbench/dut/hart/PCE
+add wave -noupdate -expand -group PCS /testbench/dut/hart/PCM
+add wave -noupdate -expand -group PCS /testbench/PCW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcAE
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/ForwardedSrcBE
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
@@ -168,86 +168,86 @@ add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
 add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
-add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/WayHit
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/VictimWay
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
-add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
-add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/RAdr
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
+add wave -noupdate -expand -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/WayHit
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/BlockReplacementBits
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/genblk1/cachereplacementpolicy/EncVicWay
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/VictimWay
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/SetValid}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word1 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word2 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way0 -group Way0Word3 {/testbench/dut/hart/ifu/icache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word1 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word2 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way1 -group Way1Word3 {/testbench/dut/hart/ifu/icache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/SetValid}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word1 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word2 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -group way2 -group Way2Word3 {/testbench/dut/hart/ifu/icache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/SetValid}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/hart/ifu/icache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/DirtyBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group icache -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/hart/ifu/icache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/controller/NextState
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/ReadLineF
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/BasePAdrF
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spillSave
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
+add wave -noupdate -expand -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/SelAdr
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/RAdr
+add wave -noupdate -expand -group icache /testbench/dut/hart/ifu/icache/FinalInstrRawF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrInF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
+add wave -noupdate -expand -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
 add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
 add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
@@ -269,8 +269,10 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
+add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
 add wave -noupdate -expand -group lsu /testbench/dut/hart/hzu/LSUStall
-add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelPTW
+add wave -noupdate -expand -group lsu -expand -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelHPTW
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
@@ -422,7 +424,8 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group typ
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
-add wave -noupdate -group csr /testbench/dut/hart/priv/csr/MIP_REGW
+add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
+add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
@@ -496,8 +499,6 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
-add wave -noupdate /testbench/dut/hart/lsu/CurrState
-add wave -noupdate /testbench/dut/hart/lsu/InterlockStall
 add wave -noupdate /testbench/dut/hart/ifu/icache/PCNextF
 add wave -noupdate /testbench/dut/hart/ifu/icache/PCPF
 add wave -noupdate /testbench/dut/hart/lsu/WalkerInstrPageFaultF
@@ -506,8 +507,8 @@ add wave -noupdate /testbench/dut/hart/lsu/dcache/RAdr
 add wave -noupdate /testbench/dut/hart/lsu/dcache/SelAdrM
 add wave -noupdate /testbench/dut/hart/lsu/SelReplayCPURequest
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 6} {24475 ns} 1} {{Cursor 2} {22501 ns} 1} {{Cursor 3} {3615 ns} 0}
-quietly wave cursor active 3
+WaveRestoreCursors {{Cursor 6} {26646 ns} 1} {{Cursor 2} {70866 ns} 0} {{Cursor 3} {24171 ns} 1}
+quietly wave cursor active 2
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 297
 configure wave -justifyvalue left
@@ -522,4 +523,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {3453 ns} {3729 ns}
+WaveRestoreZoom {70741 ns} {70973 ns}
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 7b0f564e..47dda8aa 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -115,7 +115,7 @@ module lsu
 
   logic 					   CacheableM;
   logic 					   CacheableMtoDCache;
-  logic 					   SelPTW;
+  logic 					   SelHPTW;
   logic [2:0] 				   HPTWSize;
 
 
@@ -245,7 +245,7 @@ module lsu
   
   // When replaying CPU memory request after PTW select the IEUAdrM for correct address.
   assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;
-  assign SelPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
+  assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
 				  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
   assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
   
@@ -272,28 +272,28 @@ module lsu
   // arbiter between IEU and hptw
   
   // multiplex the outputs to LSU
-  assign MemRWMtoLRSC = SelPTW ? {HPTWRead, 1'b0} : MemRWM;
+  assign MemRWMtoLRSC = SelHPTW ? {HPTWRead, 1'b0} : MemRWM;
   
-  mux2 #(3) sizemux(Funct3M, HPTWSize, SelPTW, Funct3MtoDCache);
+  mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, Funct3MtoDCache);
 
   // this is for the d cache SRAM.
   // turns out because we cannot pipeline hptw requests we don't need this register
   //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM);   // delay HPTWAdrM by a cycle
 
-  assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM;
-  assign MemPAdrNoTranslate = SelPTW ? HPTWAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; 
-  assign MemAdrE = SelPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];  
-  assign CPUBusy = SelPTW ? 1'b0 : StallW;
+  assign AtomicMtoDCache = SelHPTW ? 2'b00 : AtomicM;
+  assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; 
+  assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];  
+  assign CPUBusy = SelHPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.
-  assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache;
+  assign CommittedM = SelHPTW ? 1'b1 : CommittedMfromDCache;
 
 
-  assign PendingInterruptMtoDCache = SelPTW ? 1'b0 : PendingInterruptM;
+  assign PendingInterruptMtoDCache = SelHPTW ? 1'b0 : PendingInterruptM;
   
   
   mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0))
   dmmu(.clk, .reset, .SATP_REGW, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP,
-       .PrivilegeModeW, .DisableTranslation(SelPTW),
+       .PrivilegeModeW, .DisableTranslation(SelHPTW),
        .PAdr(MemPAdrNoTranslate),
        .VAdr(IEUAdrM),
        .Size(Funct3MtoDCache[1:0]),
@@ -321,7 +321,7 @@ module lsu
             .SquashSCW, .MemRWMtoDCache);
 
   // *** BUG, this is most likely wrong
-  assign CacheableMtoDCache = SelPTW ? 1'b1 : CacheableM;
+  assign CacheableMtoDCache = SelHPTW ? 1'b1 : CacheableM;
   
 
   // Specify which type of page fault is occurring

From 3eb5f33705de2b916bea6e59e2ee38e25e9e3420 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 22:41:34 -0600
Subject: [PATCH 79/95] Remove verbosity from lsu state machine.

---
 wally-pipelined/src/lsu/lsu.sv | 99 ++++++++++------------------------
 1 file changed, 27 insertions(+), 72 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 47dda8aa..f10154dc 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -150,76 +150,30 @@ module lsu
 
   always_comb begin
 	case(CurrState)
-	  STATE_T0_READY: begin
-		if(~ITLBMissF & DTLBMissM & AnyCPUReqM) begin
-		  NextState = STATE_T3_DTLB_MISS;
-		end
-		else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM) begin
-		  NextState = STATE_T4_ITLB_MISS;
-		end
-		else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM) begin
-		  NextState = STATE_T5_ITLB_MISS;
-		end
-		else if(ITLBMissF & DTLBMissM & AnyCPUReqM) begin
-		  NextState = STATE_T7_DITLB_MISS;
-		end else begin
-		  NextState = STATE_T0_READY;
-		end
-	  end
-	  STATE_T0_REPLAY: begin
-		if(DCacheStall) begin
-		  NextState = STATE_T0_REPLAY;
-		end else begin
-		  NextState = STATE_T0_READY;
-		end
-	  end
-	  STATE_T3_DTLB_MISS: begin
-		if(WalkerLoadPageFaultM | WalkerStorePageFaultM) begin
-		  NextState = STATE_T0_READY;
-		end else if(DTLBWriteM) begin
-		  NextState = STATE_T0_REPLAY;
-		end else begin
-		  NextState = STATE_T3_DTLB_MISS;
-		end
-	  end
-	  STATE_T4_ITLB_MISS: begin
-		if(WalkerInstrPageFaultRaw | ITLBWriteF) begin
-		  NextState = STATE_T0_READY;
-		end else begin
-		  NextState = STATE_T4_ITLB_MISS;
-		end
-	  end
-	  STATE_T5_ITLB_MISS: begin
-		if(ITLBWriteF) begin
-		  NextState = STATE_T0_REPLAY;
-		end else if(WalkerInstrPageFaultRaw) begin
-		  NextState = STATE_T0_FAULT_REPLAY;
-		end else begin
-		  NextState = STATE_T5_ITLB_MISS;
-		end
-	  end
-	  STATE_T0_FAULT_REPLAY: begin
-		if(DCacheStall) begin
-		  NextState = STATE_T0_FAULT_REPLAY;
-		end else begin
-		  NextState = STATE_T0_READY;
-		end
-	  end
-	  STATE_T7_DITLB_MISS: begin
-		if(WalkerStorePageFaultM | WalkerLoadPageFaultM) begin
-		  NextState = STATE_T0_READY;
-		end else if(DTLBWriteM) begin
-		  NextState = STATE_T5_ITLB_MISS;
-		end else begin
-		  NextState = STATE_T7_DITLB_MISS;
-		end
-	  end
-	  default: begin
-		NextState = STATE_T0_READY;
-	  end
+	  STATE_T0_READY:        if(~ITLBMissF & DTLBMissM & AnyCPUReqM)          NextState = STATE_T3_DTLB_MISS;
+	                         else if(ITLBMissF & ~DTLBMissM & ~AnyCPUReqM)    NextState = STATE_T4_ITLB_MISS;
+                             else if(ITLBMissF & ~DTLBMissM & AnyCPUReqM)     NextState = STATE_T5_ITLB_MISS;
+					         else if(ITLBMissF & DTLBMissM & AnyCPUReqM)      NextState = STATE_T7_DITLB_MISS;
+					         else                                             NextState = STATE_T0_READY;
+	  STATE_T0_REPLAY:       if(DCacheStall)                                  NextState = STATE_T0_REPLAY;
+	                         else                                             NextState = STATE_T0_READY;
+	  STATE_T3_DTLB_MISS:    if(WalkerLoadPageFaultM | WalkerStorePageFaultM) NextState = STATE_T0_READY;
+	                         else if(DTLBWriteM)                              NextState = STATE_T0_REPLAY;
+						     else                                             NextState = STATE_T3_DTLB_MISS;
+	  STATE_T4_ITLB_MISS:    if(WalkerInstrPageFaultRaw | ITLBWriteF)         NextState = STATE_T0_READY;
+	                         else                                             NextState = STATE_T4_ITLB_MISS;
+	  STATE_T5_ITLB_MISS:    if(ITLBWriteF)                                   NextState = STATE_T0_REPLAY;
+	                         else if(WalkerInstrPageFaultRaw)                 NextState = STATE_T0_FAULT_REPLAY;
+						     else                                             NextState = STATE_T5_ITLB_MISS;
+	  STATE_T0_FAULT_REPLAY: if(DCacheStall)                                  NextState = STATE_T0_FAULT_REPLAY;
+	                         else                                             NextState = STATE_T0_READY;
+	  STATE_T7_DITLB_MISS:   if(WalkerStorePageFaultM | WalkerLoadPageFaultM) NextState = STATE_T0_READY;
+	                         else if(DTLBWriteM)                              NextState = STATE_T5_ITLB_MISS;
+						     else                                             NextState = STATE_T7_DITLB_MISS;
+	  default: NextState = STATE_T0_READY;
 	endcase
   end // always_comb
-
+  
   // signal to CPU it needs to wait on HPTW.
   /* -----\/----- EXCLUDED -----\/-----
    // this code has a problem with imperas64mmu as it reads in an invalid uninitalized instruction.  InterlockStall becomes x and it propagates
@@ -330,12 +284,13 @@ module lsu
   assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWMtoLRSC[0];
 
   // Determine if an Unaligned access is taking place
+  // hptw guarantees alignment, only check inputs from IEU.
   always_comb
-    case(Funct3MtoDCache[1:0]) 
+    case(Funct3M[1:0]) 
       2'b00:  DataMisalignedM = 0;                       // lb, sb, lbu
-      2'b01:  DataMisalignedM = MemPAdrNoTranslate[0];              // lh, sh, lhu
-      2'b10:  DataMisalignedM = MemPAdrNoTranslate[1] | MemPAdrNoTranslate[0]; // lw, sw, flw, fsw, lwu
-      2'b11:  DataMisalignedM = |MemPAdrNoTranslate[2:0];           // ld, sd, fld, fsd
+      2'b01:  DataMisalignedM = IEUAdrM[0];              // lh, sh, lhu
+      2'b10:  DataMisalignedM = IEUAdrM[1] | IEUAdrM[0]; // lw, sw, flw, fsw, lwu
+      2'b11:  DataMisalignedM = |IEUAdrM[2:0];           // ld, sd, fld, fsd
     endcase 
 
   // Determine if address is valid

From df8bd786792150d7ab58059d3b70131c3fdf9fb2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sun, 19 Dec 2021 22:47:48 -0600
Subject: [PATCH 80/95] More signal name cleanup in LSU.

---
 wally-pipelined/src/lsu/lsu.sv | 28 +++++++---------------------
 1 file changed, 7 insertions(+), 21 deletions(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index f10154dc..77e07741 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -92,15 +92,12 @@ module lsu
    );
 
   logic 					   DTLBPageFaultM;
-
   
   logic [`PA_BITS-1:0] 		   MemPAdrM;  // from mmu to dcache
-  
   logic 					   DTLBMissM;
   logic 					   DTLBWriteM;
   logic 					   HPTWStall;  
   logic [`PA_BITS-1:0] 		   HPTWAdr;
-  //logic [`PA_BITS-1:0] 		   HPTWAdrM;
   logic 					   HPTWRead;
   logic [1:0] 				   MemRWMtoDCache;
   logic [1:0] 				   MemRWMtoLRSC;
@@ -121,7 +118,6 @@ module lsu
 
   logic 					   CommittedMfromDCache;
   logic 					   PendingInterruptMtoDCache;
-  //  logic 		       FlushWtoDCache;
   logic 					   WalkerPageFaultM;
 
   logic 					   AnyCPUReqM;
@@ -251,21 +247,19 @@ module lsu
        .PAdr(MemPAdrNoTranslate),
        .VAdr(IEUAdrM),
        .Size(Funct3MtoDCache[1:0]),
-       .PTE(PTE),
+       .PTE,
        .PageTypeWriteVal(PageType),
        .TLBWrite(DTLBWriteM),
        .TLBFlush(DTLBFlushM),
        .PhysicalAddress(MemPAdrM),
        .TLBMiss(DTLBMissM),
        .Cacheable(CacheableM),
-       .Idempotent(),
-       .AtomicAllowed(),
+       .Idempotent(), .AtomicAllowed(),
        .TLBPageFault(DTLBPageFaultM),
        .InstrAccessFaultF(), .LoadAccessFaultM, .StoreAccessFaultM,
        .AtomicAccessM(1'b0), .ExecuteAccessF(1'b0), 
        .WriteAccessM(MemRWMtoLRSC[0]), .ReadAccessM(MemRWMtoLRSC[1]),
        .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW
-       //.AtomicAccessM(AtomicMaskedM[1]),
        ); // *** the pma/pmp instruction access faults don't really matter here. is it possible to parameterize which outputs exist?
 
 
@@ -303,25 +297,17 @@ module lsu
   // 3. wire pass-through
   assign MemAdrE_RENAME = SelReplayCPURequest ? IEUAdrM[11:0] : MemAdrE[11:0];
   
-  dcache dcache(.clk(clk),
-				.reset(reset),
-				.CPUBusy(CPUBusy),
+  dcache dcache(.clk, .reset, .CPUBusy,
 				.MemRWM(MemRWMtoDCache),
 				.Funct3M(Funct3MtoDCache),
-				.Funct7M(Funct7M),
-				.FlushDCacheM,
+				.Funct7M, .FlushDCacheM,
 				.AtomicM(AtomicMtoDCache),
 				.MemAdrE(MemAdrE_RENAME),
-				.MemPAdrM(MemPAdrM),
+				.MemPAdrM,
 				.VAdr(IEUAdrM[11:0]),	 // this will be removed once the dcache hptw interlock is removed.
-				.WriteDataM(WriteDataM),
-				.ReadDataM(ReadDataM),
-				.DCacheStall(DCacheStall),
+				.WriteDataM, .ReadDataM, .DCacheStall,
 				.CommittedM(CommittedMfromDCache),
-				.DCacheMiss,
-				.DCacheAccess,		
-				.ExceptionM(ExceptionM),
-				.IgnoreRequest,
+				.DCacheMiss, .DCacheAccess, .ExceptionM, .IgnoreRequest,
 				.PendingInterruptM(PendingInterruptMtoDCache),
 				.CacheableM(CacheableMtoDCache), 
 

From b6d75d453a99e8d821cfe47c10dfa99f9b1760d2 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Dec 2021 10:03:56 -0600
Subject: [PATCH 81/95] Modified LSU verilog is compatible with vivado.  have
 to use extra logic IEUAdrExtM.

---
 wally-pipelined/src/lsu/lsu.sv | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 64396288..7914b710 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -94,6 +94,7 @@ module lsu
   logic 					   DTLBPageFaultM;
   
   logic [`PA_BITS-1:0] 		   MemPAdrM;  // from mmu to dcache
+  logic [`XLEN+1:0] 		   IEUAdrExtM;
   logic 					   DTLBMissM;
   logic 					   DTLBWriteM;
   logic 					   HPTWStall;  
@@ -230,7 +231,8 @@ module lsu
   //flop #(`PA_BITS) HPTWAdrMReg(clk, HPTWAdr, HPTWAdrM);   // delay HPTWAdrM by a cycle
 
   assign AtomicMtoDCache = SelHPTW ? 2'b00 : AtomicM;
-  assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : {2'b00, IEUAdrM}[`PA_BITS-1:0]; 
+  assign IEUAdrExtM = {2'b00, IEUAdrM};
+  assign MemPAdrNoTranslate = SelHPTW ? HPTWAdr : IEUAdrExtM[`PA_BITS-1:0]; 
   assign MemAdrE = SelHPTW ? HPTWAdr[11:0] : IEUAdrE[11:0];  
   assign CPUBusy = SelHPTW ? 1'b0 : StallW;
   // always block interrupts when using the hardware page table walker.

From 8416cae3fe9935080d395ff66b202b3e09fc869b Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Dec 2021 18:33:31 -0600
Subject: [PATCH 82/95] Fixed Type 5b interaction between dcache and hptw. This
 is a load concurrent with ITLBMiss.

---
 wally-pipelined/regression/linux-wave.do | 132 +++++++----------------
 wally-pipelined/src/lsu/lsu.sv           |   5 +-
 wally-pipelined/src/mmu/hptw.sv          |   2 +-
 3 files changed, 45 insertions(+), 94 deletions(-)

diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index 60723d6d..819fe3a1 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -5,42 +5,26 @@ add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate -radix unsigned /testbench/InstrCountW
 add wave -noupdate /testbench/dut/hart/SATP_REGW
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/EcallFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
-add wave -noupdate -expand -group HDU -expand -group traps /testbench/dut/hart/priv/trap/InterruptM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
-add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
 add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
 add wave -noupdate -group PCS /testbench/dut/hart/PCF
 add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
@@ -60,16 +44,15 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
-add wave -noupdate -expand -group {Execution Stage} /testbench/ExpectedPCE
-add wave -noupdate -expand -group {Execution Stage} /testbench/MepcExpected
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE
-add wave -noupdate -expand -group {Execution Stage} /testbench/textE
-add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
+add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
+add wave -noupdate -group {Execution Stage} /testbench/MepcExpected
+add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE
+add wave -noupdate -group {Execution Stage} /testbench/textE
+add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
-add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/priv/trap/InstrValidM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
@@ -154,15 +137,7 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/FlagsE
 add wave -noupdate -group alu -divider internals
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
-add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
 add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
 add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
 add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
@@ -180,15 +155,6 @@ add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/Write
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/ALUResultE
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcAE
 add wave -noupdate -group {alu execution stage} /testbench/dut/hart/ieu/dp/SrcBE
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/Funct3E
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivE
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/W64E
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallM
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/StallW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushM
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/FlushW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/MulDivResultW
-add wave -noupdate -group muldiv /testbench/dut/hart/mdu/DivBusyE
 add wave -noupdate -group icache -color Gold /testbench/dut/hart/ifu/icache/controller/CurrState
 add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextState
 add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
@@ -239,9 +205,13 @@ add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3
 add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
 add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
 add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
-add wave -noupdate -expand -group lsu -group {LSU ARB} /testbench/dut/hart/lsu/arbiter/SelHPTW
+add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
+add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
 add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WalkerPageFaultM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
@@ -250,6 +220,10 @@ add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
 add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
 add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
@@ -404,7 +378,6 @@ add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/pm
 add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
-add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
@@ -414,24 +387,6 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /test
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
-add wave -noupdate -group csr -color Gray90 -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
-add wave -noupdate -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIE_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MIP_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MTVAL_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/MTVEC_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MCAUSE_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MEDELEG_REGW
-add wave -noupdate -group csr -expand -group machine /testbench/dut/hart/priv/csr/genblk1/csrm/MIDELEG_REGW
-add wave -noupdate -group csr -expand -group machine -color Brown /testbench/dut/hart/priv/PrivilegeModeW
-add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/STVEC_REGW
-add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/STVAL
-add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
-add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIP_REGW
-add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SIE_REGW
-add wave -noupdate -group csr -expand -group supervisor /testbench/dut/hart/priv/csr/genblk1/csrs/SEPC_REGW
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
 add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
@@ -504,7 +459,6 @@ add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
 add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
 add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/priv/trap/InstrValidM
 add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
 add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/hart/PCM
 add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
@@ -518,19 +472,15 @@ add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
 add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PCNext2F
 add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedNextPCM
 add wave -noupdate -group {pc selection} /testbench/dut/hart/ifu/PrivilegedChangePCM
-add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/PrivilegedNextPCM
-add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedVectoredTrapVector
-add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
 add wave -noupdate /testbench/dut/hart/ifu/PCCorrectE
 add wave -noupdate /testbench/dut/hart/ifu/PCSrcE
 add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
 add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
-add wave -noupdate /testbench/dut/hart/ifu/PCTargetE
 add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
 add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1}
-quietly wave cursor active 1
+WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1} {{Cursor 5} {163846 ns} 0}
+quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 314
 configure wave -justifyvalue left
@@ -545,4 +495,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {14157667 ns} {14157811 ns}
+WaveRestoreZoom {163681 ns} {164021 ns}
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 7914b710..738124a9 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -186,7 +186,8 @@ module lsu
 	  STATE_T0_READY: if(DTLBMissM | ITLBMissF) InterlockStall = 1'b1;
 	  STATE_T3_DTLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
 	  STATE_T4_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
-	  STATE_T5_ITLB_MISS: if (~WalkerInstrPageFaultRaw) InterlockStall = 1'b1;
+	  STATE_T5_ITLB_MISS: InterlockStall = 1'b1;
+	  //STATE_T0_FAULT_REPLAY: if (~WalkerInstrPageFaultF) InterlockStall = 1'b1;
 	  STATE_T7_DITLB_MISS: if (~WalkerPageFaultM) InterlockStall = 1'b1;
 	  default: InterlockStall = 1'b0;
 	endcase
@@ -194,7 +195,7 @@ module lsu
   
   
   // When replaying CPU memory request after PTW select the IEUAdrM for correct address.
-  assign SelReplayCPURequest = NextState == STATE_T0_REPLAY;
+  assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY);
   assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
 				  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
   assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
diff --git a/wally-pipelined/src/mmu/hptw.sv b/wally-pipelined/src/mmu/hptw.sv
index dd545e1d..07345129 100644
--- a/wally-pipelined/src/mmu/hptw.sv
+++ b/wally-pipelined/src/mmu/hptw.sv
@@ -199,7 +199,7 @@ module hptw
 //	    LEVEL0: if (ValidLeafPTE) 	NextWalkerState = LEAF;
 //				else 				NextWalkerState = FAULT;
 	    LEAF:                       NextWalkerState = IDLE; // updates TLB
-	    FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT;
+	    FAULT: if (ITLBMissF & AnyCPUReqM) NextWalkerState = FAULT; /// **** BUG: Stays in fault 1 cycle longer than it should.
  	                        else NextWalkerState = IDLE;
 	    default: begin
 	      // synthesis translate_off

From 787af4287e634856e815b2da2c352f87c343f9a4 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 21 Dec 2021 02:35:41 +0000
Subject: [PATCH 83/95] Removed riscv-isa-sim submodule from Wally; use it in
 /opt/riscv instead

---
 .gitmodules          | 3 ---
 addins/riscv-isa-sim | 1 -
 2 files changed, 4 deletions(-)
 delete mode 160000 addins/riscv-isa-sim

diff --git a/.gitmodules b/.gitmodules
index 71d15314..cd2774a2 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -4,6 +4,3 @@
 [submodule "addins/riscv-arch-test"]
 	path = addins/riscv-arch-test
 	url = https://github.com/riscv-non-isa/riscv-arch-test
-[submodule "addins/riscv-isa-sim"]
-	path = addins/riscv-isa-sim
-	url = https://github.com/riscv-software-src/riscv-isa-sim
diff --git a/addins/riscv-isa-sim b/addins/riscv-isa-sim
deleted file mode 160000
index 0f30988e..00000000
--- a/addins/riscv-isa-sim
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0f30988e4d0e8daac893834b91979f7700bab481

From 50b307bc0e67c8771b34a4776a04598399b4cbf0 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Dec 2021 21:26:38 -0600
Subject: [PATCH 84/95] Looks like rdtime was accidentally replaced with rrame
 from a find and replace.

---
 wally-pipelined/regression/linux-wave.do     | 394 ++++++++++---------
 wally-pipelined/testbench/testbench-linux.sv |   6 +-
 2 files changed, 207 insertions(+), 193 deletions(-)

diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index 819fe3a1..c99dc2fe 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -5,26 +5,26 @@ add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate -radix unsigned /testbench/InstrCountW
 add wave -noupdate /testbench/dut/hart/SATP_REGW
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
 add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
 add wave -noupdate -group PCS /testbench/dut/hart/PCF
 add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
@@ -44,14 +44,14 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
 add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
-add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/PCE
-add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
-add wave -noupdate -group {Execution Stage} /testbench/MepcExpected
-add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
-add wave -noupdate -group {Execution Stage} /testbench/InstrEName
-add wave -noupdate -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE
-add wave -noupdate -group {Execution Stage} /testbench/textE
-add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/ExpectedPCE
+add wave -noupdate -expand -group {Execution Stage} /testbench/MepcExpected
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
+add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
+add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ieu/c/InstrValidE
+add wave -noupdate -expand -group {Execution Stage} /testbench/textE
+add wave -noupdate -expand -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
 add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/PCM
 add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
@@ -59,24 +59,24 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
 add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
 add wave -noupdate -expand -group {Memory Stage} /testbench/textM
 add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/IEUAdrM
-add wave -noupdate -expand -group {WriteBack stage} /testbench/checkInstrW
-add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrValidW
-add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
-add wave -noupdate -expand -group {WriteBack stage} /testbench/ExpectedPCW
-add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrW
-add wave -noupdate -expand -group {WriteBack stage} /testbench/InstrWName
-add wave -noupdate -expand -group {WriteBack stage} /testbench/textW
+add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
+add wave -noupdate -group {WriteBack stage} /testbench/PCW
+add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrW
+add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
+add wave -noupdate -group {WriteBack stage} /testbench/textW
 add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} -divider {class check}
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
-add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
+add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
+add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
+add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
+add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
 add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
 add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
 add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
@@ -122,18 +122,18 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
-add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
-add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
-add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
+add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
+add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
@@ -211,135 +211,135 @@ add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
-add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
-add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
-add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
-add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
-add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
-add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
-add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
+add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/RAdr
+add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
+add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
+add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
+add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
+add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
+add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
+add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
+add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
+add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
@@ -387,9 +387,9 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /test
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
-add wave -noupdate -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
+add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
+add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
+add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
@@ -478,8 +478,20 @@ add wave -noupdate /testbench/dut/hart/ieu/c/BranchTakenE
 add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
 add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
 add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
+add wave -noupdate /testbench/dut/hart/ifu/PCF
+add wave -noupdate /testbench/dut/hart/priv/priv/BreakpointFaultM
+add wave -noupdate /testbench/dut/hart/priv/priv/DTLBLoadPageFaultM
+add wave -noupdate /testbench/dut/hart/priv/priv/DTLBStorePageFaultM
+add wave -noupdate /testbench/dut/hart/priv/priv/ebreakM
+add wave -noupdate /testbench/dut/hart/priv/priv/EcallFaultM
+add wave -noupdate /testbench/dut/hart/priv/priv/ecallM
+add wave -noupdate /testbench/dut/hart/priv/priv/ExceptionM
+add wave -noupdate /testbench/dut/hart/priv/priv/IllegalCSRAccessM
+add wave -noupdate /testbench/dut/hart/priv/priv/IllegalFPUInstrM
+add wave -noupdate /testbench/dut/hart/priv/priv/IllegalIEUInstrFaultM
+add wave -noupdate /testbench/dut/hart/priv/priv/InstrAccessFaultM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1} {{Cursor 5} {163846 ns} 0}
+WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1} {{Cursor 5} {209653 ns} 0}
 quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 314
@@ -495,4 +507,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {163681 ns} {164021 ns}
+WaveRestoreZoom {211096 ns} {211182 ns}
diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv
index 18bd32f5..091e1b25 100644
--- a/wally-pipelined/testbench/testbench-linux.sv
+++ b/wally-pipelined/testbench/testbench-linux.sv
@@ -283,8 +283,10 @@ module testbench();
   `INIT_CHECKPOINT_SIMPLE_ARRAY(HPMCOUNTER, [`XLEN-1:0],`COUNTERS-1,3);
   generate
     genvar i;
+/* -----\/----- EXCLUDED -----\/-----
     `INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPCFG,  [7:0],`PMP_ENTRIES-1,0);
     `INIT_CHECKPOINT_GENBLK_ARRAY(PMP_BASE, PMPADDR, [`XLEN-1:0],`PMP_ENTRIES-1,0);
+ -----/\----- EXCLUDED -----/\----- */
   endgenerate
   `INIT_CHECKPOINT_VAL(PC,         [`XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(MEDELEG,    [`XLEN-1:0]);
@@ -449,7 +451,7 @@ module testbench();
           force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM; \
         else \
           release dut.hart.ieu.dp.ReadDataM; \
-        if(textM.substr(0,5) == "rrame") begin \
+        if(textM.substr(0,5) == "rdtime") begin \
           //$display("%tns, %d instrs: Overwrite MTIME_CLINT on read of MTIME in memory stage.", $time, InstrCountW-1); \
           force dut.uncore.clint.clint.MTIME = ExpectedRegValueM; \
         end \
@@ -547,7 +549,7 @@ module testbench();
       #1;
       // override on special conditions
       if(~dut.hart.StallW) begin
-        if(textW.substr(0,5) == "rrame") begin
+        if(textW.substr(0,5) == "rdtime") begin
           //$display("%tns, %d instrs: Releasing force of MTIME_CLINT.", $time, InstrCountW);
           release dut.uncore.clint.clint.MTIME;
         end 

From 475fa0176731cd33a6fc1850edfb5b149a467e54 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Dec 2021 21:08:34 -0800
Subject: [PATCH 85/95] Fixing paths in wally-setup.sh

---
 wally-pipelined/src/privileged/privdec.sv    |  3 +--
 wally-pipelined/src/privileged/privileged.sv |  6 ++----
 wally-setup.sh                               | 22 +++++++++++++-------
 3 files changed, 17 insertions(+), 14 deletions(-)

diff --git a/wally-pipelined/src/privileged/privdec.sv b/wally-pipelined/src/privileged/privdec.sv
index ec01f414..5fe6419e 100644
--- a/wally-pipelined/src/privileged/privdec.sv
+++ b/wally-pipelined/src/privileged/privdec.sv
@@ -49,6 +49,5 @@ module privdec (
   assign IllegalPrivilegedInstrM = PrivilegedM & ~(uretM|sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
   assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions
 
-  // *** initially, wfi and sfencevma are nop
-  // *** zfenci extension?
+  // *** initially, wfi is nop
 endmodule
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index 5fd80fbe..bf08ade9 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -144,11 +144,9 @@ module privileged (
 
   ///////////////////////////////////////////
   // decode privileged instructions
-
-
   ///////////////////////////////////////////
-  //privdec pmd(.InstrM(InstrM[31:20]),.*);
-  privdec pmd(.InstrM(InstrM[31:20]), 
+
+   privdec pmd(.InstrM(InstrM[31:20]), 
               .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
               .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, 
               .uretM, .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
diff --git a/wally-setup.sh b/wally-setup.sh
index 4dba5495..00e35943 100644
--- a/wally-setup.sh
+++ b/wally-setup.sh
@@ -10,17 +10,23 @@ echo "Executing wally-setup.sh"
 export RISCV=/opt/riscv   # change this if you installed the tools in a different location
 
 # Tools
-export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH       # GCC tools
-export PATH=~/riscv-wally/bin:$PATH    # exe2memfile; change this if riscv-wally isn't at your home directory
-export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH    # Change this for your path to Modelsim
-export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
+# GCCZ
 export LD_LIBRARY_PATH=$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/lib:$LD_LIBRARY_PATH
-
-export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # *** is this the right license server now
+export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH       # GCC tools
+# Spike
+export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH
+export PATH=$RISCV/bin:$LD_LIBRARY_PATH
+# exe2memfile
+export PATH=~/riscv-wally/bin:$PATH    # exe2memfile; change this if riscv-wally isn't at your home directory
+# Verilator
+export PATH=/usr/local/bin/verilator:$PATH # Change this for your path to Verilator
+# ModelSim/Questa (vsim)
+export PATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin:$PATH    # Change this for your path to Modelsim
+export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server
 
 # Imperas; *** remove if not using
-PATH=/cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:/cad/riscv/imperas-riscv-tests/riscv-ovpsim/bin/Liux64:$PATH  # *** maybe take this out based on Imperas
+export PATH=/cad/riscv/imperas-riscv-tests/riscv-ovpsim-plus/bin/Linux64:/cad/riscv/imperas-riscv-tests/riscv-ovpsim/bin/Liux64:$PATH  # *** maybe take this out based on Imperas
 export LD_LIBRARY_PATH=/cad/imperas/Imperas.20200630/bin/Linux64:$LD_LIBRARY_PATH # remove if no imperas
-IMPERAS_HOME=/cad/imperas/Imperas.20200630
+export IMPERAS_HOME=/cad/imperas/Imperas.20200630
 source $IMPERAS_HOME/bin/setup.sh
 setupImperas $IMPERAS_HOME

From 09a24f7240aa3544e95628d23d5e6027cef8cc55 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Tue, 21 Dec 2021 05:10:14 +0000
Subject: [PATCH 86/95] Improving Wally installation makefile

---
 Makefile | 33 ++++++++++++++++-----------------
 1 file changed, 16 insertions(+), 17 deletions(-)

diff --git a/Makefile b/Makefile
index d715d72d..35da3a5e 100644
--- a/Makefile
+++ b/Makefile
@@ -1,24 +1,23 @@
-make all:
-# move these parts into compiling archtest separtately
-#	cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F
-#	cp -r addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/I addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D
-#	sed -i 's/--isa=rv32i /--isa=32if/' addins/riscv-isa-sim/arch_test_target/spike/device/rv32i_m/F/Makefile.include
-#	sed -i 's/--isa=rv64i /--isa=64id/' addins/riscv-isa-sim/arch_test_target/spike/device/rv64i_m/D/Makefile.include
-#	if [ -d "addins/riscv-isa-sim/build" ]; then echo "Build exists"; else mkdir addins/riscv-isa-sim/build; fi
-#	cd addins/riscv-isa-sim/build; ../configure --prefix=/cad/riscv/gcc/bin
-#	make -C addins/riscv-isa-sim/build
-#	sudo make install -C addins/riscv-isa-sim/build
-#	cp addins/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
-# update with path including $RISCV_TOOLS
-# separate into make tests and make regression
-    cp $RISCV/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
-	sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= $RISCV/riscv-isa-sim/arch_test_target' tests/wally-riscv-arch-test/Makefile.include
-	echo export RISCV_PREFIX = riscv64-unknown-elf- >> tests/wally-riscv-arch-test/Makefile.include
+all:
+	install
+	compile
+	regression
+
+# install copies over the Makefile.include from riscv-isa-sim
+# And corrects the TARGETDIR path and the RISCV_PREFIXZ
+
+install:
+	cp ${RISCV}/riscv-isa-sim/arch_test_target/spike/Makefile.include addins/riscv-arch-test/
+	sed -i '/export TARGETDIR ?=/c\export TARGETDIR ?= ${RISCV}/riscv-isa-sim/arch_test_target' addins/riscv-arch-test/Makefile.include
+	echo export RISCV_PREFIX = riscv64-unknown-elf- >> addins/riscv-arch-test/Makefile.include
+
+compile:
 	make -C addins/riscv-arch-test
 	make -C addins/riscv-arch-test XLEN=32
 	cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf
+
+regression:
 	make -C wally-pipelined/regression
-	
 
 
 

From 07810f402526ae36a99655d2c0c6d7c192aa6b85 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 20 Dec 2021 21:14:35 -0800
Subject: [PATCH 87/95] Renamed to setup.sh and fixed path bug

---
 wally-setup.sh => setup.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
 rename wally-setup.sh => setup.sh (97%)

diff --git a/wally-setup.sh b/setup.sh
similarity index 97%
rename from wally-setup.sh
rename to setup.sh
index 00e35943..fb132f9f 100644
--- a/wally-setup.sh
+++ b/setup.sh
@@ -15,7 +15,7 @@ export LD_LIBRARY_PATH=$RISCV/riscv-gnu-toolchain/lib:$RISCV/riscv-gnu-toolchain
 export PATH=$RISCV/riscv-gnu-toolchain/bin:$RISCV/riscv-gnu-toolchain/riscv64-unknown-elf/bin:$PATH       # GCC tools
 # Spike
 export LD_LIBRARY_PATH=$RISCV/lib:$LD_LIBRARY_PATH
-export PATH=$RISCV/bin:$LD_LIBRARY_PATH
+export PATH=$RISCV/bin:$PATH
 # exe2memfile
 export PATH=~/riscv-wally/bin:$PATH    # exe2memfile; change this if riscv-wally isn't at your home directory
 # Verilator

From ffe792bcfcab78c5b8040d5e6b0ef3a05e4918ac Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Dec 2021 23:27:37 -0600
Subject: [PATCH 88/95] Fixed bug on icache spill.  if the cpu stalled on the
 completion it was possible to use the wrong address for the sram read.  Also
 miss spill hit always selected the wrong address.

---
 wally-pipelined/src/cache/icachefsm.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index dd4e2e4a..aa49a55e 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -294,8 +294,8 @@ module icachefsm
           ICacheStallF = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  if(StallF) begin
-			NextState = STATE_CPU_BUSY;
-			SelAdr = 2'b01;
+			NextState = STATE_CPU_BUSY_SPILL;
+			SelAdr = 2'b10;
 		  end else begin
             NextState = STATE_READY;
 		  end

From 3f62a64056e316c8e78994b25e0dd23ebc4975f4 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Mon, 20 Dec 2021 23:45:55 -0600
Subject: [PATCH 89/95] Identified bug in the IFU which selects PCNextF when
 InvalidateICacheM is true.  If the ID is invalid PCNextF should NOT be PCE.

---
 wally-pipelined/src/ifu/ifu.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index a6b63f24..896359bd 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -187,6 +187,7 @@ module ifu (
          .s(BPPredWrongE),
          .y(PCNext1F));
 
+  // *** December 20, 2021 BUG Ross Thompson, If instructions in ID and IF are already invalid we don't pick PCE on icache invalidate.
   mux2 #(`XLEN) pcmux2(.d0(PCNext1F),
          .d1(PCE),
          .s(InvalidateICacheM),

From 8b97aaac3e9668320668b77ec2510c81a4b0f23e Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 21 Dec 2021 11:29:28 -0600
Subject: [PATCH 90/95] Fixed complex bug where FENCE is instruction class miss
 predicted as a taken branch.

---
 wally-pipelined/src/ifu/ifu.sv | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 896359bd..a0875e46 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -103,6 +103,9 @@ module ifu (
   
 (* mark_debug = "true" *)  logic [`PA_BITS-1:0]         PCPFmmu, PCNextFPhys; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width.
   logic [`XLEN+1:0]            PCFExt;
+  logic [`XLEN-1:0] 		   PCBPWrongInvalidate;
+  logic 					   BPPredWrongM;
+  
 
   generate
     if (`XLEN==32) begin
@@ -187,9 +190,13 @@ module ifu (
          .s(BPPredWrongE),
          .y(PCNext1F));
 
-  // *** December 20, 2021 BUG Ross Thompson, If instructions in ID and IF are already invalid we don't pick PCE on icache invalidate.
+  // December 20, 2021 Ross Thompson, If instructions in ID and IF are already invalid we don't pick PCE on icache invalidate.
+  // this only happens because of branch class miss prediction.  The Fence instruction was incorrectly predicted as a branch
+  // this means on the previous cycle the BPPredWrongE updated PCNextF to the correct fall through address.
+  // to fix we need to select the correct address PCF as the next PCNextF. Unforunately we must still flush the instruction in IF
+  // as we are deliberately invalidating the icache.  This address has to be refetched by the icache.
   mux2 #(`XLEN) pcmux2(.d0(PCNext1F),
-         .d1(PCE),
+         .d1(PCBPWrongInvalidate),
          .s(InvalidateICacheM),
          .y(PCNext2F));
   
@@ -206,6 +213,14 @@ module ifu (
   flop #(1) resetReg (.clk(clk),
         .d(reset),
         .q(reset_q));
+
+
+  flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM),
+								.d(BPPredWrongE), .q(BPPredWrongM));
+
+  mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), 
+											.s(BPPredWrongM & InvalidateICacheM), 
+											.y(PCBPWrongInvalidate));
   
   
   assign  PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment

From 7844d3f06478ebc164258653096d110f9f213c1f Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 21 Dec 2021 15:16:00 -0600
Subject: [PATCH 91/95] Fixed bug where the wrong address is read into the
 icache memory.

---
 wally-pipelined/src/cache/icachefsm.sv | 1 +
 1 file changed, 1 insertion(+)

diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index aa49a55e..1d579cd1 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -163,6 +163,7 @@ module icachefsm
 		  NextState = STATE_HIT_SPILL;
         end else if (~hit & ~spill) begin
           CntReset = 1'b1;
+		  SelAdr = 2'b01;                                         /// *********(
           NextState = STATE_MISS_FETCH_WDV;
         end else if (~hit & spill) begin
           CntReset = 1'b1;

From 6a8e917e06c003d3e391fdfd9245fc00576675a9 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 21 Dec 2021 15:59:56 -0600
Subject: [PATCH 92/95] It was possible for a load/store followed by tlb miss
 and update to have an exception and still commit its result to memory or
 register.

---
 wally-pipelined/src/cache/dcachefsm.sv | 18 +++++++-----------
 wally-pipelined/src/lsu/lsu.sv         |  4 +++-
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv
index eb191b9a..f11b3c3e 100644
--- a/wally-pipelined/src/cache/dcachefsm.sv
+++ b/wally-pipelined/src/cache/dcachefsm.sv
@@ -169,7 +169,7 @@ module dcachefsm
 		end
 
 		// Flush dcache to next level of memory
-		else if(FlushDCacheM  & ~(ExceptionM | PendingInterruptM)) begin
+		else if(FlushDCacheM) begin
 		  NextState = STATE_FLUSH;
 		  DCacheStall = 1'b1;
 		  SelAdrM = 2'b11;
@@ -178,7 +178,7 @@ module dcachefsm
 		end
 		
 		// amo hit
-		else if(AtomicM[1] & (&MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
+		else if(AtomicM[1] & (&MemRWM) & CacheableM & CacheHit) begin
 		  SelAdrM = 2'b10;
 		  DCacheStall = 1'b0;
 		  
@@ -194,7 +194,7 @@ module dcachefsm
 		  end
 		end
 		// read hit valid cached
-		else if(MemRWM[1] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
+		else if(MemRWM[1] & CacheableM & CacheHit) begin
 		  DCacheStall = 1'b0;
 		  LRUWriteEn = 1'b1;
 		  
@@ -207,7 +207,7 @@ module dcachefsm
 	      end
 		end
 		// write hit valid cached
-		else if (MemRWM[0] & CacheableM & ~(ExceptionM | PendingInterruptM) & CacheHit) begin
+		else if (MemRWM[0] & CacheableM & CacheHit) begin
 		  SelAdrM = 2'b10;
 		  DCacheStall = 1'b0;
 		  SRAMWordWriteEnableM = 1'b1;
@@ -223,29 +223,25 @@ module dcachefsm
 		  end
 		end
 		// read or write miss valid cached
-		else if((|MemRWM) & CacheableM & ~(ExceptionM | PendingInterruptM) & ~CacheHit) begin
+		else if((|MemRWM) & CacheableM & ~CacheHit) begin
 		  NextState = STATE_MISS_FETCH_WDV;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		end
 		// uncached write
-		else if(MemRWM[0] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
+		else if(MemRWM[0] & ~CacheableM) begin
 		  NextState = STATE_UNCACHED_WRITE;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		  AHBWrite = 1'b1;
 		end
 		// uncached read
-		else if(MemRWM[1] & ~CacheableM & ~(ExceptionM | PendingInterruptM)) begin
+		else if(MemRWM[1] & ~CacheableM) begin
 		  NextState = STATE_UNCACHED_READ;
 		  CntReset = 1'b1;
 		  DCacheStall = 1'b1;
 		  AHBRead = 1'b1;	  
 		end
-		// fault
-		else if(AnyCPUReqM & (ExceptionM | PendingInterruptM)) begin
-		  NextState = STATE_READY;
-		end
 		else NextState = STATE_READY;
       end
       
diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv
index 738124a9..ed7a9fcb 100644
--- a/wally-pipelined/src/lsu/lsu.sv
+++ b/wally-pipelined/src/lsu/lsu.sv
@@ -198,7 +198,9 @@ module lsu
   assign SelReplayCPURequest = (NextState == STATE_T0_REPLAY) | (NextState == STATE_T0_FAULT_REPLAY);
   assign SelHPTW = (CurrState == STATE_T3_DTLB_MISS) | (CurrState == STATE_T4_ITLB_MISS) |
 				  (CurrState == STATE_T5_ITLB_MISS) | (CurrState == STATE_T7_DITLB_MISS);
-  assign IgnoreRequest = CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM);
+  assign IgnoreRequest = (CurrState == STATE_T0_READY & (ITLBMissF | DTLBMissM | ExceptionM | PendingInterruptM)) |
+						 ((CurrState == STATE_T0_REPLAY | CurrState == STATE_T0_FAULT_REPLAY)
+						  & (ExceptionM | PendingInterruptM));
   
   assign WalkerInstrPageFaultF = WalkerInstrPageFaultRaw | CurrState == STATE_T0_FAULT_REPLAY;
   

From b15707bb849a93dd402b0ea06a2ca54333953f1e Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 22 Dec 2021 03:59:08 +0000
Subject: [PATCH 93/95] Fixed directory in Makefile for exe2memfile

---
 Makefile | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Makefile b/Makefile
index 35da3a5e..13d18c37 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 all:
-	install
-	compile
-	regression
+	make install
+	make compile
+	make regression
 
 # install copies over the Makefile.include from riscv-isa-sim
 # And corrects the TARGETDIR path and the RISCV_PREFIXZ
@@ -14,7 +14,7 @@ install:
 compile:
 	make -C addins/riscv-arch-test
 	make -C addins/riscv-arch-test XLEN=32
-	cd tests/wally-riscv-arch-test; exe2memfile.pl work/*/*/*.elf
+	cd addins/riscv-arch-test; exe2memfile.pl work/*/*/*.elf
 
 regression:
 	make -C wally-pipelined/regression

From f863bdc495df8d51fc79f3171d37be30e5fcd5d7 Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 21 Dec 2021 22:37:55 -0600
Subject: [PATCH 94/95] linux-wave.do changes.

---
 wally-pipelined/regression/linux-wave.do | 399 ++++++++++++-----------
 1 file changed, 208 insertions(+), 191 deletions(-)

diff --git a/wally-pipelined/regression/linux-wave.do b/wally-pipelined/regression/linux-wave.do
index c99dc2fe..e91874a8 100644
--- a/wally-pipelined/regression/linux-wave.do
+++ b/wally-pipelined/regression/linux-wave.do
@@ -1,36 +1,42 @@
 onerror {resume}
+quietly virtual function -install /testbench/dut/hart/ifu -env /testbench/dut/hart/ifu { &{/testbench/dut/hart/ifu/BPPredWrongM, /testbench/dut/hart/ifu/InvalidateICacheM }} temp
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /testbench/clk
 add wave -noupdate /testbench/reset
 add wave -noupdate /testbench/reset_ext
 add wave -noupdate -radix unsigned /testbench/InstrCountW
 add wave -noupdate /testbench/dut/hart/SATP_REGW
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
-add wave -noupdate -expand -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
-add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
-add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
-add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
-add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
-add wave -noupdate -group PCS /testbench/dut/hart/PCF
-add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
-add wave -noupdate -group PCS /testbench/dut/hart/PCE
-add wave -noupdate -group PCS /testbench/dut/hart/PCM
-add wave -noupdate -group PCS /testbench/PCW
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
+add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/hart/hzu/TrapM
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/StoreStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LSUStall
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
+add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DivBusyE
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/BreakpointFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/DTLBLoadPageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/DTLBStorePageFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ebreakM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/EcallFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ecallM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/ExceptionM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalCSRAccessM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalFPUInstrM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/IllegalIEUInstrFaultM
+add wave -noupdate -group HDU -expand -group traps /testbench/dut/hart/priv/priv/InstrAccessFaultM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
+add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
+add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
 add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
 add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/icache/FinalInstrRawF
 add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
@@ -113,6 +119,12 @@ add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/if
 add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredClassNonCFIWrongE
 add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
 add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/bpred/BPPredWrongE
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCNextF
+add wave -noupdate -group PCS /testbench/dut/hart/PCF
+add wave -noupdate -group PCS /testbench/dut/hart/ifu/PCD
+add wave -noupdate -group PCS /testbench/dut/hart/PCE
+add wave -noupdate -group PCS /testbench/dut/hart/PCM
+add wave -noupdate -group PCS /testbench/PCW
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F
@@ -122,18 +134,18 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
 add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
-add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
-add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
+add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
+add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
+add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/A
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/B
 add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ALUControl
@@ -160,11 +172,12 @@ add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/controller/NextS
 add wave -noupdate -group icache /testbench/dut/hart/ifu/ITLBMissF
 add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ITLBWriteF
 add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ReadLineF
-add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[0]/ValidBits}
-add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[1]/ValidBits}
-add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[2]/ValidBits}
-add wave -noupdate -group icache {/testbench/dut/hart/ifu/icache/MemWay[3]/ValidBits}
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SelAdr
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCNextF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/RAdr
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPF
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/PCPSpillF
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/hit
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/spill
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/ICacheStallF
@@ -173,12 +186,16 @@ add wave -noupdate -group icache -expand -group {fsm out and control} /testbench
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntReset
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/PreCntEn
 add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/controller/CntEn
+add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/hart/ifu/icache/FinalInstrRawF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
+add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/InstrPAdrF
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/FetchCountFlag
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/FetchCount
-add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrReadF
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/InstrAckF
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/controller/ICacheMemWriteEnable
 add wave -noupdate -group icache -expand -group memory /testbench/dut/hart/ifu/icache/ICacheMemWriteData
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/ICacheMemReadData
+add wave -noupdate -group icache /testbench/dut/hart/ifu/icache/SpillDataBlock0
 add wave -noupdate -group AHB -color Gold /testbench/dut/hart/ebu/BusState
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/NextBusState
 add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/hart/ebu/AtomicMaskedM
@@ -200,146 +217,149 @@ add wave -noupdate -group AHB /testbench/dut/hart/ebu/HMASTLOCK
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HADDRD
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HSIZED
 add wave -noupdate -group AHB /testbench/dut/hart/ebu/HWRITED
-add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/funct
-add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/result
-add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
-add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
-add wave -noupdate -expand -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
+add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/funct
+add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/result
+add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srca
+add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/srcb
+add wave -noupdate -group AMO_ALU /testbench/dut/hart/lsu/dcache/genblk3/amoalu/width
 add wave -noupdate -expand -group lsu -color Gold /testbench/dut/hart/lsu/CurrState
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/SelHPTW
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/InterlockStall
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/LSUStall
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultF
 add wave -noupdate -expand -group lsu /testbench/dut/hart/lsu/WalkerInstrPageFaultRaw
-add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrE
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/IEUAdrM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/RAdr
-add wave -noupdate -expand -group lsu -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
-add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
-add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
-add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
-add wave -noupdate -expand -group lsu -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
-add wave -noupdate -expand -group lsu -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
-add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
-add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
-add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
-add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
-add wave -noupdate -expand -group lsu -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
+add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/hart/lsu/dcache/dcachefsm/CurrState
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWriteEnableM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWayWriteEnable
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMWordEnable
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SRAMBlockWayWriteEnableM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/SelAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ReadDataBlockM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/SelReplayCPURequest
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrE
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/IEUAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/RAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix unsigned /testbench/dut/hart/lsu/dcache/FlushAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FlushWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/BasePAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/FetchCount
+add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/hart/lsu/dcache/CacheableM
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/DCacheMemWriteData
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/IgnoreRequest
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/ExceptionM
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[0]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/MemWay[0]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WriteWordEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[1]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/MemWay[1]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[2]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/hart/lsu/dcache/MemWay[2]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetValid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/SetDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ClearDirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/VDWriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -label TAG {/testbench/dut/hart/lsu/dcache/MemWay[3]/CacheTagMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/DirtyBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ValidBits}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word0 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[0]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word1 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[1]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word2 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[2]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/WriteEnable}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way3 -expand -group Way3Word3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/word[3]/CacheDataMem/StoredData}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetValid
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearValid
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/SetDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/hart/lsu/dcache/ClearDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/RAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/hart/lsu/dcache/MemWay[0]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/hart/lsu/dcache/MemWay[1]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/hart/lsu/dcache/MemWay[2]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/WayHit}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Valid}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/Dirty}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/hart/lsu/dcache/MemWay[3]/ReadTag}
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
+add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordMuxM
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
+add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemAdrE
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemPAdrM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/CacheableM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/FlushDCacheM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataM
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
+add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/WayHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
+add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/hart/lsu/dcache/FetchCount
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBPAdr
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBRead
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBWrite
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/AHBAck
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HRDATA
+add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Memory Side} /testbench/dut/hart/lsu/dcache/HWDATA
+add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/hart/lsu/dcache/FlushWay
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/EffectivePrivilegeMode
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/Translate
 add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/hart/lsu/dmmu/genblk1/tlb/tlbcontrol/DisableTranslation
@@ -379,6 +399,7 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testb
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
+add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWAdr
 add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
 add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
@@ -390,6 +411,7 @@ add wave -noupdate -expand -group lsu -expand -group ptwalker -group types /test
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/TLBWrite
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/ITLBMissF
 add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PhysicalAddress
+add wave -noupdate -expand -group itlb /testbench/dut/hart/ifu/immu/PMAInstrAccessFaultF
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
 add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
@@ -479,19 +501,14 @@ add wave -noupdate /testbench/dut/hart/ieu/c/BranchE
 add wave -noupdate /testbench/dut/hart/ifu/PCLinkE
 add wave -noupdate /testbench/dut/hart/lsu/DCtoAHBSizeM
 add wave -noupdate /testbench/dut/hart/ifu/PCF
-add wave -noupdate /testbench/dut/hart/priv/priv/BreakpointFaultM
-add wave -noupdate /testbench/dut/hart/priv/priv/DTLBLoadPageFaultM
-add wave -noupdate /testbench/dut/hart/priv/priv/DTLBStorePageFaultM
-add wave -noupdate /testbench/dut/hart/priv/priv/ebreakM
-add wave -noupdate /testbench/dut/hart/priv/priv/EcallFaultM
-add wave -noupdate /testbench/dut/hart/priv/priv/ecallM
-add wave -noupdate /testbench/dut/hart/priv/priv/ExceptionM
-add wave -noupdate /testbench/dut/hart/priv/priv/IllegalCSRAccessM
-add wave -noupdate /testbench/dut/hart/priv/priv/IllegalFPUInstrM
-add wave -noupdate /testbench/dut/hart/priv/priv/IllegalIEUInstrFaultM
-add wave -noupdate /testbench/dut/hart/priv/priv/InstrAccessFaultM
+add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR
+add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM
+add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB
+add wave -noupdate /testbench/dut/hart/ifu/temp
+add wave -noupdate /testbench/dut/hart/ifu/BPPredWrongM
+add wave -noupdate /testbench/dut/hart/ifu/InvalidateICacheM
 TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 23} {14157765 ns} 0} {{Cursor 3} {29725 ns} 1} {{Cursor 5} {209653 ns} 0}
+WaveRestoreCursors {{Cursor 9} {25261745 ns} 1} {{Cursor 10} {23549215 ns} 1} {{Cursor 11} {25261744 ns} 0}
 quietly wave cursor active 3
 configure wave -namecolwidth 250
 configure wave -valuecolwidth 314
@@ -507,4 +524,4 @@ configure wave -griddelta 40
 configure wave -timeline 0
 configure wave -timelineunits ns
 update
-WaveRestoreZoom {211096 ns} {211182 ns}
+WaveRestoreZoom {25261542 ns} {25261948 ns}

From a8c72c08a94dc6bf8f1922d5b60c8fea2ae167f1 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Wed, 22 Dec 2021 07:04:47 -0800
Subject: [PATCH 95/95] added wallyVirtIO.patch from Ross

---
 wallyVirtIO.patch | 542 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 542 insertions(+)
 create mode 100644 wallyVirtIO.patch

diff --git a/wallyVirtIO.patch b/wallyVirtIO.patch
new file mode 100644
index 00000000..76a1d240
--- /dev/null
+++ b/wallyVirtIO.patch
@@ -0,0 +1,542 @@
+diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
+index 4a3cd2599a..39b46e3122 100644
+--- a/hw/riscv/virt.c
++++ b/hw/riscv/virt.c
+@@ -20,6 +20,7 @@
+ 
+ #include "qemu/osdep.h"
+ #include "qemu/units.h"
++#include "qemu/log.h"
+ #include "qemu/error-report.h"
+ #include "qapi/error.h"
+ #include "hw/boards.h"
+@@ -44,19 +45,10 @@
+ #include "hw/display/ramfb.h"
+ 
+ static const MemMapEntry virt_memmap[] = {
+-    [VIRT_DEBUG] =       {        0x0,         0x100 },
+     [VIRT_MROM] =        {     0x1000,        0xf000 },
+-    [VIRT_TEST] =        {   0x100000,        0x1000 },
+-    [VIRT_RTC] =         {   0x101000,        0x1000 },
+     [VIRT_CLINT] =       {  0x2000000,       0x10000 },
+-    [VIRT_PCIE_PIO] =    {  0x3000000,       0x10000 },
+     [VIRT_PLIC] =        {  0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) },
+     [VIRT_UART0] =       { 0x10000000,         0x100 },
+-    [VIRT_VIRTIO] =      { 0x10001000,        0x1000 },
+-    [VIRT_FW_CFG] =      { 0x10100000,          0x18 },
+-    [VIRT_FLASH] =       { 0x20000000,     0x4000000 },
+-    [VIRT_PCIE_ECAM] =   { 0x30000000,    0x10000000 },
+-    [VIRT_PCIE_MMIO] =   { 0x40000000,    0x40000000 },
+     [VIRT_DRAM] =        { 0x80000000,           0x0 },
+ };
+ 
+@@ -67,139 +59,23 @@ static const MemMapEntry virt_memmap[] = {
+ /* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */
+ #define VIRT64_HIGH_PCIE_MMIO_SIZE  (16 * GiB)
+ 
+-static MemMapEntry virt_high_pcie_memmap;
+-
+ #define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
+ 
+-static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s,
+-                                       const char *name,
+-                                       const char *alias_prop_name)
+-{
+-    /*
+-     * Create a single flash device.  We use the same parameters as
+-     * the flash devices on the ARM virt board.
+-     */
+-    DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01);
+-
+-    qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
+-    qdev_prop_set_uint8(dev, "width", 4);
+-    qdev_prop_set_uint8(dev, "device-width", 2);
+-    qdev_prop_set_bit(dev, "big-endian", false);
+-    qdev_prop_set_uint16(dev, "id0", 0x89);
+-    qdev_prop_set_uint16(dev, "id1", 0x18);
+-    qdev_prop_set_uint16(dev, "id2", 0x00);
+-    qdev_prop_set_uint16(dev, "id3", 0x00);
+-    qdev_prop_set_string(dev, "name", name);
+-
+-    object_property_add_child(OBJECT(s), name, OBJECT(dev));
+-    object_property_add_alias(OBJECT(s), alias_prop_name,
+-                              OBJECT(dev), "drive");
+-
+-    return PFLASH_CFI01(dev);
+-}
+-
+-static void virt_flash_create(RISCVVirtState *s)
+-{
+-    s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0");
+-    s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1");
+-}
+-
+-static void virt_flash_map1(PFlashCFI01 *flash,
+-                            hwaddr base, hwaddr size,
+-                            MemoryRegion *sysmem)
+-{
+-    DeviceState *dev = DEVICE(flash);
+-
+-    assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE));
+-    assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
+-    qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
+-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+-
+-    memory_region_add_subregion(sysmem, base,
+-                                sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
+-                                                       0));
+-}
+-
+-static void virt_flash_map(RISCVVirtState *s,
+-                           MemoryRegion *sysmem)
+-{
+-    hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
+-    hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
+-
+-    virt_flash_map1(s->flash[0], flashbase, flashsize,
+-                    sysmem);
+-    virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize,
+-                    sysmem);
+-}
+-
+-static void create_pcie_irq_map(void *fdt, char *nodename,
+-                                uint32_t plic_phandle)
+-{
+-    int pin, dev;
+-    uint32_t
+-        full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {};
+-    uint32_t *irq_map = full_irq_map;
+-
+-    /* This code creates a standard swizzle of interrupts such that
+-     * each device's first interrupt is based on it's PCI_SLOT number.
+-     * (See pci_swizzle_map_irq_fn())
+-     *
+-     * We only need one entry per interrupt in the table (not one per
+-     * possible slot) seeing the interrupt-map-mask will allow the table
+-     * to wrap to any number of devices.
+-     */
+-    for (dev = 0; dev < GPEX_NUM_IRQS; dev++) {
+-        int devfn = dev * 0x8;
+-
+-        for (pin = 0; pin < GPEX_NUM_IRQS; pin++) {
+-            int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS);
+-            int i = 0;
+-
+-            irq_map[i] = cpu_to_be32(devfn << 8);
+-
+-            i += FDT_PCI_ADDR_CELLS;
+-            irq_map[i] = cpu_to_be32(pin + 1);
+-
+-            i += FDT_PCI_INT_CELLS;
+-            irq_map[i++] = cpu_to_be32(plic_phandle);
+-
+-            i += FDT_PLIC_ADDR_CELLS;
+-            irq_map[i] = cpu_to_be32(irq_nr);
+-
+-            irq_map += FDT_INT_MAP_WIDTH;
+-        }
+-    }
+-
+-    qemu_fdt_setprop(fdt, nodename, "interrupt-map",
+-                     full_irq_map, sizeof(full_irq_map));
+-
+-    qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask",
+-                           0x1800, 0, 0, 0x7);
+-}
+-
+ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+                        uint64_t mem_size, const char *cmdline, bool is_32_bit)
+ {
+     void *fdt;
+-    int i, cpu, socket;
++    //int i, cpu, socket;
++    int cpu, socket;
+     MachineState *mc = MACHINE(s);
+     uint64_t addr, size;
+     uint32_t *clint_cells, *plic_cells;
+     unsigned long clint_addr, plic_addr;
+     uint32_t plic_phandle[MAX_NODES];
+-    uint32_t cpu_phandle, intc_phandle, test_phandle;
++    uint32_t cpu_phandle, intc_phandle;
+     uint32_t phandle = 1, plic_mmio_phandle = 1;
+-    uint32_t plic_pcie_phandle = 1, plic_virtio_phandle = 1;
+     char *mem_name, *cpu_name, *core_name, *intc_name;
+     char *name, *clint_name, *plic_name, *clust_name;
+-    hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2;
+-    hwaddr flashbase = virt_memmap[VIRT_FLASH].base;
+-    static const char * const clint_compat[2] = {
+-        "sifive,clint0", "riscv,clint0"
+-    };
+-    static const char * const plic_compat[2] = {
+-        "sifive,plic-1.0.0", "riscv,plic0"
+-    };
+ 
+     if (mc->dtb) {
+         fdt = mc->fdt = load_device_tree(mc->dtb, &s->fdt_size);
+@@ -305,8 +181,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+             (memmap[VIRT_CLINT].size * socket);
+         clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr);
+         qemu_fdt_add_subnode(fdt, clint_name);
+-        qemu_fdt_setprop_string_array(fdt, clint_name, "compatible",
+-            (char **)&clint_compat, ARRAY_SIZE(clint_compat));
++        qemu_fdt_setprop_string(fdt, clint_name, "compatible", "riscv,clint0");
+         qemu_fdt_setprop_cells(fdt, clint_name, "reg",
+             0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size);
+         qemu_fdt_setprop(fdt, clint_name, "interrupts-extended",
+@@ -322,8 +197,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+             "#address-cells", FDT_PLIC_ADDR_CELLS);
+         qemu_fdt_setprop_cell(fdt, plic_name,
+             "#interrupt-cells", FDT_PLIC_INT_CELLS);
+-        qemu_fdt_setprop_string_array(fdt, plic_name, "compatible",
+-            (char **)&plic_compat, ARRAY_SIZE(plic_compat));
++        qemu_fdt_setprop_string(fdt, plic_name, "compatible", "riscv,plic0");
+         qemu_fdt_setprop(fdt, plic_name, "interrupt-controller", NULL, 0);
+         qemu_fdt_setprop(fdt, plic_name, "interrupts-extended",
+             plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4);
+@@ -342,95 +216,11 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+     for (socket = 0; socket < riscv_socket_count(mc); socket++) {
+         if (socket == 0) {
+             plic_mmio_phandle = plic_phandle[socket];
+-            plic_virtio_phandle = plic_phandle[socket];
+-            plic_pcie_phandle = plic_phandle[socket];
+-        }
+-        if (socket == 1) {
+-            plic_virtio_phandle = plic_phandle[socket];
+-            plic_pcie_phandle = plic_phandle[socket];
+-        }
+-        if (socket == 2) {
+-            plic_pcie_phandle = plic_phandle[socket];
+         }
+     }
+ 
+     riscv_socket_fdt_write_distance_matrix(mc, fdt);
+ 
+-    for (i = 0; i < VIRTIO_COUNT; i++) {
+-        name = g_strdup_printf("/soc/virtio_mmio@%lx",
+-            (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size));
+-        qemu_fdt_add_subnode(fdt, name);
+-        qemu_fdt_setprop_string(fdt, name, "compatible", "virtio,mmio");
+-        qemu_fdt_setprop_cells(fdt, name, "reg",
+-            0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
+-            0x0, memmap[VIRT_VIRTIO].size);
+-        qemu_fdt_setprop_cell(fdt, name, "interrupt-parent",
+-            plic_virtio_phandle);
+-        qemu_fdt_setprop_cell(fdt, name, "interrupts", VIRTIO_IRQ + i);
+-        g_free(name);
+-    }
+-
+-    name = g_strdup_printf("/soc/pci@%lx",
+-        (long) memmap[VIRT_PCIE_ECAM].base);
+-    qemu_fdt_add_subnode(fdt, name);
+-    qemu_fdt_setprop_cell(fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS);
+-    qemu_fdt_setprop_cell(fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS);
+-    qemu_fdt_setprop_cell(fdt, name, "#size-cells", 0x2);
+-    qemu_fdt_setprop_string(fdt, name, "compatible", "pci-host-ecam-generic");
+-    qemu_fdt_setprop_string(fdt, name, "device_type", "pci");
+-    qemu_fdt_setprop_cell(fdt, name, "linux,pci-domain", 0);
+-    qemu_fdt_setprop_cells(fdt, name, "bus-range", 0,
+-        memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1);
+-    qemu_fdt_setprop(fdt, name, "dma-coherent", NULL, 0);
+-    qemu_fdt_setprop_cells(fdt, name, "reg", 0,
+-        memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size);
+-    qemu_fdt_setprop_sized_cells(fdt, name, "ranges",
+-        1, FDT_PCI_RANGE_IOPORT, 2, 0,
+-        2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size,
+-        1, FDT_PCI_RANGE_MMIO,
+-        2, memmap[VIRT_PCIE_MMIO].base,
+-        2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size,
+-        1, FDT_PCI_RANGE_MMIO_64BIT,
+-        2, virt_high_pcie_memmap.base,
+-        2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size);
+-
+-    create_pcie_irq_map(fdt, name, plic_pcie_phandle);
+-    g_free(name);
+-
+-    test_phandle = phandle++;
+-    name = g_strdup_printf("/soc/test@%lx",
+-        (long)memmap[VIRT_TEST].base);
+-    qemu_fdt_add_subnode(fdt, name);
+-    {
+-        static const char * const compat[3] = {
+-            "sifive,test1", "sifive,test0", "syscon"
+-        };
+-        qemu_fdt_setprop_string_array(fdt, name, "compatible", (char **)&compat,
+-                                      ARRAY_SIZE(compat));
+-    }
+-    qemu_fdt_setprop_cells(fdt, name, "reg",
+-        0x0, memmap[VIRT_TEST].base,
+-        0x0, memmap[VIRT_TEST].size);
+-    qemu_fdt_setprop_cell(fdt, name, "phandle", test_phandle);
+-    test_phandle = qemu_fdt_get_phandle(fdt, name);
+-    g_free(name);
+-
+-    name = g_strdup_printf("/soc/reboot");
+-    qemu_fdt_add_subnode(fdt, name);
+-    qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-reboot");
+-    qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
+-    qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
+-    qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_RESET);
+-    g_free(name);
+-
+-    name = g_strdup_printf("/soc/poweroff");
+-    qemu_fdt_add_subnode(fdt, name);
+-    qemu_fdt_setprop_string(fdt, name, "compatible", "syscon-poweroff");
+-    qemu_fdt_setprop_cell(fdt, name, "regmap", test_phandle);
+-    qemu_fdt_setprop_cell(fdt, name, "offset", 0x0);
+-    qemu_fdt_setprop_cell(fdt, name, "value", FINISHER_PASS);
+-    g_free(name);
+-
+     name = g_strdup_printf("/soc/uart@%lx", (long)memmap[VIRT_UART0].base);
+     qemu_fdt_add_subnode(fdt, name);
+     qemu_fdt_setprop_string(fdt, name, "compatible", "ns16550a");
+@@ -445,102 +235,12 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap,
+     qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", name);
+     g_free(name);
+ 
+-    name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base);
+-    qemu_fdt_add_subnode(fdt, name);
+-    qemu_fdt_setprop_string(fdt, name, "compatible", "google,goldfish-rtc");
+-    qemu_fdt_setprop_cells(fdt, name, "reg",
+-        0x0, memmap[VIRT_RTC].base,
+-        0x0, memmap[VIRT_RTC].size);
+-    qemu_fdt_setprop_cell(fdt, name, "interrupt-parent", plic_mmio_phandle);
+-    qemu_fdt_setprop_cell(fdt, name, "interrupts", RTC_IRQ);
+-    g_free(name);
+-
+-    name = g_strdup_printf("/soc/flash@%" PRIx64, flashbase);
+-    qemu_fdt_add_subnode(mc->fdt, name);
+-    qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash");
+-    qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg",
+-                                 2, flashbase, 2, flashsize,
+-                                 2, flashbase + flashsize, 2, flashsize);
+-    qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4);
+-    g_free(name);
+-
+ update_bootargs:
+     if (cmdline) {
+         qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline);
+     }
+ }
+ 
+-static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem,
+-                                          hwaddr ecam_base, hwaddr ecam_size,
+-                                          hwaddr mmio_base, hwaddr mmio_size,
+-                                          hwaddr high_mmio_base,
+-                                          hwaddr high_mmio_size,
+-                                          hwaddr pio_base,
+-                                          DeviceState *plic)
+-{
+-    DeviceState *dev;
+-    MemoryRegion *ecam_alias, *ecam_reg;
+-    MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg;
+-    qemu_irq irq;
+-    int i;
+-
+-    dev = qdev_new(TYPE_GPEX_HOST);
+-
+-    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
+-
+-    ecam_alias = g_new0(MemoryRegion, 1);
+-    ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
+-    memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
+-                             ecam_reg, 0, ecam_size);
+-    memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias);
+-
+-    mmio_alias = g_new0(MemoryRegion, 1);
+-    mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
+-    memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
+-                             mmio_reg, mmio_base, mmio_size);
+-    memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias);
+-
+-    /* Map high MMIO space */
+-    high_mmio_alias = g_new0(MemoryRegion, 1);
+-    memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
+-                             mmio_reg, high_mmio_base, high_mmio_size);
+-    memory_region_add_subregion(get_system_memory(), high_mmio_base,
+-                                high_mmio_alias);
+-
+-    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base);
+-
+-    for (i = 0; i < GPEX_NUM_IRQS; i++) {
+-        irq = qdev_get_gpio_in(plic, PCIE_IRQ + i);
+-
+-        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq);
+-        gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i);
+-    }
+-
+-    return dev;
+-}
+-
+-static FWCfgState *create_fw_cfg(const MachineState *mc)
+-{
+-    hwaddr base = virt_memmap[VIRT_FW_CFG].base;
+-    hwaddr size = virt_memmap[VIRT_FW_CFG].size;
+-    FWCfgState *fw_cfg;
+-    char *nodename;
+-
+-    fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16,
+-                                  &address_space_memory);
+-    fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus);
+-
+-    nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
+-    qemu_fdt_add_subnode(mc->fdt, nodename);
+-    qemu_fdt_setprop_string(mc->fdt, nodename,
+-                            "compatible", "qemu,fw-cfg-mmio");
+-    qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg",
+-                                 2, base, 2, size);
+-    qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0);
+-    g_free(nodename);
+-    return fw_cfg;
+-}
+-
+ static void virt_machine_init(MachineState *machine)
+ {
+     const MemMapEntry *memmap = virt_memmap;
+@@ -554,7 +254,7 @@ static void virt_machine_init(MachineState *machine)
+     target_ulong firmware_end_addr, kernel_start_addr;
+     uint32_t fdt_load_addr;
+     uint64_t kernel_entry;
+-    DeviceState *mmio_plic, *virtio_plic, *pcie_plic;
++    DeviceState *mmio_plic;
+     int i, j, base_hartid, hart_count;
+ 
+     /* Check socket count limit */
+@@ -565,7 +265,7 @@ static void virt_machine_init(MachineState *machine)
+     }
+ 
+     /* Initialize sockets */
+-    mmio_plic = virtio_plic = pcie_plic = NULL;
++    mmio_plic = NULL;
+     for (i = 0; i < riscv_socket_count(machine); i++) {
+         if (!riscv_socket_check_hartids(machine, i)) {
+             error_report("discontinuous hartids in socket%d", i);
+@@ -634,15 +334,6 @@ static void virt_machine_init(MachineState *machine)
+         /* Try to use different PLIC instance based device type */
+         if (i == 0) {
+             mmio_plic = s->plic[i];
+-            virtio_plic = s->plic[i];
+-            pcie_plic = s->plic[i];
+-        }
+-        if (i == 1) {
+-            virtio_plic = s->plic[i];
+-            pcie_plic = s->plic[i];
+-        }
+-        if (i == 2) {
+-            pcie_plic = s->plic[i];
+         }
+     }
+ 
+@@ -654,13 +345,6 @@ static void virt_machine_init(MachineState *machine)
+             error_report("Limiting RAM size to 10 GiB");
+         }
+ #endif
+-        virt_high_pcie_memmap.base = VIRT32_HIGH_PCIE_MMIO_BASE;
+-        virt_high_pcie_memmap.size = VIRT32_HIGH_PCIE_MMIO_SIZE;
+-    } else {
+-        virt_high_pcie_memmap.size = VIRT64_HIGH_PCIE_MMIO_SIZE;
+-        virt_high_pcie_memmap.base = memmap[VIRT_DRAM].base + machine->ram_size;
+-        virt_high_pcie_memmap.base =
+-            ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
+     }
+ 
+     /* register system main memory (actual RAM) */
+@@ -681,10 +365,12 @@ static void virt_machine_init(MachineState *machine)
+ 
+     if (riscv_is_32bit(&s->soc[0])) {
+         firmware_end_addr = riscv_find_and_load_firmware(machine,
+-                                    RISCV32_BIOS_BIN, start_addr, NULL);
++                                    "opensbi-riscv32-generic-fw_dynamic.bin",
++                                    start_addr, NULL);
+     } else {
+         firmware_end_addr = riscv_find_and_load_firmware(machine,
+-                                    RISCV64_BIOS_BIN, start_addr, NULL);
++                                    "opensbi-riscv64-generic-fw_dynamic.bin",
++                                    start_addr, NULL);
+     }
+ 
+     if (machine->kernel_filename) {
+@@ -712,21 +398,6 @@ static void virt_machine_init(MachineState *machine)
+         kernel_entry = 0;
+     }
+ 
+-    if (drive_get(IF_PFLASH, 0, 0)) {
+-        /*
+-         * Pflash was supplied, let's overwrite the address we jump to after
+-         * reset to the base of the flash.
+-         */
+-        start_addr = virt_memmap[VIRT_FLASH].base;
+-    }
+-
+-    /*
+-     * Init fw_cfg.  Must be done before riscv_load_fdt, otherwise the device
+-     * tree cannot be altered and we get FDT_ERR_NOSPACE.
+-     */
+-    s->fw_cfg = create_fw_cfg(machine);
+-    rom_set_fw(s->fw_cfg);
+-
+     /* Compute the fdt load address in dram */
+     fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
+                                    machine->ram_size, machine->fdt);
+@@ -736,41 +407,10 @@ static void virt_machine_init(MachineState *machine)
+                               virt_memmap[VIRT_MROM].size, kernel_entry,
+                               fdt_load_addr, machine->fdt);
+ 
+-    /* SiFive Test MMIO device */
+-    sifive_test_create(memmap[VIRT_TEST].base);
+-
+-    /* VirtIO MMIO devices */
+-    for (i = 0; i < VIRTIO_COUNT; i++) {
+-        sysbus_create_simple("virtio-mmio",
+-            memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size,
+-            qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i));
+-    }
+-
+-    gpex_pcie_init(system_memory,
+-                   memmap[VIRT_PCIE_ECAM].base,
+-                   memmap[VIRT_PCIE_ECAM].size,
+-                   memmap[VIRT_PCIE_MMIO].base,
+-                   memmap[VIRT_PCIE_MMIO].size,
+-                   virt_high_pcie_memmap.base,
+-                   virt_high_pcie_memmap.size,
+-                   memmap[VIRT_PCIE_PIO].base,
+-                   DEVICE(pcie_plic));
+-
+-    serial_mm_init(system_memory, memmap[VIRT_UART0].base,
++   serial_mm_init(system_memory, memmap[VIRT_UART0].base,
+         0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193,
+         serial_hd(0), DEVICE_LITTLE_ENDIAN);
+ 
+-    sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base,
+-        qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ));
+-
+-    virt_flash_create(s);
+-
+-    for (i = 0; i < ARRAY_SIZE(s->flash); i++) {
+-        /* Map legacy -drive if=pflash to machine properties */
+-        pflash_cfi01_legacy_drive(s->flash[i],
+-                                  drive_get(IF_PFLASH, 0, i));
+-    }
+-    virt_flash_map(s, system_memory);
+ }
+ 
+ static void virt_machine_instance_init(Object *obj)
+diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
+index 991a6bb760..401028b8d9 100644
+--- a/target/riscv/cpu.c
++++ b/target/riscv/cpu.c
+@@ -269,6 +269,15 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
+     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcounteren ", env->mcounteren);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "misa ", env->misa);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch ", env->mscratch);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scounteren ", env->scounteren);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch ", env->sscratch);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec);
++    qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
++    
+     if (riscv_has_ext(env, RVH)) {
+         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
+     }