diff --git a/sim/imperas.ic b/sim/imperas.ic
index 2295c9d4..4c221f2a 100644
--- a/sim/imperas.ic
+++ b/sim/imperas.ic
@@ -4,24 +4,36 @@
 --showcommands
 
 # Core settings
+--override cpu/priv_version=1.12 
+--override cpu/user_version=20191213
+# arch
+--override cpu/mimpid=0x100
+--override refRoot/cpu/tvec_align=64
+
+#  clarify
+#--override refRoot/cpu/mtvec_sext=F
+
+--override cpu/tval_ii_code=T
+
+#--override cpu/time_undefined=T
+#--override cpu/cycle_undefined=T
+#--override cpu/instret_undefined=T
+#--override cpu/hpmcounter_undefined=T
+
+--override cpu/reset_address=0x80000000
+
 --override cpu/unaligned=F
 --override cpu/ignore_non_leaf_DAU=1
-#--override cpu/wfi_is_nop=T
---override cpu/mimpid=0x100
+--override cpu/wfi_is_nop=T
 --override cpu/misa_Extensions_mask=0x0
+#--override cpu/updatePTEA=T
+#--override cpu/updatePTED=T
+--override cpu/Sstc=T
 
+# THIS NEEDS FIXING to 16
 --override cpu/PMP_registers=16
 --override cpu/PMP_undefined=T
 
-# Wally-specific non-default configuraiton
---override refRoot/cpu/Sstc=T 
---override cpu/add_implicit_Extensions=B 
---override cpu/bitmanip_version=1.0.0
-
-# Illegal instruction should not contain the bit pattern
-# illegal pmp read contained this
-# --override cpu/tval_ii_code=F
-
 # PMA Settings 
 # 'r': read access allowed
 # 'w': write access allowed
@@ -51,19 +63,11 @@
 #-override  refRoot/cpu/cv/cover=basic
 #-override  refRoot/cpu/cv/extensions=RV32I
 
-
-
 # Add Imperas simulator application instruction tracing
---override cpu/show_c_prefix=T
-
---trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 800000
-
-# Exceptions and pagetables debug
---override cpu/debugflags=6
-
-# Turn on verbose output for Imperas simulator and Model
 --verbose
---override  cpu/verbose=1
+--trace --tracechange --traceshowicount --tracemode -tracemem ASX --monitornetschange --traceafter 0
+--override cpu/debugflags=6 --override cpu/verbose=1
+--override cpu/show_c_prefix=T
 
 # Store simulator output to logfile
 --output imperas.log
diff --git a/testbench/testbench-linux-imperas.sv b/testbench/testbench-linux-imperas.sv
index 00167e5f..d3d71626 100644
--- a/testbench/testbench-linux-imperas.sv
+++ b/testbench/testbench-linux-imperas.sv
@@ -413,10 +413,11 @@ module testbench;
         end
       end
 
-      always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));
-      always @(dut.core.MExtInt)   void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt));
-      always @(dut.core.SExtInt)   void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt));
-      always @(dut.core.MSwInt)    void'(rvvi.net_push("MSWInterrupt",       dut.core.MSwInt));
+      always @(dut.core.MTimerInt)   void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));
+      always @(dut.core.MExtInt)     void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt));
+      always @(dut.core.SExtInt)     void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt));
+      always @(dut.core.MSwInt)      void'(rvvi.net_push("MSWInterrupt",       dut.core.MSwInt));
+      always @(dut.core.priv.priv.csr.csrs.csrs.STimerInt) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csrs.csrs.STimerInt));
 
       final begin
         void'(rvviRefShutdown());
diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv
index f63c640d..56ca763a 100644
--- a/testbench/testbench_imperas.sv
+++ b/testbench/testbench_imperas.sv
@@ -198,10 +198,12 @@ module testbench;
       
     end
 
-    always @(dut.core.MTimerInt) void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));
-    always @(dut.core.MExtInt)   void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt));
-    always @(dut.core.SExtInt)   void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt));
-    always @(dut.core.MSwInt)    void'(rvvi.net_push("MSWInterrupt",       dut.core.MSwInt));
+    always @(dut.core.MTimerInt)   void'(rvvi.net_push("MTimerInterrupt",    dut.core.MTimerInt));
+    always @(dut.core.MExtInt)     void'(rvvi.net_push("MExternalInterrupt", dut.core.MExtInt));
+    always @(dut.core.SExtInt)     void'(rvvi.net_push("SExternalInterrupt", dut.core.SExtInt));
+    always @(dut.core.MSwInt)      void'(rvvi.net_push("MSWInterrupt",       dut.core.MSwInt));
+    always @(dut.core.priv.priv.csr.csrs.csrs.STimerInt) void'(rvvi.net_push("STimerInterrupt", dut.core.priv.priv.csr.csrs.csrs.STimerInt));
+
 
     final begin
       void'(rvviRefShutdown());