diff --git a/fpga/constraints/debug2.xdc b/fpga/constraints/debug2.xdc
index c08f3710..585d3b82 100644
--- a/fpga/constraints/debug2.xdc
+++ b/fpga/constraints/debug2.xdc
@@ -475,7 +475,7 @@ connect_debug_port u_ila_0/probe103 [get_nets [list wallypipelinedsoc/core/ifu/I
 create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe104]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe104]
-connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.INSTRET_REGW[63]}]]
+connect_debug_port u_ila_0/probe104 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[0]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[1]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[2]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[3]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[4]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[5]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[6]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[7]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[8]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[9]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[10]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[11]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[12]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[13]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[14]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[15]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[16]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[17]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[18]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[19]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[20]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[21]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[22]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[23]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[24]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[25]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[26]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[27]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[28]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[29]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[30]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[31]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[32]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[33]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[34]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[35]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[36]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[37]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[38]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[39]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[40]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[41]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[42]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[43]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[44]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[45]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[46]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[47]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[48]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[49]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[50]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[51]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[52]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[53]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[54]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[55]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[56]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[57]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[58]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[59]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[60]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[61]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[62]} {wallypipelinedsoc/core/priv.priv/csr/counters/counters.HPMCOUNTER_REGW[2]__0[63]}]]
 
 
 create_debug_port u_ila_0 probe
@@ -743,3 +743,75 @@ create_debug_port u_ila_0 probe
 set_property port_width 64 [get_debug_ports u_ila_0/probe154]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe154]
 connect_debug_port u_ila_0/probe154 [get_nets [list {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[0]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[1]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[2]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[3]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[4]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[5]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[6]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[7]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[8]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[9]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[10]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[11]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[12]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[13]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[14]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[15]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[16]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[17]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[18]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[19]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[20]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[21]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[22]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[23]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[24]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[25]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[26]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[27]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[28]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[29]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[30]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[31]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[32]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[33]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[34]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[35]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[36]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[37]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[38]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[39]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[40]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[41]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[42]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[43]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[44]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[45]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[46]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[47]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[48]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[49]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[50]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[51]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[52]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[53]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[54]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[55]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[56]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[57]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[58]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[59]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[60]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[61]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[62]} {wallypipelinedsoc/core/priv.priv/csr/csrs/csrs.SSCRATCH_REGW[63]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 11 [get_debug_ports u_ila_0/probe155]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe155]
+connect_debug_port u_ila_0/probe155 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/RBR[0]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[1]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[2]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[3]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[4]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[5]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[6]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[7]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[8]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[9]} {wallypipelinedsoc/uncore/uart.uart/u/RBR[10]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 1 [get_debug_ports u_ila_0/probe156]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe156]
+connect_debug_port u_ila_0/probe156 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxparityerr} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe157]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe157]
+connect_debug_port u_ila_0/probe157 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/rxstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/rxstate[1]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 2 [get_debug_ports u_ila_0/probe158]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe158]
+connect_debug_port u_ila_0/probe158 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/txstate[0]} {wallypipelinedsoc/uncore/uart.uart/u/txstate[1]} ]]
+
+
+create_debug_port u_ila_0 probe
+set_property port_width 8 [get_debug_ports u_ila_0/probe159]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe159]
+connect_debug_port u_ila_0/probe159 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LCR[7]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 8 [get_debug_ports u_ila_0/probe160]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe160]
+connect_debug_port u_ila_0/probe160 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/LSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[3]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[4]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[5]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[6]} {wallypipelinedsoc/uncore/uart.uart/u/LSR[7]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 8 [get_debug_ports u_ila_0/probe161]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe161]
+connect_debug_port u_ila_0/probe161 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/SCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/SCR[7]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 8 [get_debug_ports u_ila_0/probe162]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe162]
+connect_debug_port u_ila_0/probe162 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLL[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLL[7]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 8 [get_debug_ports u_ila_0/probe163]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe163]
+connect_debug_port u_ila_0/probe163 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/DLM[0]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[1]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[2]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[3]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[4]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[5]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[6]} {wallypipelinedsoc/uncore/uart.uart/u/DLM[7]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe164]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe164]
+connect_debug_port u_ila_0/probe164 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/IER[0]} {wallypipelinedsoc/uncore/uart.uart/u/IER[1]} {wallypipelinedsoc/uncore/uart.uart/u/IER[2]} {wallypipelinedsoc/uncore/uart.uart/u/IER[3]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 4 [get_debug_ports u_ila_0/probe165]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe165]
+connect_debug_port u_ila_0/probe165 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MSR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MSR[3]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 5 [get_debug_ports u_ila_0/probe166]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe166]
+connect_debug_port u_ila_0/probe166 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/MCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/MCR[4]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 8 [get_debug_ports u_ila_0/probe167]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe167]
+connect_debug_port u_ila_0/probe167 [get_nets [list {wallypipelinedsoc/uncore/uart.uart/u/FCR[0]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[1]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[2]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[3]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[4]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[5]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[6]} {wallypipelinedsoc/uncore/uart.uart/u/FCR[7]} ]]
+
+create_debug_port u_ila_0 probe
+set_property port_width 64 [get_debug_ports u_ila_0/probe168]
+set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe168]
+connect_debug_port u_ila_0/probe168 [get_nets [list {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[0]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[1]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[2]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[3]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[4]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[5]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[6]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[7]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[8]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[9]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[10]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[11]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[12]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[13]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[14]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[15]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[16]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[17]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[18]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[19]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[20]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[21]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[22]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[23]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[24]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[25]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[26]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[27]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[28]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[29]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[30]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[31]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[32]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[33]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[34]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[35]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[36]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[37]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[38]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[39]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[40]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[41]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[42]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[43]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[44]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[45]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[46]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[47]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[48]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[49]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[50]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[51]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[52]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[53]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[54]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[55]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[56]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[57]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[58]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[59]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[60]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[61]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[62]} {wallypipelinedsoc/core/ieu/dp/regf/rf[10]__0[63]} ]]
diff --git a/fpga/generator/wave_config.wcfg b/fpga/generator/wave_config.wcfg
index f98274f2..9a6af16f 100644
--- a/fpga/generator/wave_config.wcfg
+++ b/fpga/generator/wave_config.wcfg
@@ -10,14 +10,14 @@
    </db_ref_list>
    <zoom_setting>
       <ZoomStartTime time="0fs"></ZoomStartTime>
-      <ZoomEndTime time="16385fs"></ZoomEndTime>
-      <Cursor1Time time="6fs"></Cursor1Time>
+      <ZoomEndTime time="168fs"></ZoomEndTime>
+      <Cursor1Time time="0fs"></Cursor1Time>
    </zoom_setting>
    <column_width_setting>
       <NameColumnWidth column_width="452"></NameColumnWidth>
-      <ValueColumnWidth column_width="145"></ValueColumnWidth>
+      <ValueColumnWidth column_width="141"></ValueColumnWidth>
    </column_width_setting>
-   <WVObjectSize size="29" />
+   <WVObjectSize size="11" />
    <wave_markers>
    </wave_markers>
    <wvobject type="array" fp_name="wallypipelinedsoc/core/PCM">
@@ -53,7 +53,6 @@
    <wvobject type="group" fp_name="group468">
       <obj_property name="label">CPU to LSU</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
       <wvobject type="array" fp_name="wallypipelinedsoc/core/IEUAdrM">
          <obj_property name="DisplayName">FullPathName</obj_property>
          <obj_property name="ElementShortName">wallypipelinedsoc/core/IEUAdrM[63:0]</obj_property>
@@ -111,7 +110,6 @@
    <wvobject type="group" fp_name="group470">
       <obj_property name="label">PLIC</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
       <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/requests">
          <obj_property name="DisplayName">FullPathName</obj_property>
          <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/requests[12:1]</obj_property>
@@ -140,7 +138,6 @@
    <wvobject type="group" fp_name="group471">
       <obj_property name="label">interrupts</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
       <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
          <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
          <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
@@ -178,7 +175,6 @@
    <wvobject type="group" fp_name="group463">
       <obj_property name="label">LSU to Bus</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
       <wvobject type="logic" fp_name="wallypipelinedsoc/core/lsu/LSUBusRead">
          <obj_property name="DisplayName">FullPathName</obj_property>
          <obj_property name="ElementShortName">wallypipelinedsoc/core/lsu/LSUBusRead</obj_property>
@@ -312,7 +308,6 @@
    <wvobject type="group" fp_name="group487">
       <obj_property name="label">sdc</obj_property>
       <obj_property name="DisplayName">label</obj_property>
-      <obj_property name="isExpanded"></obj_property>
       <wvobject type="logic" fp_name="wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q">
          <obj_property name="DisplayName">FullPathName</obj_property>
          <obj_property name="ElementShortName">wallypipelinedsoc/uncore/sdc.SDC/sd_top/r_DAT_ERROR_Q</obj_property>
@@ -352,144 +347,4 @@
          <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
       </wvobject>
    </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/IP_REGW_writeable[11:0]</obj_property>
-      <obj_property name="ObjectShortName">IP_REGW_writeable[11:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/MExtIntM</obj_property>
-      <obj_property name="ObjectShortName">MExtIntM</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SExtIntM</obj_property>
-      <obj_property name="ObjectShortName">SExtIntM</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/SwIntM</obj_property>
-      <obj_property name="ObjectShortName">SwIntM</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="logic" fp_name="wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csri/TimerIntM</obj_property>
-      <obj_property name="ObjectShortName">TimerIntM</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MEDELEG_REGW[63:0]</obj_property>
-      <obj_property name="ObjectShortName">MEDELEG_REGW[63:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/core/priv.priv/csr/csrm/MIDELEG_REGW[11:0]</obj_property>
-      <obj_property name="ObjectShortName">MIDELEG_REGW[11:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIMECMP">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIMECMP[63:0]</obj_property>
-      <obj_property name="ObjectShortName">MTIMECMP[63:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/clint.clint/MTIME">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/clint.clint/MTIME[63:0]</obj_property>
-      <obj_property name="ObjectShortName">MTIME[63:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intEn[1]__0">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intEn[1]__0[10:1]</obj_property>
-      <obj_property name="ObjectShortName">intEn[1]__0[10:1]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/intPriority[10]">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/intPriority[10][2:0]</obj_property>
-      <obj_property name="ObjectShortName">intPriority[10][2:0]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1]">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][1][10:1]</obj_property>
-      <obj_property name="ObjectShortName">irqMatrix[1][1][10:1]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2]">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][2][10:1]</obj_property>
-      <obj_property name="ObjectShortName">irqMatrix[1][2][10:1]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3]">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][3][10:1]</obj_property>
-      <obj_property name="ObjectShortName">irqMatrix[1][3][10:1]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4]">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][4][10:1]</obj_property>
-      <obj_property name="ObjectShortName">irqMatrix[1][4][10:1]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5]">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][5][10:1]</obj_property>
-      <obj_property name="ObjectShortName">irqMatrix[1][5][10:1]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6]">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][6][10:1]</obj_property>
-      <obj_property name="ObjectShortName">irqMatrix[1][6][10:1]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
-   <wvobject type="array" fp_name="wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7]">
-      <obj_property name="DisplayName">FullPathName</obj_property>
-      <obj_property name="ElementShortName">wallypipelinedsoc/uncore/plic.plic/irqMatrix[1][7][10:1]</obj_property>
-      <obj_property name="ObjectShortName">irqMatrix[1][7][10:1]</obj_property>
-      <obj_property name="Radix">HEXRADIX</obj_property>
-      <obj_property name="LABELRADIX">true</obj_property>
-      <obj_property name="WaveformStyle">STYLE_DIGITAL</obj_property>
-   </wvobject>
 </wave_config>
diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh
index 7587a9f2..6f273c0d 100644
--- a/pipelined/config/buildroot/wally-config.vh
+++ b/pipelined/config/buildroot/wally-config.vh
@@ -78,6 +78,9 @@
 // Address space
 `define RESET_VECTOR 64'h0000000000001000
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -126,6 +129,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 1
diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh
index fc63937c..b101a679 100644
--- a/pipelined/config/fpga/wally-config.vh
+++ b/pipelined/config/fpga/wally-config.vh
@@ -79,6 +79,9 @@
 // Address space
 `define RESET_VECTOR 64'h0000000000001000
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -134,6 +137,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 1
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 1
diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh
index 42e20aff..5832033a 100644
--- a/pipelined/config/rv32e/wally-config.vh
+++ b/pipelined/config/rv32e/wally-config.vh
@@ -80,6 +80,9 @@
 // Address space
 `define RESET_VECTOR 32'h80000000
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -131,6 +134,7 @@
 `define BPRED_ENABLED 0
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh
index 022447ff..41645e8a 100644
--- a/pipelined/config/rv32gc/wally-config.vh
+++ b/pipelined/config/rv32gc/wally-config.vh
@@ -78,6 +78,9 @@
 // Address space
 `define RESET_VECTOR 32'h80000000
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -129,6 +132,7 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv32ia/wally-config.vh b/pipelined/config/rv32ia/wally-config.vh
index 93042b8c..ed7b52d3 100644
--- a/pipelined/config/rv32ia/wally-config.vh
+++ b/pipelined/config/rv32ia/wally-config.vh
@@ -80,6 +80,9 @@
 // Address space
 `define RESET_VECTOR 32'h80000000
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -131,6 +134,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh
index fcd3c8e5..b615c739 100644
--- a/pipelined/config/rv32ic/wally-config.vh
+++ b/pipelined/config/rv32ic/wally-config.vh
@@ -78,6 +78,9 @@
 // Address space
 `define RESET_VECTOR 32'h80000000
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -129,6 +132,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh
index 005a1de3..417051f1 100644
--- a/pipelined/config/rv64BP/wally-config.vh
+++ b/pipelined/config/rv64BP/wally-config.vh
@@ -59,7 +59,7 @@
 
 // TLB configuration.  Entries should be a power of 2
 `define ITLB_ENTRIES 32
-`define DTLB_ENTRIES 32
+`define DTLB_ENTRIES 32 
 
 // Cache configuration.  Sizes should be a power of two
 // typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
@@ -82,6 +82,9 @@
 // Bus Interface width
 `define AHBW 64
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -132,6 +135,8 @@
 //`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
 `define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL"  or BPLOCALPAg or BPGSHARE
 `define TESTSBP 1
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh
index d25827b7..da74f981 100644
--- a/pipelined/config/rv64fp/wally-config.vh
+++ b/pipelined/config/rv64fp/wally-config.vh
@@ -84,6 +84,9 @@
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
 `define BOOTROM_SUPPORTED 1'b1
 `define BOOTROM_BASE   56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
@@ -130,6 +133,8 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
+
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh
index 6af3c7bd..b069a532 100644
--- a/pipelined/config/rv64gc/wally-config.vh
+++ b/pipelined/config/rv64gc/wally-config.vh
@@ -82,6 +82,9 @@
 // Bus Interface width
 `define AHBW 64
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Physiccal Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -132,6 +135,7 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64ia/wally-config.vh b/pipelined/config/rv64ia/wally-config.vh
index 43bd1ecd..0145930e 100644
--- a/pipelined/config/rv64ia/wally-config.vh
+++ b/pipelined/config/rv64ia/wally-config.vh
@@ -82,6 +82,9 @@
 // Bus Interface width
 `define AHBW 64
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Physiccal Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -132,6 +135,7 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh
index c46dbfe7..59230476 100644
--- a/pipelined/config/rv64ic/wally-config.vh
+++ b/pipelined/config/rv64ic/wally-config.vh
@@ -82,6 +82,9 @@
 // Bus Interface width
 `define AHBW 64
 
+// WFI Timeout Wait
+`define WFI_TIMEOUT_BIT 20
+
 // Peripheral Physiccal Addresses
 // Peripheral memory space extends from BASE to BASE+RANGE
 // Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
@@ -132,6 +135,7 @@
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0
+`define BPRED_SIZE 10
 
 `define REPLAY 0
 `define HPTW_WRITES_SUPPORTED 0
diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally
index cbd2caf7..c37186d0 100755
--- a/pipelined/regression/regression-wally
+++ b/pipelined/regression/regression-wally
@@ -45,7 +45,7 @@ configs = [
     )
 ]
 def getBuildrootTC(short):
-    INSTR_LIMIT = 100000 # multiple of 100000
+    INSTR_LIMIT = 4000000 # multiple of 100000; 4M is interesting because it gets into the kernel and enabling VM
     MAX_EXPECTED = 246000000
     if short:
         BRcmd="vsim > {} -c <<!\ndo wally-pipelined-batch.do buildroot buildroot $RISCV "+str(INSTR_LIMIT)+" 1 0\n!"
diff --git a/pipelined/regression/wkdir/README b/pipelined/regression/wkdir/README
deleted file mode 100644
index e69de29b..00000000
diff --git a/pipelined/src/fma/baby_torture.tv b/pipelined/src/fma/baby_torture.tv
new file mode 100644
index 00000000..3452b9e4
--- /dev/null
+++ b/pipelined/src/fma/baby_torture.tv
@@ -0,0 +1,1249 @@
+// Torture tests generated Tue Apr 19 15:04:28 2022 by ./torturegen.pl
+
+////////// Testcases from f16_add_rz.tv of type add rounding mode 0
+0000_0000_FA02_04_FA02_0 // f16_add_rz.tv line 500 0000_FA02_FA02_00 0 + -1.01000000010 x 2^15 = -1.01000000010 x 2^15
+93FF_0000_EBFF_04_EBFF_1 // f16_add_rz.tv line 1000 93FF_EBFF_EBFF_01 -1.01111111111 x 2^-11 + -1.01111111111 x 2^11 = -1.01111111111 x 2^11
+// Skipped denorm f16_add_rz.tv line 1500 03FF_C401_C400_01 Denorm + -1.00000000001 x 2^2 = -1.00000000000 x 2^2
+// Skipped denorm f16_add_rz.tv line 2000 03FE_0001_03FF_00 Denorm + Denorm = Denorm
+54CE_0000_BC00_04_54BE_0 // f16_add_rz.tv line 2500 54CE_BC00_54BE_00 1.00011001110 x 2^6 + -1.00000000000 x 2^0 = 1.00010111110 x 2^6
+0401_0000_B7FE_04_B7FD_1 // f16_add_rz.tv line 3000 0401_B7FE_B7FD_01 1.00000000001 x 2^-14 + -1.01111111110 x 2^-2 = -1.01111111101 x 2^-2
+07FF_0000_C3FF_04_C3FE_1 // f16_add_rz.tv line 3500 07FF_C3FF_C3FE_01 1.01111111111 x 2^-14 + -1.01111111111 x 2^1 = -1.01111111110 x 2^1
+9C3B_0000_87FF_04_9C5A_1 // f16_add_rz.tv line 4000 9C3B_87FF_9C5A_01 -1.00000111011 x 2^-8 + -1.01111111111 x 2^-14 = -1.00001011010 x 2^-8
+// Skipped denorm f16_add_rz.tv line 4500 1000_8001_0FFF_01 1.00000000000 x 2^-11 + -Denorm = 1.01111111111 x 2^-12
+1001_0000_2FBB_04_2FC3_1 // f16_add_rz.tv line 5000 1001_2FBB_2FC3_01 1.00000000001 x 2^-11 + 1.01110111011 x 2^-4 = 1.01111000011 x 2^-4
+37EE_0000_7800_04_7800_1 // f16_add_rz.tv line 5500 37EE_7800_7800_01 1.01111101110 x 2^-2 + 1.00000000000 x 2^15 = 1.00000000000 x 2^15
+13FE_0000_47FE_04_47FE_1 // f16_add_rz.tv line 6000 13FE_47FE_47FE_01 1.01111111110 x 2^-11 + 1.01111111110 x 2^2 = 1.01111111110 x 2^2
+3400_0000_CA47_04_CA27_0 // f16_add_rz.tv line 6500 3400_CA47_CA27_00 1.00000000000 x 2^-2 + -1.01001000111 x 2^3 = -1.01000100111 x 2^3
+30EE_0000_3FFF_04_404E_1 // f16_add_rz.tv line 7000 30EE_3FFF_404E_01 1.00011101110 x 2^-3 + 1.01111111111 x 2^0 = 1.00001001110 x 2^1
+37FF_0000_3801_04_3C00_1 // f16_add_rz.tv line 7500 37FF_3801_3C00_01 1.01111111111 x 2^-2 + 1.00000000001 x 2^-1 = 1.00000000000 x 2^0
+37FE_0000_B783_04_27B0_0 // f16_add_rz.tv line 8000 37FE_B783_27B0_00 1.01111111110 x 2^-2 + -1.01110000011 x 2^-2 = 1.01110110000 x 2^-6
+0EBE_0000_1000_04_135F_0 // f16_add_rz.tv line 8500 0EBE_1000_135F_00 1.01010111110 x 2^-12 + 1.00000000000 x 2^-11 = 1.01101011111 x 2^-11
+// Skipped denorm f16_add_rz.tv line 9000 3801_03FE_3801_01 1.00000000001 x 2^-1 + Denorm = 1.00000000001 x 2^-1
+3801_0000_480F_04_484F_1 // f16_add_rz.tv line 9500 3801_480F_484F_01 1.00000000001 x 2^-1 + 1.00000001111 x 2^3 = 1.00001001111 x 2^3
+// Skipped denorm f16_add_rz.tv line 10000 003E_FBFF_FBFE_01 Denorm + -1.01111111111 x 2^15 = -1.01111111110 x 2^15
+3BFE_0000_E801_04_E800_1 // f16_add_rz.tv line 10500 3BFE_E801_E800_01 1.01111111110 x 2^-1 + -1.00000000001 x 2^11 = -1.00000000000 x 2^11
+3C00_0000_88D3_04_3BFF_1 // f16_add_rz.tv line 11000 3C00_88D3_3BFF_01 1.00000000000 x 2^0 + -1.00011010011 x 2^-13 = 1.01111111111 x 2^-1
+257F_0000_C000_04_BFEA_1 // f16_add_rz.tv line 11500 257F_C000_BFEA_01 1.00101111111 x 2^-6 + -1.00000000000 x 2^1 = -1.01111101010 x 2^0
+3FFF_0000_BBFE_04_3C00_0 // f16_add_rz.tv line 12000 3FFF_BBFE_3C00_00 1.01111111111 x 2^0 + -1.01111111110 x 2^-1 = 1.00000000000 x 2^0
+3FFE_0000_4AFD_04_4BFC_1 // f16_add_rz.tv line 12500 3FFE_4AFD_4BFC_01 1.01111111110 x 2^0 + 1.01011111101 x 2^3 = 1.01111111100 x 2^3
+B7FF_0000_93FF_04_B801_1 // f16_add_rz.tv line 13000 B7FF_93FF_B801_01 -1.01111111111 x 2^-2 + -1.01111111111 x 2^-11 = -1.00000000001 x 2^-1
+4001_0000_8401_04_4000_1 // f16_add_rz.tv line 13500 4001_8401_4000_01 1.00000000001 x 2^1 + -1.00000000001 x 2^-14 = 1.00000000000 x 2^1
+43FF_0000_3808_04_4480_1 // f16_add_rz.tv line 14000 43FF_3808_4480_01 1.01111111111 x 2^1 + 1.00000001000 x 2^-1 = 1.00010000000 x 2^2
+AC0A_0000_7C00_04_7C00_0 // f16_add_rz.tv line 14500 AC0A_7C00_7C00_00 -1.00000001010 x 2^-4 + INF = INF
+4400_0000_6BFE_04_6C00_0 // f16_add_rz.tv line 15000 4400_6BFE_6C00_00 1.00000000000 x 2^2 + 1.01111111110 x 2^11 = 1.00000000000 x 2^12
+4401_0000_D3F2_04_D371_1 // f16_add_rz.tv line 15500 4401_D3F2_D371_01 1.00000000001 x 2^2 + -1.01111110010 x 2^5 = -1.01101110001 x 2^5
+5BC2_0000_43FF_04_5BE1_1 // f16_add_rz.tv line 16000 5BC2_43FF_5BE1_01 1.01111000010 x 2^7 + 1.01111111111 x 2^1 = 1.01111100001 x 2^7
+47FE_0000_3C01_04_487F_1 // f16_add_rz.tv line 16500 47FE_3C01_487F_01 1.01111111110 x 2^2 + 1.00000000001 x 2^0 = 1.00001111111 x 2^3
+6800_0000_13F1_04_6800_1 // f16_add_rz.tv line 17000 6800_13F1_6800_01 1.00000000000 x 2^11 + 1.01111110001 x 2^-11 = 1.00000000000 x 2^11
+78FB_0000_3400_04_78FB_1 // f16_add_rz.tv line 17500 78FB_3400_78FB_01 1.00011111011 x 2^15 + 1.00000000000 x 2^-2 = 1.00011111011 x 2^15
+6BFF_0000_07FE_04_6BFF_1 // f16_add_rz.tv line 18000 6BFF_07FE_6BFF_01 1.01111111111 x 2^11 + 1.01111111110 x 2^-14 = 1.01111111111 x 2^11
+6BFE_0000_13FE_04_6BFE_1 // f16_add_rz.tv line 18500 6BFE_13FE_6BFE_01 1.01111111110 x 2^11 + 1.01111111110 x 2^-11 = 1.01111111110 x 2^11
+382F_0000_FFFF_04_FFFF_0 // f16_add_rz.tv line 19000 382F_FFFF_FFFF_00 1.00000101111 x 2^-1 + NaN = NaN
+7800_0000_F801_04_D000_0 // f16_add_rz.tv line 19500 7800_F801_D000_00 1.00000000000 x 2^15 + -1.00000000001 x 2^15 = -1.00000000000 x 2^5
+7801_0000_4877_04_7801_1 // f16_add_rz.tv line 20000 7801_4877_7801_01 1.00000000001 x 2^15 + 1.00001110111 x 2^3 = 1.00000000001 x 2^15
+// Skipped denorm f16_add_rz.tv line 20500 0090_C400_C3FF_01 Denorm + -1.00000000000 x 2^2 = -1.01111111111 x 2^1
+7BFE_0000_BFFE_04_7BFD_1 // f16_add_rz.tv line 21000 7BFE_BFFE_7BFD_01 1.01111111110 x 2^15 + -1.01111111110 x 2^0 = 1.01111111101 x 2^15
+7C00_0000_4F08_04_7C00_0 // f16_add_rz.tv line 21500 7C00_4F08_7C00_00 INF + 1.01100001000 x 2^4 = INF
+BFFA_0000_B7FF_04_C0FC_1 // f16_add_rz.tv line 22000 BFFA_B7FF_C0FC_01 -1.01111111010 x 2^0 + -1.01111111111 x 2^-2 = -1.00011111100 x 2^1
+7FFF_0000_9001_04_7FFF_0 // f16_add_rz.tv line 22500 7FFF_9001_7FFF_00 NaN + -1.00000000001 x 2^-11 = NaN
+7FFE_0000_B82F_04_7FFE_0 // f16_add_rz.tv line 23000 7FFE_B82F_7FFE_00 NaN + -1.00000101111 x 2^-1 = NaN
+// Skipped denorm f16_add_rz.tv line 23500 2F68_8000_2F68_00 1.01101101000 x 2^-4 + -Denorm = 1.01101101000 x 2^-4
+// Skipped denorm f16_add_rz.tv line 24000 8001_7BFE_7BFD_01 -Denorm + 1.01111111110 x 2^15 = 1.01111111101 x 2^15
+// Skipped denorm f16_add_rz.tv line 24500 83FF_EB8E_EB8E_01 -Denorm + -1.01110001110 x 2^11 = -1.01110001110 x 2^11
+75FF_0000_47FF_04_75FF_1 // f16_add_rz.tv line 25000 75FF_47FF_75FF_01 1.00111111111 x 2^14 + 1.01111111111 x 2^2 = 1.00111111111 x 2^14
+8400_0000_4001_04_4000_1 // f16_add_rz.tv line 25500 8400_4001_4000_01 -1.00000000000 x 2^-14 + 1.00000000001 x 2^1 = 1.00000000000 x 2^1
+8401_0000_C3E7_04_C3E7_1 // f16_add_rz.tv line 26000 8401_C3E7_C3E7_01 -1.00000000001 x 2^-14 + -1.01111100111 x 2^1 = -1.01111100111 x 2^1
+CC00_0000_3800_04_CBC0_0 // f16_add_rz.tv line 26500 CC00_3800_CBC0_00 -1.00000000000 x 2^4 + 1.00000000000 x 2^-1 = -1.01111000000 x 2^3
+87FE_0000_13FE_04_12FE_1 // f16_add_rz.tv line 27000 87FE_13FE_12FE_01 -1.01111111110 x 2^-14 + 1.01111111110 x 2^-11 = 1.01011111110 x 2^-11
+9000_0000_7FF2_04_7FF2_0 // f16_add_rz.tv line 27500 9000_7FF2_7FF2_00 -1.00000000000 x 2^-11 + NaN = NaN
+// Skipped denorm f16_add_rz.tv line 28000 C082_03FF_C081_01 -1.00010000010 x 2^1 + Denorm = -1.00010000001 x 2^1
+9001_0000_FC01_04_FE01_0 // f16_add_rz.tv line 28500 9001_FC01_FE01_10 -1.00000000001 x 2^-11 + NaN = NaN
+93FF_0000_2DFF_04_2DEF_1 // f16_add_rz.tv line 29000 93FF_2DFF_2DEF_01 -1.01111111111 x 2^-11 + 1.00111111111 x 2^-4 = 1.00111101111 x 2^-4
+BE01_0000_E800_04_E800_1 // f16_add_rz.tv line 29500 BE01_E800_E800_01 -1.01000000001 x 2^0 + -1.00000000000 x 2^11 = -1.00000000000 x 2^11
+B400_0000_C3FE_04_C43F_0 // f16_add_rz.tv line 30000 B400_C3FE_C43F_00 -1.00000000000 x 2^-2 + -1.01111111110 x 2^1 = -1.00000111111 x 2^2
+B401_0000_2702_04_B321_1 // f16_add_rz.tv line 30500 B401_2702_B321_01 -1.00000000001 x 2^-2 + 1.01100000010 x 2^-6 = -1.01100100001 x 2^-3
+E09F_0000_BBFF_04_E0A0_1 // f16_add_rz.tv line 31000 E09F_BBFF_E0A0_01 -1.00010011111 x 2^9 + -1.01111111111 x 2^-1 = -1.00010100000 x 2^9
+B7FE_0000_B401_04_B9FF_1 // f16_add_rz.tv line 31500 B7FE_B401_B9FF_01 -1.01111111110 x 2^-2 + -1.00000000001 x 2^-2 = -1.00111111111 x 2^-1
+// Skipped denorm f16_add_rz.tv line 32000 B800_80BF_B800_01 -1.00000000000 x 2^-1 + -Denorm = -1.00000000000 x 2^-1
+6BBC_0000_8400_04_6BBB_1 // f16_add_rz.tv line 32500 6BBC_8400_6BBB_01 1.01110111100 x 2^11 + -1.00000000000 x 2^-14 = 1.01110111011 x 2^11
+BBFF_0000_7FFE_04_7FFE_0 // f16_add_rz.tv line 33000 BBFF_7FFE_7FFE_00 -1.01111111111 x 2^-1 + NaN = NaN
+BBFE_0000_09DF_04_BBFD_1 // f16_add_rz.tv line 33500 BBFE_09DF_BBFD_01 -1.01111111110 x 2^-1 + 1.00111011111 x 2^-13 = -1.01111111101 x 2^-1
+124E_0000_6BFF_04_6BFF_1 // f16_add_rz.tv line 34000 124E_6BFF_6BFF_01 1.01001001110 x 2^-11 + 1.01111111111 x 2^11 = 1.01111111111 x 2^11
+BC01_0000_4401_04_4201_1 // f16_add_rz.tv line 34500 BC01_4401_4201_01 -1.00000000001 x 2^0 + 1.00000000001 x 2^2 = 1.01000000001 x 2^1
+BFFF_0000_10BF_04_BFFE_1 // f16_add_rz.tv line 35000 BFFF_10BF_BFFE_01 -1.01111111111 x 2^0 + 1.00010111111 x 2^-11 = -1.01111111110 x 2^0
+48EF_0000_3C00_04_496F_0 // f16_add_rz.tv line 35500 48EF_3C00_496F_00 1.00011101111 x 2^3 + 1.00000000000 x 2^0 = 1.00101101111 x 2^3
+C000_0000_37FE_04_BE00_1 // f16_add_rz.tv line 36000 C000_37FE_BE00_01 -1.00000000000 x 2^1 + 1.01111111110 x 2^-2 = -1.01000000000 x 2^0
+// Skipped denorm f16_add_rz.tv line 36500 C001_021F_C000_01 -1.00000000001 x 2^1 + Denorm = -1.00000000000 x 2^1
+1180_0000_07FF_04_127F_1 // f16_add_rz.tv line 37000 1180_07FF_127F_01 1.00110000000 x 2^-11 + 1.01111111111 x 2^-14 = 1.01001111111 x 2^-11
+// Skipped denorm f16_add_rz.tv line 37500 C3FE_0001_C3FD_01 -1.01111111110 x 2^1 + Denorm = -1.01111111101 x 2^1
+// Skipped denorm f16_add_rz.tv line 38000 C3FE_00FF_C3FD_01 -1.01111111110 x 2^1 + Denorm = -1.01111111101 x 2^1
+1A7C_0000_F800_04_F7FF_1 // f16_add_rz.tv line 38500 1A7C_F800_F7FF_01 1.01001111100 x 2^-9 + -1.00000000000 x 2^15 = -1.01111111111 x 2^14
+C401_0000_C7FE_04_C9FF_1 // f16_add_rz.tv line 39000 C401_C7FE_C9FF_01 -1.00000000001 x 2^2 + -1.01111111110 x 2^2 = -1.00111111111 x 2^3
+C7FF_0000_C73F_04_CB9F_0 // f16_add_rz.tv line 39500 C7FF_C73F_CB9F_00 -1.01111111111 x 2^2 + -1.01100111111 x 2^2 = -1.01110011111 x 2^3
+3F10_0000_BFFF_04_B378_0 // f16_add_rz.tv line 40000 3F10_BFFF_B378_00 1.01100010000 x 2^0 + -1.01111111111 x 2^0 = -1.01101111000 x 2^-3
+E800_0000_B801_04_E800_1 // f16_add_rz.tv line 40500 E800_B801_E800_01 -1.00000000000 x 2^11 + -1.00000000001 x 2^-1 = -1.00000000000 x 2^11
+E801_0000_B387_04_E801_1 // f16_add_rz.tv line 41000 E801_B387_E801_01 -1.00000000001 x 2^11 + -1.01110000111 x 2^-3 = -1.00000000001 x 2^11
+CBE1_0000_9000_04_CBE1_1 // f16_add_rz.tv line 41500 CBE1_9000_CBE1_01 -1.01111100001 x 2^3 + -1.00000000000 x 2^-11 = -1.01111100001 x 2^3
+// Skipped denorm f16_add_rz.tv line 42000 EBFE_83FE_EBFE_01 -1.01111111110 x 2^11 + -Denorm = -1.01111111110 x 2^11
+F800_0000_3F00_04_F7FF_1 // f16_add_rz.tv line 42500 F800_3F00_F7FF_01 -1.00000000000 x 2^15 + 1.01100000000 x 2^0 = -1.01111111111 x 2^14
+CFBF_0000_7BFF_04_7BFE_1 // f16_add_rz.tv line 43000 CFBF_7BFF_7BFE_01 -1.01110111111 x 2^4 + 1.01111111111 x 2^15 = 1.01111111110 x 2^15
+FBFF_0000_6801_04_FBBE_1 // f16_add_rz.tv line 43500 FBFF_6801_FBBE_01 -1.01111111111 x 2^15 + 1.00000000001 x 2^11 = -1.01110111110 x 2^15
+FBFE_0000_11FF_04_FBFD_1 // f16_add_rz.tv line 44000 FBFE_11FF_FBFD_01 -1.01111111110 x 2^15 + 1.00111111111 x 2^-11 = -1.01111111101 x 2^15
+3CD8_0000_4000_04_426C_0 // f16_add_rz.tv line 44500 3CD8_4000_426C_00 1.00011011000 x 2^0 + 1.00000000000 x 2^1 = 1.01001101100 x 2^1
+FC01_0000_3BFE_04_FE01_0 // f16_add_rz.tv line 45000 FC01_3BFE_FE01_10 NaN + 1.01111111110 x 2^-1 = NaN
+FFFF_0000_44F7_04_FFFF_0 // f16_add_rz.tv line 45500 FFFF_44F7_FFFF_00 NaN + 1.00011110111 x 2^2 = NaN
+CB78_0000_13FF_04_CB77_1 // f16_add_rz.tv line 46000 CB78_13FF_CB77_01 -1.01101111000 x 2^3 + 1.01111111111 x 2^-11 = -1.01101110111 x 2^3
+
+////////// Testcases from f16_add_rd.tv of type add rounding mode 2
+0000_0000_FBFF_24_FBFF_0 // f16_add_rd.tv line 498 0000_FBFF_FBFF_00 0 + -1.01111111111 x 2^15 = -1.01111111111 x 2^15
+// Skipped denorm f16_add_rd.tv line 998 0001_448C_448C_01 Denorm + 1.00010001100 x 2^2 = 1.00010001100 x 2^2
+C3A0_0000_C401_24_C7D1_0 // f16_add_rd.tv line 1498 C3A0_C401_C7D1_00 -1.01110100000 x 2^1 + -1.00000000001 x 2^2 = -1.01111010001 x 2^2
+// Skipped denorm f16_add_rd.tv line 1998 03FE_C000_C000_01 Denorm + -1.00000000000 x 2^1 = -1.00000000000 x 2^1
+0400_0000_68A5_24_68A5_1 // f16_add_rd.tv line 2498 0400_68A5_68A5_01 1.00000000000 x 2^-14 + 1.00010100101 x 2^11 = 1.00010100101 x 2^11
+// Skipped denorm f16_add_rd.tv line 2998 02FD_B7FE_B7FE_01 Denorm + -1.01111111110 x 2^-2 = -1.01111111110 x 2^-2
+07FF_0000_93FF_24_9300_1 // f16_add_rd.tv line 3498 07FF_93FF_9300_01 1.01111111111 x 2^-14 + -1.01111111111 x 2^-11 = -1.01100000000 x 2^-11
+07FE_0000_33CF_24_33CF_1 // f16_add_rd.tv line 3998 07FE_33CF_33CF_01 1.01111111110 x 2^-14 + 1.01111001111 x 2^-3 = 1.01111001111 x 2^-3
+// Skipped denorm f16_add_rd.tv line 4498 EAFB_8001_EAFC_01 -1.01011111011 x 2^11 + -Denorm = -1.01011111100 x 2^11
+1001_0000_7C00_24_7C00_0 // f16_add_rd.tv line 4998 1001_7C00_7C00_00 1.00000000001 x 2^-11 + INF = INF
+13FF_0000_32E7_24_32EE_1 // f16_add_rd.tv line 5498 13FF_32E7_32EE_01 1.01111111111 x 2^-11 + 1.01011100111 x 2^-3 = 1.01011101110 x 2^-3
+BC1F_0000_47FE_24_46F6_1 // f16_add_rd.tv line 5998 BC1F_47FE_46F6_01 -1.00000011111 x 2^0 + 1.01111111110 x 2^2 = 1.01011110110 x 2^2
+3400_0000_43FF_24_443F_1 // f16_add_rd.tv line 6498 3400_43FF_443F_01 1.00000000000 x 2^-2 + 1.01111111111 x 2^1 = 1.00000111111 x 2^2
+3401_0000_9AE8_24_33E6_1 // f16_add_rd.tv line 6998 3401_9AE8_33E6_01 1.00000000001 x 2^-2 + -1.01011101000 x 2^-9 = 1.01111100110 x 2^-3
+7703_0000_3801_24_7703_1 // f16_add_rd.tv line 7498 7703_3801_7703_01 1.01100000011 x 2^14 + 1.00000000001 x 2^-1 = 1.01100000011 x 2^14
+37FE_0000_3400_24_39FF_0 // f16_add_rd.tv line 7998 37FE_3400_39FF_00 1.01111111110 x 2^-2 + 1.00000000000 x 2^-2 = 1.00111111111 x 2^-1
+3800_0000_2EFE_24_38DF_1 // f16_add_rd.tv line 8498 3800_2EFE_38DF_01 1.00000000000 x 2^-1 + 1.01011111110 x 2^-4 = 1.00011011111 x 2^-1
+// Skipped denorm f16_add_rd.tv line 8998 B0FC_03FE_B0FC_01 -1.00011111100 x 2^-3 + Denorm = -1.00011111100 x 2^-3
+3801_0000_FFFF_24_FFFF_0 // f16_add_rd.tv line 9498 3801_FFFF_FFFF_00 1.00000000001 x 2^-1 + NaN = NaN
+3BFF_0000_AB04_24_3B8E_1 // f16_add_rd.tv line 9998 3BFF_AB04_3B8E_01 1.01111111111 x 2^-1 + -1.01100000100 x 2^-5 = 1.01110001110 x 2^-1
+AD11_0000_E801_24_E802_1 // f16_add_rd.tv line 10498 AD11_E801_E802_01 -1.00100010001 x 2^-4 + -1.00000000001 x 2^11 = -1.00000000010 x 2^11
+3C00_0000_C400_24_C200_0 // f16_add_rd.tv line 10998 3C00_C400_C200_00 1.00000000000 x 2^0 + -1.00000000000 x 2^2 = -1.01000000000 x 2^1
+3C01_0000_0BFD_24_3C01_1 // f16_add_rd.tv line 11498 3C01_0BFD_3C01_01 1.00000000001 x 2^0 + 1.01111111101 x 2^-13 = 1.00000000001 x 2^0
+4FDE_0000_BBFE_24_4F9E_1 // f16_add_rd.tv line 11998 4FDE_BBFE_4F9E_01 1.01111011110 x 2^4 + -1.01111111110 x 2^-1 = 1.01110011110 x 2^4
+3FFE_0000_B7FF_24_3DFE_1 // f16_add_rd.tv line 12498 3FFE_B7FF_3DFE_01 1.01111111110 x 2^0 + -1.01111111111 x 2^-2 = 1.00111111110 x 2^0
+4000_0000_1008_24_4000_1 // f16_add_rd.tv line 12998 4000_1008_4000_01 1.00000000000 x 2^1 + 1.00000001000 x 2^-11 = 1.00000000000 x 2^1
+C64C_0000_8401_24_C64D_1 // f16_add_rd.tv line 13498 C64C_8401_C64D_01 -1.01001001100 x 2^2 + -1.00000000001 x 2^-14 = -1.01001001101 x 2^2
+// Skipped denorm f16_add_rd.tv line 13998 43FF_8000_43FF_00 1.01111111111 x 2^1 + -Denorm = 1.01111111111 x 2^1
+43FE_0000_2E03_24_4417_1 // f16_add_rd.tv line 14498 43FE_2E03_4417_01 1.01111111110 x 2^1 + 1.01000000011 x 2^-4 = 1.00000010111 x 2^2
+265F_0000_6BFE_24_6BFE_1 // f16_add_rd.tv line 14998 265F_6BFE_6BFE_01 1.01001011111 x 2^-6 + 1.01111111110 x 2^11 = 1.01111111110 x 2^11
+4401_0000_47FF_24_4A00_0 // f16_add_rd.tv line 15498 4401_47FF_4A00_00 1.00000000001 x 2^2 + 1.01111111111 x 2^2 = 1.01000000000 x 2^3
+47FF_0000_F8C0_24_F8C0_1 // f16_add_rd.tv line 15998 47FF_F8C0_F8C0_01 1.01111111111 x 2^2 + -1.00011000000 x 2^15 = -1.00011000000 x 2^15
+23CF_0000_3C01_24_3C10_1 // f16_add_rd.tv line 16498 23CF_3C01_3C10_01 1.01111001111 x 2^-7 + 1.00000000001 x 2^0 = 1.00000010000 x 2^0
+6800_0000_3800_24_6800_1 // f16_add_rd.tv line 16998 6800_3800_6800_01 1.00000000000 x 2^11 + 1.00000000000 x 2^-1 = 1.00000000000 x 2^11
+6801_0000_3B7A_24_6801_1 // f16_add_rd.tv line 17498 6801_3B7A_6801_01 1.00000000001 x 2^11 + 1.01101111010 x 2^-1 = 1.00000000001 x 2^11
+90C9_0000_07FE_24_8F93_1 // f16_add_rd.tv line 17998 90C9_07FE_8F93_01 -1.00011001001 x 2^-11 + 1.01111111110 x 2^-14 = -1.01110010011 x 2^-12
+// Skipped denorm f16_add_rd.tv line 18498 6BFE_03FF_6BFE_01 1.01111111110 x 2^11 + Denorm = 1.01111111110 x 2^11
+6BFE_0000_4C21_24_6C03_1 // f16_add_rd.tv line 18998 6BFE_4C21_6C03_01 1.01111111110 x 2^11 + 1.00000100001 x 2^4 = 1.00000000011 x 2^12
+BFDC_0000_F801_24_F802_1 // f16_add_rd.tv line 19498 BFDC_F801_F802_01 -1.01111011100 x 2^0 + -1.00000000001 x 2^15 = -1.00000000010 x 2^15
+7801_0000_E800_24_7782_0 // f16_add_rd.tv line 19998 7801_E800_7782_00 1.00000000001 x 2^15 + -1.00000000000 x 2^11 = 1.01110000010 x 2^14
+7BFF_0000_5CFB_24_7BFF_5 // f16_add_rd.tv line 20498 7BFF_5CFB_7BFF_05 1.01111111111 x 2^15 + 1.00011111011 x 2^8 = 1.01111111111 x 2^15
+050F_0000_BFFE_24_BFFE_1 // f16_add_rd.tv line 20998 050F_BFFE_BFFE_01 1.00100001111 x 2^-14 + -1.01111111110 x 2^0 = -1.01111111110 x 2^0
+7C00_0000_BBFF_24_7C00_0 // f16_add_rd.tv line 21498 7C00_BBFF_7C00_00 INF + -1.01111111111 x 2^-1 = INF
+7C01_0000_EBBE_24_7E01_0 // f16_add_rd.tv line 21998 7C01_EBBE_7E01_10 NaN + -1.01110111110 x 2^11 = NaN
+C3C3_0000_9001_24_C3C4_1 // f16_add_rd.tv line 22498 C3C3_9001_C3C4_01 -1.01111000011 x 2^1 + -1.00000000001 x 2^-11 = -1.01111000100 x 2^1
+7FFE_0000_8400_24_7FFE_0 // f16_add_rd.tv line 22998 7FFE_8400_7FFE_00 NaN + -1.00000000000 x 2^-14 = NaN
+// Skipped denorm f16_add_rd.tv line 23498 8000_C475_C475_00 -Denorm + -1.00001110101 x 2^2 = -1.00001110101 x 2^2
+C80C_0000_7BFE_24_7BFD_1 // f16_add_rd.tv line 23998 C80C_7BFE_7BFD_01 -1.00000001100 x 2^3 + 1.01111111110 x 2^15 = 1.01111111101 x 2^15
+// Skipped denorm f16_add_rd.tv line 24498 83FF_6BFF_6BFE_01 -Denorm + 1.01111111111 x 2^11 = 1.01111111110 x 2^11
+// Skipped denorm f16_add_rd.tv line 24998 83FE_BA31_BA32_01 -Denorm + -1.01000110001 x 2^-1 = -1.01000110010 x 2^-1
+4A3F_0000_4001_24_4B3F_1 // f16_add_rd.tv line 25498 4A3F_4001_4B3F_01 1.01000111111 x 2^3 + 1.00000000001 x 2^1 = 1.01100111111 x 2^3
+8401_0000_3C00_24_3BFF_1 // f16_add_rd.tv line 25998 8401_3C00_3BFF_01 -1.00000000001 x 2^-14 + 1.00000000000 x 2^0 = 1.01111111111 x 2^-1
+87FF_0000_4827_24_4826_1 // f16_add_rd.tv line 26498 87FF_4827_4826_01 -1.01111111111 x 2^-14 + 1.00000100111 x 2^3 = 1.00000100110 x 2^3
+37EB_0000_13FE_24_37EE_1 // f16_add_rd.tv line 26998 37EB_13FE_37EE_01 1.01111101011 x 2^-2 + 1.01111111110 x 2^-11 = 1.01111101110 x 2^-2
+9000_0000_07FF_24_8E01_1 // f16_add_rd.tv line 27498 9000_07FF_8E01_01 -1.00000000000 x 2^-11 + 1.01111111111 x 2^-14 = -1.01000000001 x 2^-12
+9001_0000_A23E_24_A27F_1 // f16_add_rd.tv line 27998 9001_A23E_A27F_01 -1.00000000001 x 2^-11 + -1.01000111110 x 2^-7 = -1.01001111111 x 2^-7
+1357_0000_FC01_24_FE01_0 // f16_add_rd.tv line 28498 1357_FC01_FE01_10 1.01101010111 x 2^-11 + NaN = NaN
+93FF_0000_F800_24_F801_1 // f16_add_rd.tv line 28998 93FF_F800_F801_01 -1.01111111111 x 2^-11 + -1.00000000000 x 2^15 = -1.00000000001 x 2^15
+93FE_0000_633F_24_633E_1 // f16_add_rd.tv line 29498 93FE_633F_633E_01 -1.01111111110 x 2^-11 + 1.01100111111 x 2^9 = 1.01100111110 x 2^9
+8B6F_0000_C3FE_24_C3FF_1 // f16_add_rd.tv line 29998 8B6F_C3FE_C3FF_01 -1.01101101111 x 2^-13 + -1.01111111110 x 2^1 = -1.01111111111 x 2^1
+B401_0000_BFFF_24_C080_1 // f16_add_rd.tv line 30498 B401_BFFF_C080_01 -1.00000000001 x 2^-2 + -1.01111111111 x 2^0 = -1.00010000000 x 2^1
+B7FF_0000_BCC0_24_BEC0_1 // f16_add_rd.tv line 30998 B7FF_BCC0_BEC0_01 -1.01111111111 x 2^-2 + -1.00011000000 x 2^0 = -1.01011000000 x 2^0
+4FF9_0000_B401_24_4FE8_1 // f16_add_rd.tv line 31498 4FF9_B401_4FE8_01 1.01111111001 x 2^4 + -1.00000000001 x 2^-2 = 1.01111101000 x 2^4
+B800_0000_9000_24_B801_0 // f16_add_rd.tv line 31998 B800_9000_B801_00 -1.00000000000 x 2^-1 + -1.00000000000 x 2^-11 = -1.00000000001 x 2^-1
+B801_0000_0B3B_24_B801_1 // f16_add_rd.tv line 32498 B801_0B3B_B801_01 -1.00000000001 x 2^-1 + 1.01100111011 x 2^-13 = -1.00000000001 x 2^-1
+B4C0_0000_7FFE_24_7FFE_0 // f16_add_rd.tv line 32998 B4C0_7FFE_7FFE_00 -1.00011000000 x 2^-2 + NaN = NaN
+BBFE_0000_7BFF_24_7BFE_1 // f16_add_rd.tv line 33498 BBFE_7BFF_7BFE_01 -1.01111111110 x 2^-1 + 1.01111111111 x 2^15 = 1.01111111110 x 2^15
+BC00_0000_FE3F_24_FE3F_0 // f16_add_rd.tv line 33998 BC00_FE3F_FE3F_00 -1.00000000000 x 2^0 + NaN = NaN
+6BFF_0000_4401_24_6C00_1 // f16_add_rd.tv line 34498 6BFF_4401_6C00_01 1.01111111111 x 2^11 + 1.00000000001 x 2^2 = 1.00000000000 x 2^12
+BFFF_0000_4000_24_1400_0 // f16_add_rd.tv line 34998 BFFF_4000_1400_00 -1.01111111111 x 2^0 + 1.00000000000 x 2^1 = 1.00000000000 x 2^-10
+BFFE_0000_040E_24_BFFE_1 // f16_add_rd.tv line 35498 BFFE_040E_BFFE_01 -1.01111111110 x 2^0 + 1.00000001110 x 2^-14 = -1.01111111110 x 2^0
+C81F_0000_37FE_24_C7BF_1 // f16_add_rd.tv line 35998 C81F_37FE_C7BF_01 -1.00000011111 x 2^3 + 1.01111111110 x 2^-2 = -1.01110111111 x 2^2
+C001_0000_13FF_24_C001_1 // f16_add_rd.tv line 36498 C001_13FF_C001_01 -1.00000000001 x 2^1 + 1.01111111111 x 2^-11 = -1.00000000001 x 2^1
+C3FF_0000_C11E_24_C68F_1 // f16_add_rd.tv line 36998 C3FF_C11E_C68F_01 -1.01111111111 x 2^1 + -1.00100011110 x 2^1 = -1.01010001111 x 2^2
+// Skipped denorm f16_add_rd.tv line 37498 D527_0001_D527_01 -1.00100100111 x 2^6 + Denorm = -1.00100100111 x 2^6
+C3FE_0000_FC00_24_FC00_0 // f16_add_rd.tv line 37998 C3FE_FC00_FC00_00 -1.01111111110 x 2^1 + -INF = -INF
+C400_0000_893F_24_C401_1 // f16_add_rd.tv line 38498 C400_893F_C401_01 -1.00000000000 x 2^2 + -1.00100111111 x 2^-13 = -1.00000000001 x 2^2
+0881_0000_C7FE_24_C7FE_1 // f16_add_rd.tv line 38998 0881_C7FE_C7FE_01 1.00010000001 x 2^-13 + -1.01111111110 x 2^2 = -1.01111111110 x 2^2
+C7FF_0000_C3FF_24_CA00_1 // f16_add_rd.tv line 39498 C7FF_C3FF_CA00_01 -1.01111111111 x 2^2 + -1.01111111111 x 2^1 = -1.01000000000 x 2^3
+C7FE_0000_8A7F_24_C7FF_1 // f16_add_rd.tv line 39998 C7FE_8A7F_C7FF_01 -1.01111111110 x 2^2 + -1.01001111111 x 2^-13 = -1.01111111111 x 2^2
+7BD8_0000_B801_24_7BD7_1 // f16_add_rd.tv line 40498 7BD8_B801_7BD7_01 1.01111011000 x 2^15 + -1.00000000001 x 2^-1 = 1.01111010111 x 2^15
+E801_0000_B400_24_E802_1 // f16_add_rd.tv line 40998 E801_B400_E802_01 -1.00000000001 x 2^11 + -1.00000000000 x 2^-2 = -1.00000000010 x 2^11
+EBFF_0000_BDFF_24_EC00_1 // f16_add_rd.tv line 41498 EBFF_BDFF_EC00_01 -1.01111111111 x 2^11 + -1.00111111111 x 2^0 = -1.00000000000 x 2^12
+// Skipped denorm f16_add_rd.tv line 41998 D4FF_83FE_D500_01 -1.00011111111 x 2^6 + -Denorm = -1.00100000000 x 2^6
+F800_0000_7FFF_24_7FFF_0 // f16_add_rd.tv line 42498 F800_7FFF_7FFF_00 -1.00000000000 x 2^15 + NaN = NaN
+F801_0000_7BC8_24_778E_0 // f16_add_rd.tv line 42998 F801_7BC8_778E_00 -1.00000000001 x 2^15 + 1.01111001000 x 2^15 = 1.01110001110 x 2^14
+A020_0000_6801_24_6800_1 // f16_add_rd.tv line 43498 A020_6801_6800_01 -1.00000100000 x 2^-7 + 1.00000000001 x 2^11 = 1.00000000000 x 2^11
+FBFE_0000_4400_24_FBFE_1 // f16_add_rd.tv line 43998 FBFE_4400_FBFE_01 -1.01111111110 x 2^15 + 1.00000000000 x 2^2 = -1.01111111110 x 2^15
+FC00_0000_07C6_24_FC00_0 // f16_add_rd.tv line 44498 FC00_07C6_FC00_00 -INF + 1.01111000110 x 2^-14 = -INF
+BA33_0000_3BFE_24_332C_0 // f16_add_rd.tv line 44998 BA33_3BFE_332C_00 -1.01000110011 x 2^-1 + 1.01111111110 x 2^-1 = 1.01100101100 x 2^-3
+FFFF_0000_37FF_24_FFFF_0 // f16_add_rd.tv line 45498 FFFF_37FF_FFFF_00 NaN + 1.01111111111 x 2^-2 = NaN
+FFFE_0000_CBFF_24_FFFE_0 // f16_add_rd.tv line 45998 FFFE_CBFF_FFFE_00 NaN + -1.01111111111 x 2^3 = NaN
+
+////////// Testcases from f16_add_ru.tv of type add rounding mode 3
+3C2F_0000_63C0_34_63C3_1 // f16_add_ru.tv line 497 3C2F_63C0_63C3_01 1.00000101111 x 2^0 + 1.01111000000 x 2^9 = 1.01111000011 x 2^9
+F843_0000_4F90_34_F842_1 // f16_add_ru.tv line 997 F843_4F90_F842_01 -1.00001000011 x 2^15 + 1.01110010000 x 2^4 = -1.00001000010 x 2^15
+4B6F_0000_3810_34_4BB0_0 // f16_add_ru.tv line 1497 4B6F_3810_4BB0_00 1.01101101111 x 2^3 + 1.00000010000 x 2^-1 = 1.01110110000 x 2^3
+BBC0_0000_7FF3_34_7FF3_0 // f16_add_ru.tv line 1997 BBC0_7FF3_7FF3_00 -1.01111000000 x 2^-1 + NaN = NaN
+// Skipped denorm f16_add_ru.tv line 2497 80BF_FAE3_FAE3_01 -Denorm + -1.01011100011 x 2^15 = -1.01011100011 x 2^15
+9F24_0000_B7D3_34_B7EF_1 // f16_add_ru.tv line 2997 9F24_B7D3_B7EF_01 -1.01100100100 x 2^-8 + -1.01111010011 x 2^-2 = -1.01111101111 x 2^-2
+B564_0000_4A3C_34_4A11_1 // f16_add_ru.tv line 3497 B564_4A3C_4A11_01 -1.00101100100 x 2^-2 + 1.01000111100 x 2^3 = 1.01000010001 x 2^3
+D827_0000_AFFF_34_D827_1 // f16_add_ru.tv line 3997 D827_AFFF_D827_01 -1.00000100111 x 2^7 + -1.01111111111 x 2^-4 = -1.00000100111 x 2^7
+B740_0000_CFF0_34_D006_1 // f16_add_ru.tv line 4497 B740_CFF0_D006_01 -1.01101000000 x 2^-2 + -1.01111110000 x 2^4 = -1.00000000110 x 2^5
+// Skipped denorm f16_add_ru.tv line 4997 80BF_AC1B_AC1B_01 -Denorm + -1.00000011011 x 2^-4 = -1.00000011011 x 2^-4
+76A1_0000_3409_34_76A2_1 // f16_add_ru.tv line 5497 76A1_3409_76A2_01 1.01010100001 x 2^14 + 1.00000001001 x 2^-2 = 1.01010100010 x 2^14
+4B04_0000_C466_34_48D1_0 // f16_add_ru.tv line 5997 4B04_C466_48D1_00 1.01100000100 x 2^3 + -1.00001100110 x 2^2 = 1.00011010001 x 2^3
+8AFF_0000_24BE_34_24B1_1 // f16_add_ru.tv line 6497 8AFF_24BE_24B1_01 -1.01011111111 x 2^-13 + 1.00010111110 x 2^-6 = 1.00010110001 x 2^-6
+7CCC_0000_CADE_34_7ECC_0 // f16_add_ru.tv line 6997 7CCC_CADE_7ECC_10 NaN + -1.01011011110 x 2^3 = NaN
+477F_0000_47DD_34_4BAE_0 // f16_add_ru.tv line 7497 477F_47DD_4BAE_00 1.01101111111 x 2^2 + 1.01111011101 x 2^2 = 1.01110101110 x 2^3
+539E_0000_B80E_34_538E_1 // f16_add_ru.tv line 7997 539E_B80E_538E_01 1.01110011110 x 2^5 + -1.00000001110 x 2^-1 = 1.01110001110 x 2^5
+0BAE_0000_B1F3_34_B1F1_1 // f16_add_ru.tv line 8497 0BAE_B1F3_B1F1_01 1.01110101110 x 2^-13 + -1.00111110011 x 2^-3 = -1.00111110001 x 2^-3
+582F_0000_7FDA_34_7FDA_0 // f16_add_ru.tv line 8997 582F_7FDA_7FDA_00 1.00000101111 x 2^7 + NaN = NaN
+CC04_0000_997F_34_CC04_1 // f16_add_ru.tv line 9497 CC04_997F_CC04_01 -1.00000000100 x 2^4 + -1.00101111111 x 2^-9 = -1.00000000100 x 2^4
+6BBF_0000_8C1E_34_6BBF_1 // f16_add_ru.tv line 9997 6BBF_8C1E_6BBF_01 1.01110111111 x 2^11 + -1.00000011110 x 2^-12 = 1.01110111111 x 2^11
+BF1D_0000_4800_34_4639_1 // f16_add_ru.tv line 10497 BF1D_4800_4639_01 -1.01100011101 x 2^0 + 1.00000000000 x 2^3 = 1.01000111001 x 2^2
+1A9C_0000_0B02_34_1B0D_1 // f16_add_ru.tv line 10997 1A9C_0B02_1B0D_01 1.01010011100 x 2^-9 + 1.01100000010 x 2^-13 = 1.01100001101 x 2^-9
+DB80_0000_CCFF_34_DC0F_1 // f16_add_ru.tv line 11497 DB80_CCFF_DC0F_01 -1.01110000000 x 2^7 + -1.00011111111 x 2^4 = -1.00000001111 x 2^8
+FAFE_0000_7CE0_34_7EE0_0 // f16_add_ru.tv line 11997 FAFE_7CE0_7EE0_10 -1.01011111110 x 2^15 + NaN = NaN
+2FFF_0000_43EF_34_4418_1 // f16_add_ru.tv line 12497 2FFF_43EF_4418_01 1.01111111111 x 2^-4 + 1.01111101111 x 2^1 = 1.00000011000 x 2^2
+C602_0000_D33F_34_D3FF_1 // f16_add_ru.tv line 12997 C602_D33F_D3FF_01 -1.01000000010 x 2^2 + -1.01100111111 x 2^5 = -1.01111111111 x 2^5
+C7BA_0000_BC08_34_C85E_0 // f16_add_ru.tv line 13497 C7BA_BC08_C85E_00 -1.01110111010 x 2^2 + -1.00000001000 x 2^0 = -1.00001011110 x 2^3
+4CE0_0000_93DF_34_4CE0_1 // f16_add_ru.tv line 13997 4CE0_93DF_4CE0_01 1.00011100000 x 2^4 + -1.01111011111 x 2^-11 = 1.00011100000 x 2^4
+3929_0000_429E_34_43E9_1 // f16_add_ru.tv line 14497 3929_429E_43E9_01 1.00100101001 x 2^-1 + 1.01010011110 x 2^1 = 1.01111101001 x 2^1
+5CFC_0000_EBBF_34_EB1F_1 // f16_add_ru.tv line 14997 5CFC_EBBF_EB1F_01 1.00011111100 x 2^8 + -1.01110111111 x 2^11 = -1.01100011111 x 2^11
+C7F8_0000_EFF4_34_EFF5_1 // f16_add_ru.tv line 15497 C7F8_EFF4_EFF5_01 -1.01111111000 x 2^2 + -1.01111110100 x 2^12 = -1.01111110101 x 2^12
+3BC7_0000_BF6C_34_BB11_0 // f16_add_ru.tv line 15997 3BC7_BF6C_BB11_00 1.01111000111 x 2^-1 + -1.01101101100 x 2^0 = -1.01100010001 x 2^-1
+// Skipped denorm f16_add_ru.tv line 16497 8100_920C_922C_00 -Denorm + -1.01000001100 x 2^-11 = -1.01000101100 x 2^-11
+6827_0000_B1FB_34_6827_1 // f16_add_ru.tv line 16997 6827_B1FB_6827_01 1.00000100111 x 2^11 + -1.00111111011 x 2^-3 = 1.00000100111 x 2^11
+// Skipped denorm f16_add_ru.tv line 17497 C3FE_01FC_C3FD_01 -1.01111111110 x 2^1 + Denorm = -1.01111111101 x 2^1
+B903_0000_CBFC_34_CC26_1 // f16_add_ru.tv line 17997 B903_CBFC_CC26_01 -1.00100000011 x 2^-1 + -1.01111111100 x 2^3 = -1.00000100110 x 2^4
+F77B_0000_3640_34_F77A_1 // f16_add_ru.tv line 18497 F77B_3640_F77A_01 -1.01101111011 x 2^14 + 1.01001000000 x 2^-2 = -1.01101111010 x 2^14
+4FBF_0000_AFF0_34_4FB8_1 // f16_add_ru.tv line 18997 4FBF_AFF0_4FB8_01 1.01110111111 x 2^4 + -1.01111110000 x 2^-4 = 1.01110111000 x 2^4
+793D_0000_BFE0_34_793D_1 // f16_add_ru.tv line 19497 793D_BFE0_793D_01 1.00100111101 x 2^15 + -1.01111100000 x 2^0 = 1.00100111101 x 2^15
+B440_0000_58FE_34_58FC_1 // f16_add_ru.tv line 19997 B440_58FE_58FC_01 -1.00001000000 x 2^-2 + 1.00011111110 x 2^7 = 1.00011111100 x 2^7
+EB76_0000_B37C_34_EB76_1 // f16_add_ru.tv line 20497 EB76_B37C_EB76_01 -1.01101110110 x 2^11 + -1.01101111100 x 2^-3 = -1.01101110110 x 2^11
+887B_0000_34C7_34_34C7_1 // f16_add_ru.tv line 20997 887B_34C7_34C7_01 -1.00001111011 x 2^-13 + 1.00011000111 x 2^-2 = 1.00011000111 x 2^-2
+BB34_0000_BC90_34_C015_0 // f16_add_ru.tv line 21497 BB34_BC90_C015_00 -1.01100110100 x 2^-1 + -1.00010010000 x 2^0 = -1.00000010101 x 2^1
+4003_0000_2FFB_34_4043_1 // f16_add_ru.tv line 21997 4003_2FFB_4043_01 1.00000000011 x 2^1 + 1.01111111011 x 2^-4 = 1.00001000011 x 2^1
+A524_0000_4B03_34_4B01_1 // f16_add_ru.tv line 22497 A524_4B03_4B01_01 -1.00100100100 x 2^-6 + 1.01100000011 x 2^3 = 1.01100000001 x 2^3
+EA2F_0000_E40C_34_EC1A_1 // f16_add_ru.tv line 22997 EA2F_E40C_EC1A_01 -1.01000101111 x 2^11 + -1.00000001100 x 2^10 = -1.00000011010 x 2^12
+BEB4_0000_481F_34_4691_0 // f16_add_ru.tv line 23497 BEB4_481F_4691_00 -1.01010110100 x 2^0 + 1.00000011111 x 2^3 = 1.01010010001 x 2^2
+36F6_0000_4FF3_34_5008_1 // f16_add_ru.tv line 23997 36F6_4FF3_5008_01 1.01011110110 x 2^-2 + 1.01111110011 x 2^4 = 1.00000001000 x 2^5
+9F1F_0000_B478_34_B494_1 // f16_add_ru.tv line 24497 9F1F_B478_B494_01 -1.01100011111 x 2^-8 + -1.00001111000 x 2^-2 = -1.00010010100 x 2^-2
+1C0A_0000_343F_34_3450_1 // f16_add_ru.tv line 24997 1C0A_343F_3450_01 1.00000001010 x 2^-8 + 1.00000111111 x 2^-2 = 1.00001010000 x 2^-2
+AF61_0000_C7C0_34_C7DD_1 // f16_add_ru.tv line 25497 AF61_C7C0_C7DD_01 -1.01101100001 x 2^-4 + -1.01111000000 x 2^2 = -1.01111011101 x 2^2
+D07E_0000_103C_34_D07D_1 // f16_add_ru.tv line 25997 D07E_103C_D07D_01 -1.00001111110 x 2^5 + 1.00000111100 x 2^-11 = -1.00001111101 x 2^5
+9060_0000_FF78_34_FF78_0 // f16_add_ru.tv line 26497 9060_FF78_FF78_00 -1.00001100000 x 2^-11 + NaN = NaN
+B620_0000_C003_34_C0C7_0 // f16_add_ru.tv line 26997 B620_C003_C0C7_00 -1.01000100000 x 2^-2 + -1.00000000011 x 2^1 = -1.00011000111 x 2^1
+A82F_0000_8A02_34_A835_1 // f16_add_ru.tv line 27497 A82F_8A02_A835_01 -1.00000101111 x 2^-5 + -1.01000000010 x 2^-13 = -1.00000110101 x 2^-5
+437A_0000_A415_34_4372_1 // f16_add_ru.tv line 27997 437A_A415_4372_01 1.01101111010 x 2^1 + -1.00000010101 x 2^-6 = 1.01101110010 x 2^1
+2FD7_0000_BD4F_34_BCD1_1 // f16_add_ru.tv line 28497 2FD7_BD4F_BCD1_01 1.01111010111 x 2^-4 + -1.00101001111 x 2^0 = -1.00011010001 x 2^0
+7C3A_0000_B071_34_7E3A_0 // f16_add_ru.tv line 28997 7C3A_B071_7E3A_10 NaN + -1.00001110001 x 2^-3 = NaN
+FC01_0000_BBA2_34_FE01_0 // f16_add_ru.tv line 29497 FC01_BBA2_FE01_10 NaN + -1.01110100010 x 2^-1 = NaN
+7BF3_0000_4804_34_7BF4_1 // f16_add_ru.tv line 29997 7BF3_4804_7BF4_01 1.01111110011 x 2^15 + 1.00000000100 x 2^3 = 1.01111110100 x 2^15
+3907_0000_07BF_34_3908_1 // f16_add_ru.tv line 30497 3907_07BF_3908_01 1.00100000111 x 2^-1 + 1.01110111111 x 2^-14 = 1.00100001000 x 2^-1
+3FBE_0000_53BF_34_53FD_1 // f16_add_ru.tv line 30997 3FBE_53BF_53FD_01 1.01110111110 x 2^0 + 1.01110111111 x 2^5 = 1.01111111101 x 2^5
+// Skipped denorm f16_add_ru.tv line 31497 80C0_3C02_3C02_01 -Denorm + 1.00000000010 x 2^0 = 1.00000000010 x 2^0
+BC1E_0000_840E_34_BC1E_1 // f16_add_ru.tv line 31997 BC1E_840E_BC1E_01 -1.00000011110 x 2^0 + -1.00000001110 x 2^-14 = -1.00000011110 x 2^0
+// Skipped denorm f16_add_ru.tv line 32497 6842_03B6_6843_01 1.00001000010 x 2^11 + Denorm = 1.00001000011 x 2^11
+86C8_0000_3818_34_3818_1 // f16_add_ru.tv line 32997 86C8_3818_3818_01 -1.01011001000 x 2^-14 + 1.00000011000 x 2^-1 = 1.00000011000 x 2^-1
+4842_0000_CB79_34_C66E_0 // f16_add_ru.tv line 33497 4842_CB79_C66E_00 1.00001000010 x 2^3 + -1.01101111001 x 2^3 = -1.01001101110 x 2^2
+13E8_0000_DC87_34_DC86_1 // f16_add_ru.tv line 33997 13E8_DC87_DC86_01 1.01111101000 x 2^-11 + -1.00010000111 x 2^8 = -1.00010000110 x 2^8
+B8F0_0000_EC3B_34_EC3B_1 // f16_add_ru.tv line 34497 B8F0_EC3B_EC3B_01 -1.00011110000 x 2^-1 + -1.00000111011 x 2^12 = -1.00000111011 x 2^12
+C5C0_0000_8B1F_34_C5C0_1 // f16_add_ru.tv line 34997 C5C0_8B1F_C5C0_01 -1.00111000000 x 2^2 + -1.01100011111 x 2^-13 = -1.00111000000 x 2^2
+C901_0000_B0C9_34_C914_1 // f16_add_ru.tv line 35497 C901_B0C9_C914_01 -1.00100000001 x 2^3 + -1.00011001001 x 2^-3 = -1.00100010100 x 2^3
+340F_0000_A5FE_34_335F_1 // f16_add_ru.tv line 35997 340F_A5FE_335F_01 1.00000001111 x 2^-2 + -1.00111111110 x 2^-6 = 1.01101011111 x 2^-3
+1A1F_0000_5F5E_34_5F5F_1 // f16_add_ru.tv line 36497 1A1F_5F5E_5F5F_01 1.01000011111 x 2^-9 + 1.01101011110 x 2^8 = 1.01101011111 x 2^8
+DEC5_0000_307F_34_DEC4_1 // f16_add_ru.tv line 36997 DEC5_307F_DEC4_01 -1.01011000101 x 2^8 + 1.00001111111 x 2^-3 = -1.01011000100 x 2^8
+407A_0000_6DE0_34_6DE1_1 // f16_add_ru.tv line 37497 407A_6DE0_6DE1_01 1.00001111010 x 2^1 + 1.00111100000 x 2^12 = 1.00111100001 x 2^12
+7BDF_0000_32BF_34_7BE0_1 // f16_add_ru.tv line 37997 7BDF_32BF_7BE0_01 1.01111011111 x 2^15 + 1.01010111111 x 2^-3 = 1.01111100000 x 2^15
+B7F2_0000_8A31_34_B7F2_1 // f16_add_ru.tv line 38497 B7F2_8A31_B7F2_01 -1.01111110010 x 2^-2 + -1.01000110001 x 2^-13 = -1.01111110010 x 2^-2
+337F_0000_43EB_34_4432_1 // f16_add_ru.tv line 38997 337F_43EB_4432_01 1.01101111111 x 2^-3 + 1.01111101011 x 2^1 = 1.00000110010 x 2^2
+B3AE_0000_6B3F_34_6B3F_1 // f16_add_ru.tv line 39497 B3AE_6B3F_6B3F_01 -1.01110101110 x 2^-3 + 1.01100111111 x 2^11 = 1.01100111111 x 2^11
+BFFF_0000_3AFF_34_BC7F_1 // f16_add_ru.tv line 39997 BFFF_3AFF_BC7F_01 -1.01111111111 x 2^0 + 1.01011111111 x 2^-1 = -1.00001111111 x 2^0
+583E_0000_BBAC_34_5837_1 // f16_add_ru.tv line 40497 583E_BBAC_5837_01 1.00000111110 x 2^7 + -1.01110101100 x 2^-1 = 1.00000110111 x 2^7
+A7FF_0000_A3CD_34_A9F2_1 // f16_add_ru.tv line 40997 A7FF_A3CD_A9F2_01 -1.01111111111 x 2^-6 + -1.01111001101 x 2^-7 = -1.00111110010 x 2^-5
+2E38_0000_FBE7_34_FBE6_1 // f16_add_ru.tv line 41497 2E38_FBE7_FBE6_01 1.01000111000 x 2^-4 + -1.01111100111 x 2^15 = -1.01111100110 x 2^15
+D844_0000_C3FA_34_D863_1 // f16_add_ru.tv line 41997 D844_C3FA_D863_01 -1.00001000100 x 2^7 + -1.01111111010 x 2^1 = -1.00001100011 x 2^7
+2C0B_0000_BBE7_34_BB65_1 // f16_add_ru.tv line 42497 2C0B_BBE7_BB65_01 1.00000001011 x 2^-4 + -1.01111100111 x 2^-1 = -1.01101100101 x 2^-1
+B73E_0000_47E0_34_476D_1 // f16_add_ru.tv line 42997 B73E_47E0_476D_01 -1.01100111110 x 2^-2 + 1.01111100000 x 2^2 = 1.01101101101 x 2^2
+4FEA_0000_D3A7_34_CF64_0 // f16_add_ru.tv line 43497 4FEA_D3A7_CF64_00 1.01111101010 x 2^4 + -1.01110100111 x 2^5 = -1.01101100100 x 2^4
+FB3E_0000_43F9_34_FB3D_1 // f16_add_ru.tv line 43997 FB3E_43F9_FB3D_01 -1.01100111110 x 2^15 + 1.01111111001 x 2^1 = -1.01100111101 x 2^15
+B4DF_0000_BBFE_34_BD36_1 // f16_add_ru.tv line 44497 B4DF_BBFE_BD36_01 -1.00011011111 x 2^-2 + -1.01111111110 x 2^-1 = -1.00100110110 x 2^0
+07B9_0000_B508_34_B507_1 // f16_add_ru.tv line 44997 07B9_B508_B507_01 1.01110111001 x 2^-14 + -1.00100001000 x 2^-2 = -1.00100000111 x 2^-2
+8575_0000_B405_34_B405_1 // f16_add_ru.tv line 45497 8575_B405_B405_01 -1.00101110101 x 2^-14 + -1.00000000101 x 2^-2 = -1.00000000101 x 2^-2
+6ADE_0000_B440_34_6ADE_1 // f16_add_ru.tv line 45997 6ADE_B440_6ADE_01 1.01011011110 x 2^11 + -1.00001000000 x 2^-2 = 1.01011011110 x 2^11
+
+////////// Testcases from f16_add_rne.tv of type add rounding mode 1
+EB08_0000_AD2E_14_EB08_1 // f16_add_rne.tv line 499 EB08_AD2E_EB08_01 -1.01100001000 x 2^11 + -1.00100101110 x 2^-4 = -1.01100001000 x 2^11
+CC83_0000_6081_14_605D_1 // f16_add_rne.tv line 999 CC83_6081_605D_01 -1.00010000011 x 2^4 + 1.00010000001 x 2^9 = 1.00001011101 x 2^9
+E2EF_0000_BF7C_14_E2F3_1 // f16_add_rne.tv line 1499 E2EF_BF7C_E2F3_01 -1.01011101111 x 2^9 + -1.01101111100 x 2^0 = -1.01011110011 x 2^9
+4F3E_0000_7440_14_7442_1 // f16_add_rne.tv line 1999 4F3E_7440_7442_01 1.01100111110 x 2^4 + 1.00001000000 x 2^14 = 1.00001000010 x 2^14
+3538_0000_FC7F_14_FE7F_0 // f16_add_rne.tv line 2499 3538_FC7F_FE7F_10 1.00100111000 x 2^-2 + NaN = NaN
+CE7E_0000_A80B_14_CE80_1 // f16_add_rne.tv line 2999 CE7E_A80B_CE80_01 -1.01001111110 x 2^4 + -1.00000001011 x 2^-5 = -1.01010000000 x 2^4
+7BC3_0000_93F6_14_7BC3_1 // f16_add_rne.tv line 3499 7BC3_93F6_7BC3_01 1.01111000011 x 2^15 + -1.01111110110 x 2^-11 = 1.01111000011 x 2^15
+F80D_0000_2B7C_14_F80D_1 // f16_add_rne.tv line 3999 F80D_2B7C_F80D_01 -1.00000001101 x 2^15 + 1.01101111100 x 2^-5 = -1.00000001101 x 2^15
+8BE8_0000_E2DA_14_E2DA_1 // f16_add_rne.tv line 4499 8BE8_E2DA_E2DA_01 -1.01111101000 x 2^-13 + -1.01011011010 x 2^9 = -1.01011011010 x 2^9
+37EF_0000_B089_14_35AA_1 // f16_add_rne.tv line 4999 37EF_B089_35AA_01 1.01111101111 x 2^-2 + -1.00010001001 x 2^-3 = 1.00110101010 x 2^-2
+17FF_0000_577F_14_577F_1 // f16_add_rne.tv line 5499 17FF_577F_577F_01 1.01111111111 x 2^-10 + 1.01101111111 x 2^6 = 1.01101111111 x 2^6
+30BE_0000_CF03_14_CEFA_1 // f16_add_rne.tv line 5999 30BE_CF03_CEFA_01 1.00010111110 x 2^-3 + -1.01100000011 x 2^4 = -1.01011111010 x 2^4
+B41F_0000_C5C1_14_C603_1 // f16_add_rne.tv line 6499 B41F_C5C1_C603_01 -1.00000011111 x 2^-2 + -1.00111000001 x 2^2 = -1.01000000011 x 2^2
+7DB3_0000_B738_14_7FB3_0 // f16_add_rne.tv line 6999 7DB3_B738_7FB3_10 NaN + -1.01100111000 x 2^-2 = NaN
+BFD4_0000_4811_14_462D_0 // f16_add_rne.tv line 7499 BFD4_4811_462D_00 -1.01111010100 x 2^0 + 1.00000010001 x 2^3 = 1.01000101101 x 2^2
+C643_0000_541F_14_5376_1 // f16_add_rne.tv line 7999 C643_541F_5376_01 -1.01001000011 x 2^2 + 1.00000011111 x 2^6 = 1.01101110110 x 2^5
+47B7_0000_AFEE_14_4797_1 // f16_add_rne.tv line 8499 47B7_AFEE_4797_01 1.01110110111 x 2^2 + -1.01111101110 x 2^-4 = 1.01110010111 x 2^2
+F45E_0000_B6FB_14_F45E_1 // f16_add_rne.tv line 8999 F45E_B6FB_F45E_01 -1.00001011110 x 2^14 + -1.01011111011 x 2^-2 = -1.00001011110 x 2^14
+7F9F_0000_7C0A_14_7F9F_0 // f16_add_rne.tv line 9499 7F9F_7C0A_7F9F_10 NaN + NaN = NaN
+743C_0000_37FE_14_743C_1 // f16_add_rne.tv line 9999 743C_37FE_743C_01 1.00000111100 x 2^14 + 1.01111111110 x 2^-2 = 1.00000111100 x 2^14
+// Skipped denorm f16_add_rne.tv line 10499 03DB_3F03_3F03_01 Denorm + 1.01100000011 x 2^0 = 1.01100000011 x 2^0
+5731_0000_A009_14_5731_1 // f16_add_rne.tv line 10999 5731_A009_5731_01 1.01100110001 x 2^6 + -1.00000001001 x 2^-7 = 1.01100110001 x 2^6
+2FBF_0000_09FD_14_2FC2_1 // f16_add_rne.tv line 11499 2FBF_09FD_2FC2_01 1.01110111111 x 2^-4 + 1.00111111101 x 2^-13 = 1.01111000010 x 2^-4
+1013_0000_4EFA_14_4EFA_1 // f16_add_rne.tv line 11999 1013_4EFA_4EFA_01 1.00000010011 x 2^-11 + 1.01011111010 x 2^4 = 1.01011111010 x 2^4
+1082_0000_14BE_14_16FF_0 // f16_add_rne.tv line 12499 1082_14BE_16FF_00 1.00010000010 x 2^-11 + 1.00010111110 x 2^-10 = 1.01011111111 x 2^-10
+3306_0000_C00A_14_BF33_1 // f16_add_rne.tv line 12999 3306_C00A_BF33_01 1.01100000110 x 2^-3 + -1.00000001010 x 2^1 = -1.01100110011 x 2^0
+4C10_0000_06EE_14_4C10_1 // f16_add_rne.tv line 13499 4C10_06EE_4C10_01 1.00000010000 x 2^4 + 1.01011101110 x 2^-14 = 1.00000010000 x 2^4
+C3E2_0000_BFFE_14_C5F0_1 // f16_add_rne.tv line 13999 C3E2_BFFE_C5F0_01 -1.01111100010 x 2^1 + -1.01111111110 x 2^0 = -1.00111110000 x 2^2
+F844_0000_570E_14_F840_1 // f16_add_rne.tv line 14499 F844_570E_F840_01 -1.00001000100 x 2^15 + 1.01100001110 x 2^6 = -1.00001000000 x 2^15
+C0FD_0000_B403_14_C17D_1 // f16_add_rne.tv line 14999 C0FD_B403_C17D_01 -1.00011111101 x 2^1 + -1.00000000011 x 2^-2 = -1.00101111101 x 2^1
+FEFE_0000_84F9_14_FEFE_0 // f16_add_rne.tv line 15499 FEFE_84F9_FEFE_00 NaN + -1.00011111001 x 2^-14 = NaN
+// Skipped denorm f16_add_rne.tv line 15999 0030_CC91_CC91_01 Denorm + -1.00010010001 x 2^4 = -1.00010010001 x 2^4
+53C8_0000_BB7A_14_53AA_1 // f16_add_rne.tv line 16499 53C8_BB7A_53AA_01 1.01111001000 x 2^5 + -1.01101111010 x 2^-1 = 1.01110101010 x 2^5
+2102_0000_B42E_14_B406_1 // f16_add_rne.tv line 16999 2102_B42E_B406_01 1.00100000010 x 2^-7 + -1.00000101110 x 2^-2 = -1.00000000110 x 2^-2
+B782_0000_FB15_14_FB15_1 // f16_add_rne.tv line 17499 B782_FB15_FB15_01 -1.01110000010 x 2^-2 + -1.01100010101 x 2^15 = -1.01100010101 x 2^15
+8423_0000_CF98_14_CF98_1 // f16_add_rne.tv line 17999 8423_CF98_CF98_01 -1.00000100011 x 2^-14 + -1.01110011000 x 2^4 = -1.01110011000 x 2^4
+3322_0000_C566_14_C52D_1 // f16_add_rne.tv line 18499 3322_C566_C52D_01 1.01100100010 x 2^-3 + -1.00101100110 x 2^2 = -1.00100101101 x 2^2
+4FDC_0000_07C7_14_4FDC_1 // f16_add_rne.tv line 18999 4FDC_07C7_4FDC_01 1.01111011100 x 2^4 + 1.01111000111 x 2^-14 = 1.01111011100 x 2^4
+CBFE_0000_C835_14_CE1A_1 // f16_add_rne.tv line 19499 CBFE_C835_CE1A_01 -1.01111111110 x 2^3 + -1.00000110101 x 2^3 = -1.01000011010 x 2^4
+27F6_0000_F1C2_14_F1C2_1 // f16_add_rne.tv line 19999 27F6_F1C2_F1C2_01 1.01111110110 x 2^-6 + -1.00111000010 x 2^13 = -1.00111000010 x 2^13
+CA1F_0000_4F6E_14_4C5E_1 // f16_add_rne.tv line 20499 CA1F_4F6E_4C5E_01 -1.01000011111 x 2^3 + 1.01101101110 x 2^4 = 1.00001011110 x 2^4
+477C_0000_ABFF_14_476C_1 // f16_add_rne.tv line 20999 477C_ABFF_476C_01 1.01101111100 x 2^2 + -1.01111111111 x 2^-5 = 1.01101101100 x 2^2
+// Skipped denorm f16_add_rne.tv line 21499 B841_83EF_B841_01 -1.00001000001 x 2^-1 + -Denorm = -1.00001000001 x 2^-1
+8800_0000_4FC4_14_4FC4_1 // f16_add_rne.tv line 21999 8800_4FC4_4FC4_01 -1.00000000000 x 2^-13 + 1.01111000100 x 2^4 = 1.01111000100 x 2^4
+2840_0000_75BF_14_75BF_1 // f16_add_rne.tv line 22499 2840_75BF_75BF_01 1.00001000000 x 2^-5 + 1.00110111111 x 2^14 = 1.00110111111 x 2^14
+49F9_0000_CC88_14_C62E_0 // f16_add_rne.tv line 22999 49F9_CC88_C62E_00 1.00111111001 x 2^3 + -1.00010001000 x 2^4 = -1.01000101110 x 2^2
+FE1E_0000_FFC3_14_FE1E_0 // f16_add_rne.tv line 23499 FE1E_FFC3_FE1E_00 NaN + NaN = NaN
+879E_0000_060F_14_818F_0 // f16_add_rne.tv line 23999 879E_060F_818F_00 -1.01110011110 x 2^-14 + 1.01000001111 x 2^-14 = -Denorm
+DC1B_0000_F460_14_F470_1 // f16_add_rne.tv line 24499 DC1B_F460_F470_01 -1.00000011011 x 2^8 + -1.00001100000 x 2^14 = -1.00001110000 x 2^14
+047C_0000_FBB7_14_FBB7_1 // f16_add_rne.tv line 24999 047C_FBB7_FBB7_01 1.00001111100 x 2^-14 + -1.01110110111 x 2^15 = -1.01110110111 x 2^15
+B03F_0000_CD6E_14_CD76_1 // f16_add_rne.tv line 25499 B03F_CD6E_CD76_01 -1.00000111111 x 2^-3 + -1.00101101110 x 2^4 = -1.00101110110 x 2^4
+// Skipped denorm f16_add_rne.tv line 25999 00FF_687E_687E_01 Denorm + 1.00001111110 x 2^11 = 1.00001111110 x 2^11
+BB9F_0000_C44E_14_C542_1 // f16_add_rne.tv line 26499 BB9F_C44E_C542_01 -1.01110011111 x 2^-1 + -1.00001001110 x 2^2 = -1.00101000010 x 2^2
+3FF9_0000_6390_14_6394_1 // f16_add_rne.tv line 26999 3FF9_6390_6394_01 1.01111111001 x 2^0 + 1.01110010000 x 2^9 = 1.01110010100 x 2^9
+0A3F_0000_FC81_14_FE81_0 // f16_add_rne.tv line 27499 0A3F_FC81_FE81_10 1.01000111111 x 2^-13 + NaN = NaN
+363F_0000_CBBF_14_CB8D_1 // f16_add_rne.tv line 27999 363F_CBBF_CB8D_01 1.01000111111 x 2^-2 + -1.01110111111 x 2^3 = -1.01110001101 x 2^3
+// Skipped denorm f16_add_rne.tv line 28499 807D_7BE0_7BE0_01 -Denorm + 1.01111100000 x 2^15 = 1.01111100000 x 2^15
+B27F_0000_4840_14_4826_1 // f16_add_rne.tv line 28999 B27F_4840_4826_01 -1.01001111111 x 2^-3 + 1.00001000000 x 2^3 = 1.00000100110 x 2^3
+0710_0000_7B89_14_7B89_1 // f16_add_rne.tv line 29499 0710_7B89_7B89_01 1.01100010000 x 2^-14 + 1.01110001001 x 2^15 = 1.01110001001 x 2^15
+4C9F_0000_AEC0_14_4C98_1 // f16_add_rne.tv line 29999 4C9F_AEC0_4C98_01 1.00010011111 x 2^4 + -1.01011000000 x 2^-4 = 1.00010011000 x 2^4
+6887_0000_B57F_14_6887_1 // f16_add_rne.tv line 30499 6887_B57F_6887_01 1.00010000111 x 2^11 + -1.00101111111 x 2^-2 = 1.00010000111 x 2^11
+CC1C_0000_E2AF_14_E2D0_1 // f16_add_rne.tv line 30999 CC1C_E2AF_E2D0_01 -1.00000011100 x 2^4 + -1.01010101111 x 2^9 = -1.01011010000 x 2^9
+1C0C_0000_EBD0_14_EBD0_1 // f16_add_rne.tv line 31499 1C0C_EBD0_EBD0_01 1.00000001100 x 2^-8 + -1.01111010000 x 2^11 = -1.01111010000 x 2^11
+FDF7_0000_3D3E_14_FFF7_0 // f16_add_rne.tv line 31999 FDF7_3D3E_FFF7_10 NaN + 1.00100111110 x 2^0 = NaN
+0B40_0000_B807_14_B807_1 // f16_add_rne.tv line 32499 0B40_B807_B807_01 1.01101000000 x 2^-13 + -1.00000000111 x 2^-1 = -1.00000000111 x 2^-1
+9080_0000_D102_14_D102_1 // f16_add_rne.tv line 32999 9080_D102_D102_01 -1.00010000000 x 2^-11 + -1.00100000010 x 2^5 = -1.00100000010 x 2^5
+// Skipped denorm f16_add_rne.tv line 33499 B021_03F4_B021_01 -1.00000100001 x 2^-3 + Denorm = -1.00000100001 x 2^-3
+// Skipped denorm f16_add_rne.tv line 33999 DAFE_03FF_DAFE_01 -1.01011111110 x 2^7 + Denorm = -1.01011111110 x 2^7
+7F01_0000_D122_14_7F01_0 // f16_add_rne.tv line 34499 7F01_D122_7F01_00 NaN + -1.00100100010 x 2^5 = NaN
+B041_0000_7506_14_7506_1 // f16_add_rne.tv line 34999 B041_7506_7506_01 -1.00001000001 x 2^-3 + 1.00100000110 x 2^14 = 1.00100000110 x 2^14
+C37D_0000_6877_14_6875_1 // f16_add_rne.tv line 35499 C37D_6877_6875_01 -1.01101111101 x 2^1 + 1.00001110111 x 2^11 = 1.00001110101 x 2^11
+87DE_0000_7F78_14_7F78_0 // f16_add_rne.tv line 35999 87DE_7F78_7F78_00 -1.01111011110 x 2^-14 + NaN = NaN
+5604_0000_87F7_14_5604_1 // f16_add_rne.tv line 36499 5604_87F7_5604_01 1.01000000100 x 2^6 + -1.01111110111 x 2^-14 = 1.01000000100 x 2^6
+38F0_0000_8BFC_14_38F0_1 // f16_add_rne.tv line 36999 38F0_8BFC_38F0_01 1.00011110000 x 2^-1 + -1.01111111100 x 2^-13 = 1.00011110000 x 2^-1
+C274_0000_91CE_14_C274_1 // f16_add_rne.tv line 37499 C274_91CE_C274_01 -1.01001110100 x 2^1 + -1.00111001110 x 2^-11 = -1.01001110100 x 2^1
+A2FE_0000_2DDE_14_2CFE_1 // f16_add_rne.tv line 37999 A2FE_2DDE_2CFE_01 -1.01011111110 x 2^-7 + 1.00111011110 x 2^-4 = 1.00011111110 x 2^-4
+37FE_0000_C7EF_14_C76F_1 // f16_add_rne.tv line 38499 37FE_C7EF_C76F_01 1.01111111110 x 2^-2 + -1.01111101111 x 2^2 = -1.01101101111 x 2^2
+446F_0000_DBFA_14_DBD7_1 // f16_add_rne.tv line 38999 446F_DBFA_DBD7_01 1.00001101111 x 2^2 + -1.01111111010 x 2^7 = -1.01111010111 x 2^7
+3BFC_0000_7B80_14_7B80_1 // f16_add_rne.tv line 39499 3BFC_7B80_7B80_01 1.01111111100 x 2^-1 + 1.01110000000 x 2^15 = 1.01110000000 x 2^15
+4C02_0000_2507_14_4C03_1 // f16_add_rne.tv line 39999 4C02_2507_4C03_01 1.00000000010 x 2^4 + 1.00100000111 x 2^-6 = 1.00000000011 x 2^4
+// Skipped denorm f16_add_rne.tv line 40499 08C0_010F_0948_01 1.00011000000 x 2^-13 + Denorm = 1.00101001000 x 2^-13
+BFF8_0000_3E3E_14_B6E8_0 // f16_add_rne.tv line 40999 BFF8_3E3E_B6E8_00 -1.01111111000 x 2^0 + 1.01000111110 x 2^0 = -1.01011101000 x 2^-2
+CBC2_0000_27EC_14_CBBE_1 // f16_add_rne.tv line 41499 CBC2_27EC_CBBE_01 -1.01111000010 x 2^3 + 1.01111101100 x 2^-6 = -1.01110111110 x 2^3
+4655_0000_DD8E_14_DD75_1 // f16_add_rne.tv line 41999 4655_DD8E_DD75_01 1.01001010101 x 2^2 + -1.00110001110 x 2^8 = -1.00101110101 x 2^8
+DD46_0000_9340_14_DD46_1 // f16_add_rne.tv line 42499 DD46_9340_DD46_01 -1.00101000110 x 2^8 + -1.01101000000 x 2^-11 = -1.00101000110 x 2^8
+9200_0000_CDE8_14_CDE8_1 // f16_add_rne.tv line 42999 9200_CDE8_CDE8_01 -1.01000000000 x 2^-11 + -1.00111101000 x 2^4 = -1.00111101000 x 2^4
+// Skipped denorm f16_add_rne.tv line 43499 5BE0_83E2_5BE0_01 1.01111100000 x 2^7 + -Denorm = 1.01111100000 x 2^7
+74BF_0000_CAC0_14_74BE_1 // f16_add_rne.tv line 43999 74BF_CAC0_74BE_01 1.00010111111 x 2^14 + -1.01011000000 x 2^3 = 1.00010111110 x 2^14
+B6ED_0000_C87E_14_C8B5_1 // f16_add_rne.tv line 44499 B6ED_C87E_C8B5_01 -1.01011101101 x 2^-2 + -1.00001111110 x 2^3 = -1.00010110101 x 2^3
+41EF_0000_AFC3_14_41B1_1 // f16_add_rne.tv line 44999 41EF_AFC3_41B1_01 1.00111101111 x 2^1 + -1.01111000011 x 2^-4 = 1.00110110001 x 2^1
+C8A0_0000_11F0_14_C8A0_1 // f16_add_rne.tv line 45499 C8A0_11F0_C8A0_01 -1.00010100000 x 2^3 + 1.00111110000 x 2^-11 = -1.00010100000 x 2^3
+D805_0000_7A09_14_7A05_1 // f16_add_rne.tv line 45999 D805_7A09_7A05_01 -1.00000000101 x 2^7 + 1.01000001001 x 2^15 = 1.01000000101 x 2^15
+
+////////// Testcases from f16_mul_rz.tv of type mul rounding mode 0
+0000_FA02_3CFF_08_8000_0 // f16_mul_rz.tv line 500 0000_FA02_8000_00 0 * -1.01000000010 x 2^15 = -Denorm
+93FF_EBFF_3CFF_08_43FE_1 // f16_mul_rz.tv line 1000 93FF_EBFF_43FE_01 -1.01111111111 x 2^-11 * -1.01111111111 x 2^11 = 1.01111111110 x 2^1
+// Skipped denorm f16_mul_rz.tv line 1500 03FF_C401_8BFF_01 Denorm * -1.00000000001 x 2^2 = -1.01111111111 x 2^-13
+// Skipped denorm f16_mul_rz.tv line 2000 03FE_0001_0000_03 Denorm * Denorm = 0
+54CE_BC00_3CFF_08_D4CE_0 // f16_mul_rz.tv line 2500 54CE_BC00_D4CE_00 1.00011001110 x 2^6 * -1.00000000000 x 2^0 = -1.00011001110 x 2^6
+0401_B7FE_3CFF_08_81FF_3 // f16_mul_rz.tv line 3000 0401_B7FE_81FF_03 1.00000000001 x 2^-14 * -1.01111111110 x 2^-2 = -Denorm
+07FF_C3FF_3CFF_08_8FFE_1 // f16_mul_rz.tv line 3500 07FF_C3FF_8FFE_01 1.01111111111 x 2^-14 * -1.01111111111 x 2^1 = -1.01111111110 x 2^-12
+9C3B_87FF_3CFF_08_0008_3 // f16_mul_rz.tv line 4000 9C3B_87FF_0008_03 -1.00000111011 x 2^-8 * -1.01111111111 x 2^-14 = Denorm
+// Skipped denorm f16_mul_rz.tv line 4500 1000_8001_8000_03 1.00000000000 x 2^-11 * -Denorm = -Denorm
+1001_2FBB_3CFF_08_03DE_3 // f16_mul_rz.tv line 5000 1001_2FBB_03DE_03 1.00000000001 x 2^-11 * 1.01110111011 x 2^-4 = Denorm
+37EE_7800_3CFF_08_73EE_0 // f16_mul_rz.tv line 5500 37EE_7800_73EE_00 1.01111101110 x 2^-2 * 1.00000000000 x 2^15 = 1.01111101110 x 2^13
+13FE_47FE_3CFF_08_1FFC_1 // f16_mul_rz.tv line 6000 13FE_47FE_1FFC_01 1.01111111110 x 2^-11 * 1.01111111110 x 2^2 = 1.01111111100 x 2^-8
+3400_CA47_3CFF_08_C247_0 // f16_mul_rz.tv line 6500 3400_CA47_C247_00 1.00000000000 x 2^-2 * -1.01001000111 x 2^3 = -1.01001000111 x 2^1
+30EE_3FFF_3CFF_08_34ED_1 // f16_mul_rz.tv line 7000 30EE_3FFF_34ED_01 1.00011101110 x 2^-3 * 1.01111111111 x 2^0 = 1.00011101101 x 2^-2
+37FF_3801_3CFF_08_3400_1 // f16_mul_rz.tv line 7500 37FF_3801_3400_01 1.01111111111 x 2^-2 * 1.00000000001 x 2^-1 = 1.00000000000 x 2^-2
+37FE_B783_3CFF_08_B381_1 // f16_mul_rz.tv line 8000 37FE_B783_B381_01 1.01111111110 x 2^-2 * -1.01110000011 x 2^-2 = -1.01110000001 x 2^-3
+0EBE_1000_3CFF_08_0003_3 // f16_mul_rz.tv line 8500 0EBE_1000_0003_03 1.01010111110 x 2^-12 * 1.00000000000 x 2^-11 = Denorm
+// Skipped denorm f16_mul_rz.tv line 9000 3801_03FE_01FF_03 1.00000000001 x 2^-1 * Denorm = Denorm
+3801_480F_3CFF_08_4410_1 // f16_mul_rz.tv line 9500 3801_480F_4410_01 1.00000000001 x 2^-1 * 1.00000001111 x 2^3 = 1.00000010000 x 2^2
+// Skipped denorm f16_mul_rz.tv line 10000 003E_FBFF_B3BF_01 Denorm * -1.01111111111 x 2^15 = -1.01110111111 x 2^-3
+3BFE_E801_3CFF_08_E7FF_1 // f16_mul_rz.tv line 10500 3BFE_E801_E7FF_01 1.01111111110 x 2^-1 * -1.00000000001 x 2^11 = -1.01111111111 x 2^10
+3C00_88D3_3CFF_08_88D3_0 // f16_mul_rz.tv line 11000 3C00_88D3_88D3_00 1.00000000000 x 2^0 * -1.00011010011 x 2^-13 = -1.00011010011 x 2^-13
+257F_C000_3CFF_08_A97F_0 // f16_mul_rz.tv line 11500 257F_C000_A97F_00 1.00101111111 x 2^-6 * -1.00000000000 x 2^1 = -1.00101111111 x 2^-5
+3FFF_BBFE_3CFF_08_BFFD_1 // f16_mul_rz.tv line 12000 3FFF_BBFE_BFFD_01 1.01111111111 x 2^0 * -1.01111111110 x 2^-1 = -1.01111111101 x 2^0
+3FFE_4AFD_3CFF_08_4EFB_1 // f16_mul_rz.tv line 12500 3FFE_4AFD_4EFB_01 1.01111111110 x 2^0 * 1.01011111101 x 2^3 = 1.01011111011 x 2^4
+B7FF_93FF_3CFF_08_0FFE_1 // f16_mul_rz.tv line 13000 B7FF_93FF_0FFE_01 -1.01111111111 x 2^-2 * -1.01111111111 x 2^-11 = 1.01111111110 x 2^-12
+4001_8401_3CFF_08_8802_1 // f16_mul_rz.tv line 13500 4001_8401_8802_01 1.00000000001 x 2^1 * -1.00000000001 x 2^-14 = -1.00000000010 x 2^-13
+43FF_3808_3CFF_08_4007_1 // f16_mul_rz.tv line 14000 43FF_3808_4007_01 1.01111111111 x 2^1 * 1.00000001000 x 2^-1 = 1.00000000111 x 2^1
+AC0A_7C00_3CFF_08_FC00_0 // f16_mul_rz.tv line 14500 AC0A_7C00_FC00_00 -1.00000001010 x 2^-4 * INF = -INF
+4400_6BFE_3CFF_08_73FE_0 // f16_mul_rz.tv line 15000 4400_6BFE_73FE_00 1.00000000000 x 2^2 * 1.01111111110 x 2^11 = 1.01111111110 x 2^13
+4401_D3F2_3CFF_08_DBF3_1 // f16_mul_rz.tv line 15500 4401_D3F2_DBF3_01 1.00000000001 x 2^2 * -1.01111110010 x 2^5 = -1.01111110011 x 2^7
+5BC2_43FF_3CFF_08_63C1_1 // f16_mul_rz.tv line 16000 5BC2_43FF_63C1_01 1.01111000010 x 2^7 * 1.01111111111 x 2^1 = 1.01111000001 x 2^9
+47FE_3C01_3CFF_08_47FF_1 // f16_mul_rz.tv line 16500 47FE_3C01_47FF_01 1.01111111110 x 2^2 * 1.00000000001 x 2^0 = 1.01111111111 x 2^2
+6800_13F1_3CFF_08_3FF1_0 // f16_mul_rz.tv line 17000 6800_13F1_3FF1_00 1.00000000000 x 2^11 * 1.01111110001 x 2^-11 = 1.01111110001 x 2^0
+78FB_3400_3CFF_08_70FB_0 // f16_mul_rz.tv line 17500 78FB_3400_70FB_00 1.00011111011 x 2^15 * 1.00000000000 x 2^-2 = 1.00011111011 x 2^13
+6BFF_07FE_3CFF_08_37FD_1 // f16_mul_rz.tv line 18000 6BFF_07FE_37FD_01 1.01111111111 x 2^11 * 1.01111111110 x 2^-14 = 1.01111111101 x 2^-2
+6BFE_13FE_3CFF_08_43FC_1 // f16_mul_rz.tv line 18500 6BFE_13FE_43FC_01 1.01111111110 x 2^11 * 1.01111111110 x 2^-11 = 1.01111111100 x 2^1
+382F_FFFF_3CFF_08_FFFF_0 // f16_mul_rz.tv line 19000 382F_FFFF_FFFF_00 1.00000101111 x 2^-1 * NaN = NaN
+7800_F801_3CFF_08_FBFF_5 // f16_mul_rz.tv line 19500 7800_F801_FBFF_05 1.00000000000 x 2^15 * -1.00000000001 x 2^15 = -1.01111111111 x 2^15
+7801_4877_3CFF_08_7BFF_5 // f16_mul_rz.tv line 20000 7801_4877_7BFF_05 1.00000000001 x 2^15 * 1.00001110111 x 2^3 = 1.01111111111 x 2^15
+// Skipped denorm f16_mul_rz.tv line 20500 0090_C400_8240_00 Denorm * -1.00000000000 x 2^2 = -Denorm
+7BFE_BFFE_3CFF_08_FBFF_5 // f16_mul_rz.tv line 21000 7BFE_BFFE_FBFF_05 1.01111111110 x 2^15 * -1.01111111110 x 2^0 = -1.01111111111 x 2^15
+7C00_4F08_3CFF_08_7C00_0 // f16_mul_rz.tv line 21500 7C00_4F08_7C00_00 INF * 1.01100001000 x 2^4 = INF
+BFFA_B7FF_3CFF_08_3BF9_1 // f16_mul_rz.tv line 22000 BFFA_B7FF_3BF9_01 -1.01111111010 x 2^0 * -1.01111111111 x 2^-2 = 1.01111111001 x 2^-1
+7FFF_9001_3CFF_08_7FFF_0 // f16_mul_rz.tv line 22500 7FFF_9001_7FFF_00 NaN * -1.00000000001 x 2^-11 = NaN
+7FFE_B82F_3CFF_08_7FFE_0 // f16_mul_rz.tv line 23000 7FFE_B82F_7FFE_00 NaN * -1.00000101111 x 2^-1 = NaN
+// Skipped denorm f16_mul_rz.tv line 23500 2F68_8000_8000_00 1.01101101000 x 2^-4 * -Denorm = -Denorm
+// Skipped denorm f16_mul_rz.tv line 24000 8001_7BFE_9BFE_00 -Denorm * 1.01111111110 x 2^15 = -1.01111111110 x 2^-9
+// Skipped denorm f16_mul_rz.tv line 24500 83FF_EB8E_338C_01 -Denorm * -1.01110001110 x 2^11 = 1.01110001100 x 2^-3
+75FF_47FF_3CFF_08_7BFF_5 // f16_mul_rz.tv line 25000 75FF_47FF_7BFF_05 1.00111111111 x 2^14 * 1.01111111111 x 2^2 = 1.01111111111 x 2^15
+8400_4001_3CFF_08_8801_0 // f16_mul_rz.tv line 25500 8400_4001_8801_00 -1.00000000000 x 2^-14 * 1.00000000001 x 2^1 = -1.00000000001 x 2^-13
+8401_C3E7_3CFF_08_0BE8_1 // f16_mul_rz.tv line 26000 8401_C3E7_0BE8_01 -1.00000000001 x 2^-14 * -1.01111100111 x 2^1 = 1.01111101000 x 2^-13
+CC00_3800_3CFF_08_C800_0 // f16_mul_rz.tv line 26500 CC00_3800_C800_00 -1.00000000000 x 2^4 * 1.00000000000 x 2^-1 = -1.00000000000 x 2^3
+87FE_13FE_3CFF_08_8001_3 // f16_mul_rz.tv line 27000 87FE_13FE_8001_03 -1.01111111110 x 2^-14 * 1.01111111110 x 2^-11 = -Denorm
+9000_7FF2_3CFF_08_7FF2_0 // f16_mul_rz.tv line 27500 9000_7FF2_7FF2_00 -1.00000000000 x 2^-11 * NaN = NaN
+// Skipped denorm f16_mul_rz.tv line 28000 C082_03FF_8880_01 -1.00010000010 x 2^1 * Denorm = -1.00010000000 x 2^-13
+9001_FC01_3CFF_08_FE01_0 // f16_mul_rz.tv line 28500 9001_FC01_FE01_10 -1.00000000001 x 2^-11 * NaN = NaN
+93FF_2DFF_3CFF_08_85FE_1 // f16_mul_rz.tv line 29000 93FF_2DFF_85FE_01 -1.01111111111 x 2^-11 * 1.00111111111 x 2^-4 = -1.00111111110 x 2^-14
+BE01_E800_3CFF_08_6A01_0 // f16_mul_rz.tv line 29500 BE01_E800_6A01_00 -1.01000000001 x 2^0 * -1.00000000000 x 2^11 = 1.01000000001 x 2^11
+B400_C3FE_3CFF_08_3BFE_0 // f16_mul_rz.tv line 30000 B400_C3FE_3BFE_00 -1.00000000000 x 2^-2 * -1.01111111110 x 2^1 = 1.01111111110 x 2^-1
+B401_2702_3CFF_08_9F03_1 // f16_mul_rz.tv line 30500 B401_2702_9F03_01 -1.00000000001 x 2^-2 * 1.01100000010 x 2^-6 = -1.01100000011 x 2^-8
+E09F_BBFF_3CFF_08_609E_1 // f16_mul_rz.tv line 31000 E09F_BBFF_609E_01 -1.00010011111 x 2^9 * -1.01111111111 x 2^-1 = 1.00010011110 x 2^9
+B7FE_B401_3CFF_08_2FFF_1 // f16_mul_rz.tv line 31500 B7FE_B401_2FFF_01 -1.01111111110 x 2^-2 * -1.00000000001 x 2^-2 = 1.01111111111 x 2^-4
+// Skipped denorm f16_mul_rz.tv line 32000 B800_80BF_005F_03 -1.00000000000 x 2^-1 * -Denorm = Denorm
+6BBC_8400_3CFF_08_B3BC_0 // f16_mul_rz.tv line 32500 6BBC_8400_B3BC_00 1.01110111100 x 2^11 * -1.00000000000 x 2^-14 = -1.01110111100 x 2^-3
+BBFF_7FFE_3CFF_08_7FFE_0 // f16_mul_rz.tv line 33000 BBFF_7FFE_7FFE_00 -1.01111111111 x 2^-1 * NaN = NaN
+BBFE_09DF_3CFF_08_89DD_1 // f16_mul_rz.tv line 33500 BBFE_09DF_89DD_01 -1.01111111110 x 2^-1 * 1.00111011111 x 2^-13 = -1.00111011101 x 2^-13
+124E_6BFF_3CFF_08_424D_1 // f16_mul_rz.tv line 34000 124E_6BFF_424D_01 1.01001001110 x 2^-11 * 1.01111111111 x 2^11 = 1.01001001101 x 2^1
+BC01_4401_3CFF_08_C402_1 // f16_mul_rz.tv line 34500 BC01_4401_C402_01 -1.00000000001 x 2^0 * 1.00000000001 x 2^2 = -1.00000000010 x 2^2
+BFFF_10BF_3CFF_08_94BE_1 // f16_mul_rz.tv line 35000 BFFF_10BF_94BE_01 -1.01111111111 x 2^0 * 1.00010111111 x 2^-11 = -1.00010111110 x 2^-10
+48EF_3C00_3CFF_08_48EF_0 // f16_mul_rz.tv line 35500 48EF_3C00_48EF_00 1.00011101111 x 2^3 * 1.00000000000 x 2^0 = 1.00011101111 x 2^3
+C000_37FE_3CFF_08_BBFE_0 // f16_mul_rz.tv line 36000 C000_37FE_BBFE_00 -1.00000000000 x 2^1 * 1.01111111110 x 2^-2 = -1.01111111110 x 2^-1
+// Skipped denorm f16_mul_rz.tv line 36500 C001_021F_843F_01 -1.00000000001 x 2^1 * Denorm = -1.00000111111 x 2^-14
+1180_07FF_3CFF_08_0001_3 // f16_mul_rz.tv line 37000 1180_07FF_0001_03 1.00110000000 x 2^-11 * 1.01111111111 x 2^-14 = Denorm
+// Skipped denorm f16_mul_rz.tv line 37500 C3FE_0001_8003_03 -1.01111111110 x 2^1 * Denorm = -Denorm
+// Skipped denorm f16_mul_rz.tv line 38000 C3FE_00FF_83FB_03 -1.01111111110 x 2^1 * Denorm = -Denorm
+1A7C_F800_3CFF_08_D67C_0 // f16_mul_rz.tv line 38500 1A7C_F800_D67C_00 1.01001111100 x 2^-9 * -1.00000000000 x 2^15 = -1.01001111100 x 2^6
+C401_C7FE_3CFF_08_4FFF_1 // f16_mul_rz.tv line 39000 C401_C7FE_4FFF_01 -1.00000000001 x 2^2 * -1.01111111110 x 2^2 = 1.01111111111 x 2^4
+C7FF_C73F_3CFF_08_533E_1 // f16_mul_rz.tv line 39500 C7FF_C73F_533E_01 -1.01111111111 x 2^2 * -1.01100111111 x 2^2 = 1.01100111110 x 2^5
+3F10_BFFF_3CFF_08_C30F_1 // f16_mul_rz.tv line 40000 3F10_BFFF_C30F_01 1.01100010000 x 2^0 * -1.01111111111 x 2^0 = -1.01100001111 x 2^1
+E800_B801_3CFF_08_6401_0 // f16_mul_rz.tv line 40500 E800_B801_6401_00 -1.00000000000 x 2^11 * -1.00000000001 x 2^-1 = 1.00000000001 x 2^10
+E801_B387_3CFF_08_5F88_1 // f16_mul_rz.tv line 41000 E801_B387_5F88_01 -1.00000000001 x 2^11 * -1.01110000111 x 2^-3 = 1.01110001000 x 2^8
+CBE1_9000_3CFF_08_1FE1_0 // f16_mul_rz.tv line 41500 CBE1_9000_1FE1_00 -1.01111100001 x 2^3 * -1.00000000000 x 2^-11 = 1.01111100001 x 2^-8
+// Skipped denorm f16_mul_rz.tv line 42000 EBFE_83FE_33FA_01 -1.01111111110 x 2^11 * -Denorm = 1.01111111010 x 2^-3
+F800_3F00_3CFF_08_FB00_0 // f16_mul_rz.tv line 42500 F800_3F00_FB00_00 -1.00000000000 x 2^15 * 1.01100000000 x 2^0 = -1.01100000000 x 2^15
+CFBF_7BFF_3CFF_08_FBFF_5 // f16_mul_rz.tv line 43000 CFBF_7BFF_FBFF_05 -1.01110111111 x 2^4 * 1.01111111111 x 2^15 = -1.01111111111 x 2^15
+FBFF_6801_3CFF_08_FBFF_5 // f16_mul_rz.tv line 43500 FBFF_6801_FBFF_05 -1.01111111111 x 2^15 * 1.00000000001 x 2^11 = -1.01111111111 x 2^15
+FBFE_11FF_3CFF_08_D1FD_1 // f16_mul_rz.tv line 44000 FBFE_11FF_D1FD_01 -1.01111111110 x 2^15 * 1.00111111111 x 2^-11 = -1.00111111101 x 2^5
+3CD8_4000_3CFF_08_40D8_0 // f16_mul_rz.tv line 44500 3CD8_4000_40D8_00 1.00011011000 x 2^0 * 1.00000000000 x 2^1 = 1.00011011000 x 2^1
+FC01_3BFE_3CFF_08_FE01_0 // f16_mul_rz.tv line 45000 FC01_3BFE_FE01_10 NaN * 1.01111111110 x 2^-1 = NaN
+FFFF_44F7_3CFF_08_FFFF_0 // f16_mul_rz.tv line 45500 FFFF_44F7_FFFF_00 NaN * 1.00011110111 x 2^2 = NaN
+CB78_13FF_3CFF_08_A377_1 // f16_mul_rz.tv line 46000 CB78_13FF_A377_01 -1.01101111000 x 2^3 * 1.01111111111 x 2^-11 = -1.01101110111 x 2^-7
+
+////////// Testcases from f16_mul_rd.tv of type mul rounding mode 2
+0000_FBFF_3CFF_28_8000_0 // f16_mul_rd.tv line 498 0000_FBFF_8000_00 0 * -1.01111111111 x 2^15 = -Denorm
+// Skipped denorm f16_mul_rd.tv line 998 0001_448C_0004_03 Denorm * 1.00010001100 x 2^2 = Denorm
+C3A0_C401_3CFF_28_4BA1_1 // f16_mul_rd.tv line 1498 C3A0_C401_4BA1_01 -1.01110100000 x 2^1 * -1.00000000001 x 2^2 = 1.01110100001 x 2^3
+// Skipped denorm f16_mul_rd.tv line 1998 03FE_C000_87FC_00 Denorm * -1.00000000000 x 2^1 = -1.01111111100 x 2^-14
+0400_68A5_3CFF_28_30A5_0 // f16_mul_rd.tv line 2498 0400_68A5_30A5_00 1.00000000000 x 2^-14 * 1.00010100101 x 2^11 = 1.00010100101 x 2^-3
+// Skipped denorm f16_mul_rd.tv line 2998 02FD_B7FE_817F_03 Denorm * -1.01111111110 x 2^-2 = -Denorm
+07FF_93FF_3CFF_28_8002_3 // f16_mul_rd.tv line 3498 07FF_93FF_8002_03 1.01111111111 x 2^-14 * -1.01111111111 x 2^-11 = -Denorm
+07FE_33CF_3CFF_28_01F3_3 // f16_mul_rd.tv line 3998 07FE_33CF_01F3_03 1.01111111110 x 2^-14 * 1.01111001111 x 2^-3 = Denorm
+// Skipped denorm f16_mul_rd.tv line 4498 EAFB_8001_0AFB_00 -1.01011111011 x 2^11 * -Denorm = 1.01011111011 x 2^-13
+1001_7C00_3CFF_28_7C00_0 // f16_mul_rd.tv line 4998 1001_7C00_7C00_00 1.00000000001 x 2^-11 * INF = INF
+13FF_32E7_3CFF_28_0AE6_1 // f16_mul_rd.tv line 5498 13FF_32E7_0AE6_01 1.01111111111 x 2^-11 * 1.01011100111 x 2^-3 = 1.01011100110 x 2^-13
+BC1F_47FE_3CFF_28_C81E_1 // f16_mul_rd.tv line 5998 BC1F_47FE_C81E_01 -1.00000011111 x 2^0 * 1.01111111110 x 2^2 = -1.00000011110 x 2^3
+3400_43FF_3CFF_28_3BFF_0 // f16_mul_rd.tv line 6498 3400_43FF_3BFF_00 1.00000000000 x 2^-2 * 1.01111111111 x 2^1 = 1.01111111111 x 2^-1
+3401_9AE8_3CFF_28_92EA_1 // f16_mul_rd.tv line 6998 3401_9AE8_92EA_01 1.00000000001 x 2^-2 * -1.01011101000 x 2^-9 = -1.01011101010 x 2^-11
+7703_3801_3CFF_28_7304_1 // f16_mul_rd.tv line 7498 7703_3801_7304_01 1.01100000011 x 2^14 * 1.00000000001 x 2^-1 = 1.01100000100 x 2^13
+37FE_3400_3CFF_28_2FFE_0 // f16_mul_rd.tv line 7998 37FE_3400_2FFE_00 1.01111111110 x 2^-2 * 1.00000000000 x 2^-2 = 1.01111111110 x 2^-4
+3800_2EFE_3CFF_28_2AFE_0 // f16_mul_rd.tv line 8498 3800_2EFE_2AFE_00 1.00000000000 x 2^-1 * 1.01011111110 x 2^-4 = 1.01011111110 x 2^-5
+// Skipped denorm f16_mul_rd.tv line 8998 B0FC_03FE_80A0_03 -1.00011111100 x 2^-3 * Denorm = -Denorm
+3801_FFFF_3CFF_28_FFFF_0 // f16_mul_rd.tv line 9498 3801_FFFF_FFFF_00 1.00000000001 x 2^-1 * NaN = NaN
+3BFF_AB04_3CFF_28_AB04_1 // f16_mul_rd.tv line 9998 3BFF_AB04_AB04_01 1.01111111111 x 2^-1 * -1.01100000100 x 2^-5 = -1.01100000100 x 2^-5
+AD11_E801_3CFF_28_5912_1 // f16_mul_rd.tv line 10498 AD11_E801_5912_01 -1.00100010001 x 2^-4 * -1.00000000001 x 2^11 = 1.00100010010 x 2^7
+3C00_C400_3CFF_28_C400_0 // f16_mul_rd.tv line 10998 3C00_C400_C400_00 1.00000000000 x 2^0 * -1.00000000000 x 2^2 = -1.00000000000 x 2^2
+3C01_0BFD_3CFF_28_0BFE_1 // f16_mul_rd.tv line 11498 3C01_0BFD_0BFE_01 1.00000000001 x 2^0 * 1.01111111101 x 2^-13 = 1.01111111110 x 2^-13
+4FDE_BBFE_3CFF_28_CFDD_1 // f16_mul_rd.tv line 11998 4FDE_BBFE_CFDD_01 1.01111011110 x 2^4 * -1.01111111110 x 2^-1 = -1.01111011101 x 2^4
+3FFE_B7FF_3CFF_28_BBFE_1 // f16_mul_rd.tv line 12498 3FFE_B7FF_BBFE_01 1.01111111110 x 2^0 * -1.01111111111 x 2^-2 = -1.01111111110 x 2^-1
+4000_1008_3CFF_28_1408_0 // f16_mul_rd.tv line 12998 4000_1008_1408_00 1.00000000000 x 2^1 * 1.00000001000 x 2^-11 = 1.00000001000 x 2^-10
+C64C_8401_3CFF_28_0E4D_1 // f16_mul_rd.tv line 13498 C64C_8401_0E4D_01 -1.01001001100 x 2^2 * -1.00000000001 x 2^-14 = 1.01001001101 x 2^-12
+// Skipped denorm f16_mul_rd.tv line 13998 43FF_8000_8000_00 1.01111111111 x 2^1 * -Denorm = -Denorm
+43FE_2E03_3CFF_28_3601_1 // f16_mul_rd.tv line 14498 43FE_2E03_3601_01 1.01111111110 x 2^1 * 1.01000000011 x 2^-4 = 1.01000000001 x 2^-2
+265F_6BFE_3CFF_28_565D_1 // f16_mul_rd.tv line 14998 265F_6BFE_565D_01 1.01001011111 x 2^-6 * 1.01111111110 x 2^11 = 1.01001011101 x 2^6
+4401_47FF_3CFF_28_5000_1 // f16_mul_rd.tv line 15498 4401_47FF_5000_01 1.00000000001 x 2^2 * 1.01111111111 x 2^2 = 1.00000000000 x 2^5
+47FF_F8C0_3CFF_28_FC00_5 // f16_mul_rd.tv line 15998 47FF_F8C0_FC00_05 1.01111111111 x 2^2 * -1.00011000000 x 2^15 = -INF
+23CF_3C01_3CFF_28_23D0_1 // f16_mul_rd.tv line 16498 23CF_3C01_23D0_01 1.01111001111 x 2^-7 * 1.00000000001 x 2^0 = 1.01111010000 x 2^-7
+6800_3800_3CFF_28_6400_0 // f16_mul_rd.tv line 16998 6800_3800_6400_00 1.00000000000 x 2^11 * 1.00000000000 x 2^-1 = 1.00000000000 x 2^10
+6801_3B7A_3CFF_28_677B_1 // f16_mul_rd.tv line 17498 6801_3B7A_677B_01 1.00000000001 x 2^11 * 1.01101111010 x 2^-1 = 1.01101111011 x 2^10
+90C9_07FE_3CFF_28_8002_3 // f16_mul_rd.tv line 17998 90C9_07FE_8002_03 -1.00011001001 x 2^-11 * 1.01111111110 x 2^-14 = -Denorm
+// Skipped denorm f16_mul_rd.tv line 18498 6BFE_03FF_33FC_01 1.01111111110 x 2^11 * Denorm = 1.01111111100 x 2^-3
+6BFE_4C21_3CFF_28_7BFF_5 // f16_mul_rd.tv line 18998 6BFE_4C21_7BFF_05 1.01111111110 x 2^11 * 1.00000100001 x 2^4 = 1.01111111111 x 2^15
+BFDC_F801_3CFF_28_7BDD_1 // f16_mul_rd.tv line 19498 BFDC_F801_7BDD_01 -1.01111011100 x 2^0 * -1.00000000001 x 2^15 = 1.01111011101 x 2^15
+7801_E800_3CFF_28_FC00_5 // f16_mul_rd.tv line 19998 7801_E800_FC00_05 1.00000000001 x 2^15 * -1.00000000000 x 2^11 = -INF
+7BFF_5CFB_3CFF_28_7BFF_5 // f16_mul_rd.tv line 20498 7BFF_5CFB_7BFF_05 1.01111111111 x 2^15 * 1.00011111011 x 2^8 = 1.01111111111 x 2^15
+050F_BFFE_3CFF_28_890E_1 // f16_mul_rd.tv line 20998 050F_BFFE_890E_01 1.00100001111 x 2^-14 * -1.01111111110 x 2^0 = -1.00100001110 x 2^-13
+7C00_BBFF_3CFF_28_FC00_0 // f16_mul_rd.tv line 21498 7C00_BBFF_FC00_00 INF * -1.01111111111 x 2^-1 = -INF
+7C01_EBBE_3CFF_28_7E01_0 // f16_mul_rd.tv line 21998 7C01_EBBE_7E01_10 NaN * -1.01110111110 x 2^11 = NaN
+C3C3_9001_3CFF_28_17C4_1 // f16_mul_rd.tv line 22498 C3C3_9001_17C4_01 -1.01111000011 x 2^1 * -1.00000000001 x 2^-11 = 1.01111000100 x 2^-10
+7FFE_8400_3CFF_28_7FFE_0 // f16_mul_rd.tv line 22998 7FFE_8400_7FFE_00 NaN * -1.00000000000 x 2^-14 = NaN
+// Skipped denorm f16_mul_rd.tv line 23498 8000_C475_0000_00 -Denorm * -1.00001110101 x 2^2 = 0
+C80C_7BFE_3CFF_28_FC00_5 // f16_mul_rd.tv line 23998 C80C_7BFE_FC00_05 -1.00000001100 x 2^3 * 1.01111111110 x 2^15 = -INF
+// Skipped denorm f16_mul_rd.tv line 24498 83FF_6BFF_B3FE_01 -Denorm * 1.01111111111 x 2^11 = -1.01111111110 x 2^-3
+// Skipped denorm f16_mul_rd.tv line 24998 83FE_BA31_0316_03 -Denorm * -1.01000110001 x 2^-1 = Denorm
+4A3F_4001_3CFF_28_4E40_1 // f16_mul_rd.tv line 25498 4A3F_4001_4E40_01 1.01000111111 x 2^3 * 1.00000000001 x 2^1 = 1.01001000000 x 2^4
+8401_3C00_3CFF_28_8401_0 // f16_mul_rd.tv line 25998 8401_3C00_8401_00 -1.00000000001 x 2^-14 * 1.00000000000 x 2^0 = -1.00000000001 x 2^-14
+87FF_4827_3CFF_28_9427_1 // f16_mul_rd.tv line 26498 87FF_4827_9427_01 -1.01111111111 x 2^-14 * 1.00000100111 x 2^3 = -1.00000100111 x 2^-10
+37EB_13FE_3CFF_28_0FE9_1 // f16_mul_rd.tv line 26998 37EB_13FE_0FE9_01 1.01111101011 x 2^-2 * 1.01111111110 x 2^-11 = 1.01111101001 x 2^-12
+9000_07FF_3CFF_28_8001_3 // f16_mul_rd.tv line 27498 9000_07FF_8001_03 -1.00000000000 x 2^-11 * 1.01111111111 x 2^-14 = -Denorm
+9001_A23E_3CFF_28_0063_3 // f16_mul_rd.tv line 27998 9001_A23E_0063_03 -1.00000000001 x 2^-11 * -1.01000111110 x 2^-7 = Denorm
+1357_FC01_3CFF_28_FE01_0 // f16_mul_rd.tv line 28498 1357_FC01_FE01_10 1.01101010111 x 2^-11 * NaN = NaN
+93FF_F800_3CFF_28_4FFF_0 // f16_mul_rd.tv line 28998 93FF_F800_4FFF_00 -1.01111111111 x 2^-11 * -1.00000000000 x 2^15 = 1.01111111111 x 2^4
+93FE_633F_3CFF_28_BB3E_1 // f16_mul_rd.tv line 29498 93FE_633F_BB3E_01 -1.01111111110 x 2^-11 * 1.01100111111 x 2^9 = -1.01100111110 x 2^-1
+8B6F_C3FE_3CFF_28_136D_1 // f16_mul_rd.tv line 29998 8B6F_C3FE_136D_01 -1.01101101111 x 2^-13 * -1.01111111110 x 2^1 = 1.01101101101 x 2^-11
+B401_BFFF_3CFF_28_3800_1 // f16_mul_rd.tv line 30498 B401_BFFF_3800_01 -1.00000000001 x 2^-2 * -1.01111111111 x 2^0 = 1.00000000000 x 2^-1
+B7FF_BCC0_3CFF_28_38BF_1 // f16_mul_rd.tv line 30998 B7FF_BCC0_38BF_01 -1.01111111111 x 2^-2 * -1.00011000000 x 2^0 = 1.00010111111 x 2^-1
+4FF9_B401_3CFF_28_C7FB_1 // f16_mul_rd.tv line 31498 4FF9_B401_C7FB_01 1.01111111001 x 2^4 * -1.00000000001 x 2^-2 = -1.01111111011 x 2^2
+B800_9000_3CFF_28_0C00_0 // f16_mul_rd.tv line 31998 B800_9000_0C00_00 -1.00000000000 x 2^-1 * -1.00000000000 x 2^-11 = 1.00000000000 x 2^-12
+B801_0B3B_3CFF_28_873D_1 // f16_mul_rd.tv line 32498 B801_0B3B_873D_01 -1.00000000001 x 2^-1 * 1.01100111011 x 2^-13 = -1.01100111101 x 2^-14
+B4C0_7FFE_3CFF_28_7FFE_0 // f16_mul_rd.tv line 32998 B4C0_7FFE_7FFE_00 -1.00011000000 x 2^-2 * NaN = NaN
+BBFE_7BFF_3CFF_28_FBFE_1 // f16_mul_rd.tv line 33498 BBFE_7BFF_FBFE_01 -1.01111111110 x 2^-1 * 1.01111111111 x 2^15 = -1.01111111110 x 2^15
+BC00_FE3F_3CFF_28_FE3F_0 // f16_mul_rd.tv line 33998 BC00_FE3F_FE3F_00 -1.00000000000 x 2^0 * NaN = NaN
+6BFF_4401_3CFF_28_7400_1 // f16_mul_rd.tv line 34498 6BFF_4401_7400_01 1.01111111111 x 2^11 * 1.00000000001 x 2^2 = 1.00000000000 x 2^14
+BFFF_4000_3CFF_28_C3FF_0 // f16_mul_rd.tv line 34998 BFFF_4000_C3FF_00 -1.01111111111 x 2^0 * 1.00000000000 x 2^1 = -1.01111111111 x 2^1
+BFFE_040E_3CFF_28_880D_1 // f16_mul_rd.tv line 35498 BFFE_040E_880D_01 -1.01111111110 x 2^0 * 1.00000001110 x 2^-14 = -1.00000001101 x 2^-13
+C81F_37FE_3CFF_28_C41E_1 // f16_mul_rd.tv line 35998 C81F_37FE_C41E_01 -1.00000011111 x 2^3 * 1.01111111110 x 2^-2 = -1.00000011110 x 2^2
+C001_13FF_3CFF_28_9801_1 // f16_mul_rd.tv line 36498 C001_13FF_9801_01 -1.00000000001 x 2^1 * 1.01111111111 x 2^-11 = -1.00000000001 x 2^-9
+C3FF_C11E_3CFF_28_491D_1 // f16_mul_rd.tv line 36998 C3FF_C11E_491D_01 -1.01111111111 x 2^1 * -1.00100011110 x 2^1 = 1.00100011101 x 2^3
+// Skipped denorm f16_mul_rd.tv line 37498 D527_0001_8053_03 -1.00100100111 x 2^6 * Denorm = -Denorm
+C3FE_FC00_3CFF_28_7C00_0 // f16_mul_rd.tv line 37998 C3FE_FC00_7C00_00 -1.01111111110 x 2^1 * -INF = INF
+C400_893F_3CFF_28_113F_0 // f16_mul_rd.tv line 38498 C400_893F_113F_00 -1.00000000000 x 2^2 * -1.00100111111 x 2^-13 = 1.00100111111 x 2^-11
+0881_C7FE_3CFF_28_9480_1 // f16_mul_rd.tv line 38998 0881_C7FE_9480_01 1.00010000001 x 2^-13 * -1.01111111110 x 2^2 = -1.00010000000 x 2^-10
+C7FF_C3FF_3CFF_28_4FFE_1 // f16_mul_rd.tv line 39498 C7FF_C3FF_4FFE_01 -1.01111111111 x 2^2 * -1.01111111111 x 2^1 = 1.01111111110 x 2^4
+C7FE_8A7F_3CFF_28_167D_1 // f16_mul_rd.tv line 39998 C7FE_8A7F_167D_01 -1.01111111110 x 2^2 * -1.01001111111 x 2^-13 = 1.01001111101 x 2^-10
+7BD8_B801_3CFF_28_F7DA_1 // f16_mul_rd.tv line 40498 7BD8_B801_F7DA_01 1.01111011000 x 2^15 * -1.00000000001 x 2^-1 = -1.01111011010 x 2^14
+E801_B400_3CFF_28_6001_0 // f16_mul_rd.tv line 40998 E801_B400_6001_00 -1.00000000001 x 2^11 * -1.00000000000 x 2^-2 = 1.00000000001 x 2^9
+EBFF_BDFF_3CFF_28_6DFE_1 // f16_mul_rd.tv line 41498 EBFF_BDFF_6DFE_01 -1.01111111111 x 2^11 * -1.00111111111 x 2^0 = 1.00111111110 x 2^12
+// Skipped denorm f16_mul_rd.tv line 41998 D4FF_83FE_1CFC_01 -1.00011111111 x 2^6 * -Denorm = 1.00011111100 x 2^-8
+F800_7FFF_3CFF_28_7FFF_0 // f16_mul_rd.tv line 42498 F800_7FFF_7FFF_00 -1.00000000000 x 2^15 * NaN = NaN
+F801_7BC8_3CFF_28_FC00_5 // f16_mul_rd.tv line 42998 F801_7BC8_FC00_05 -1.00000000001 x 2^15 * 1.01111001000 x 2^15 = -INF
+A020_6801_3CFF_28_CC22_1 // f16_mul_rd.tv line 43498 A020_6801_CC22_01 -1.00000100000 x 2^-7 * 1.00000000001 x 2^11 = -1.00000100010 x 2^4
+FBFE_4400_3CFF_28_FC00_5 // f16_mul_rd.tv line 43998 FBFE_4400_FC00_05 -1.01111111110 x 2^15 * 1.00000000000 x 2^2 = -INF
+FC00_07C6_3CFF_28_FC00_0 // f16_mul_rd.tv line 44498 FC00_07C6_FC00_00 -INF * 1.01111000110 x 2^-14 = -INF
+BA33_3BFE_3CFF_28_BA32_1 // f16_mul_rd.tv line 44998 BA33_3BFE_BA32_01 -1.01000110011 x 2^-1 * 1.01111111110 x 2^-1 = -1.01000110010 x 2^-1
+FFFF_37FF_3CFF_28_FFFF_0 // f16_mul_rd.tv line 45498 FFFF_37FF_FFFF_00 NaN * 1.01111111111 x 2^-2 = NaN
+FFFE_CBFF_3CFF_28_FFFE_0 // f16_mul_rd.tv line 45998 FFFE_CBFF_FFFE_00 NaN * -1.01111111111 x 2^3 = NaN
+
+////////// Testcases from f16_mul_ru.tv of type mul rounding mode 3
+3C2F_63C0_3CFF_38_640E_1 // f16_mul_ru.tv line 497 3C2F_63C0_640E_01 1.00000101111 x 2^0 * 1.01111000000 x 2^9 = 1.00000001110 x 2^10
+F843_4F90_3CFF_38_FBFF_5 // f16_mul_ru.tv line 997 F843_4F90_FBFF_05 -1.00001000011 x 2^15 * 1.01110010000 x 2^4 = -1.01111111111 x 2^15
+4B6F_3810_3CFF_38_478D_1 // f16_mul_ru.tv line 1497 4B6F_3810_478D_01 1.01101101111 x 2^3 * 1.00000010000 x 2^-1 = 1.01110001101 x 2^2
+BBC0_7FF3_3CFF_38_7FF3_0 // f16_mul_ru.tv line 1997 BBC0_7FF3_7FF3_00 -1.01111000000 x 2^-1 * NaN = NaN
+// Skipped denorm f16_mul_ru.tv line 2497 80BF_FAE3_3924_01 -Denorm * -1.01011100011 x 2^15 = 1.00100100100 x 2^-1
+9F24_B7D3_3CFF_38_1AFC_1 // f16_mul_ru.tv line 2997 9F24_B7D3_1AFC_01 -1.01100100100 x 2^-8 * -1.01111010011 x 2^-2 = 1.01011111100 x 2^-9
+B564_4A3C_3CFF_38_C433_1 // f16_mul_ru.tv line 3497 B564_4A3C_C433_01 -1.00101100100 x 2^-2 * 1.01000111100 x 2^3 = -1.00000110011 x 2^2
+D827_AFFF_3CFF_38_4C27_1 // f16_mul_ru.tv line 3997 D827_AFFF_4C27_01 -1.00000100111 x 2^7 * -1.01111111111 x 2^-4 = 1.00000100111 x 2^4
+B740_CFF0_3CFF_38_4B32_1 // f16_mul_ru.tv line 4497 B740_CFF0_4B32_01 -1.01101000000 x 2^-2 * -1.01111110000 x 2^4 = 1.01100110010 x 2^3
+// Skipped denorm f16_mul_ru.tv line 4997 80BF_AC1B_000D_03 -Denorm * -1.00000011011 x 2^-4 = Denorm
+76A1_3409_3CFF_38_6EB0_1 // f16_mul_ru.tv line 5497 76A1_3409_6EB0_01 1.01010100001 x 2^14 * 1.00000001001 x 2^-2 = 1.01010110000 x 2^12
+4B04_C466_3CFF_38_D3B6_1 // f16_mul_ru.tv line 5997 4B04_C466_D3B6_01 1.01100000100 x 2^3 * -1.00001100110 x 2^2 = -1.01110110110 x 2^5
+8AFF_24BE_3CFF_38_8042_3 // f16_mul_ru.tv line 6497 8AFF_24BE_8042_03 -1.01011111111 x 2^-13 * 1.00010111110 x 2^-6 = -Denorm
+7CCC_CADE_3CFF_38_7ECC_0 // f16_mul_ru.tv line 6997 7CCC_CADE_7ECC_10 NaN * -1.01011011110 x 2^3 = NaN
+477F_47DD_3CFF_38_535F_1 // f16_mul_ru.tv line 7497 477F_47DD_535F_01 1.01101111111 x 2^2 * 1.01111011101 x 2^2 = 1.01101011111 x 2^5
+539E_B80E_3CFF_38_CFB8_1 // f16_mul_ru.tv line 7997 539E_B80E_CFB8_01 1.01110011110 x 2^5 * -1.00000001110 x 2^-1 = -1.01110111000 x 2^4
+0BAE_B1F3_3CFF_38_82DB_3 // f16_mul_ru.tv line 8497 0BAE_B1F3_82DB_03 1.01110101110 x 2^-13 * -1.00111110011 x 2^-3 = -Denorm
+582F_7FDA_3CFF_38_7FDA_0 // f16_mul_ru.tv line 8997 582F_7FDA_7FDA_00 1.00000101111 x 2^7 * NaN = NaN
+CC04_997F_3CFF_38_2985_1 // f16_mul_ru.tv line 9497 CC04_997F_2985_01 -1.00000000100 x 2^4 * -1.00101111111 x 2^-9 = 1.00110000101 x 2^-5
+6BBF_8C1E_3CFF_38_BBF9_1 // f16_mul_ru.tv line 9997 6BBF_8C1E_BBF9_01 1.01110111111 x 2^11 * -1.00000011110 x 2^-12 = -1.01111111001 x 2^-1
+BF1D_4800_3CFF_38_CB1D_0 // f16_mul_ru.tv line 10497 BF1D_4800_CB1D_00 -1.01100011101 x 2^0 * 1.00000000000 x 2^3 = -1.01100011101 x 2^3
+1A9C_0B02_3CFF_38_000C_3 // f16_mul_ru.tv line 10997 1A9C_0B02_000C_03 1.01010011100 x 2^-9 * 1.01100000010 x 2^-13 = Denorm
+DB80_CCFF_3CFF_38_6CB0_1 // f16_mul_ru.tv line 11497 DB80_CCFF_6CB0_01 -1.01110000000 x 2^7 * -1.00011111111 x 2^4 = 1.00010110000 x 2^12
+FAFE_7CE0_3CFF_38_7EE0_0 // f16_mul_ru.tv line 11997 FAFE_7CE0_7EE0_10 -1.01011111110 x 2^15 * NaN = NaN
+2FFF_43EF_3CFF_38_37EF_1 // f16_mul_ru.tv line 12497 2FFF_43EF_37EF_01 1.01111111111 x 2^-4 * 1.01111101111 x 2^1 = 1.01111101111 x 2^-2
+C602_D33F_3CFF_38_5D72_1 // f16_mul_ru.tv line 12997 C602_D33F_5D72_01 -1.01000000010 x 2^2 * -1.01100111111 x 2^5 = 1.00101110010 x 2^8
+C7BA_BC08_3CFF_38_47CA_1 // f16_mul_ru.tv line 13497 C7BA_BC08_47CA_01 -1.01110111010 x 2^2 * -1.00000001000 x 2^0 = 1.01111001010 x 2^2
+4CE0_93DF_3CFF_38_A4CB_1 // f16_mul_ru.tv line 13997 4CE0_93DF_A4CB_01 1.00011100000 x 2^4 * -1.01111011111 x 2^-11 = -1.00011001011 x 2^-6
+3929_429E_3CFF_38_4045_1 // f16_mul_ru.tv line 14497 3929_429E_4045_01 1.00100101001 x 2^-1 * 1.01010011110 x 2^1 = 1.00001000101 x 2^1
+5CFC_EBBF_3CFF_38_FBFF_5 // f16_mul_ru.tv line 14997 5CFC_EBBF_FBFF_05 1.00011111100 x 2^8 * -1.01110111111 x 2^11 = -1.01111111111 x 2^15
+C7F8_EFF4_3CFF_38_7BED_1 // f16_mul_ru.tv line 15497 C7F8_EFF4_7BED_01 -1.01111111000 x 2^2 * -1.01111110100 x 2^12 = 1.01111101101 x 2^15
+3BC7_BF6C_3CFF_38_BF37_1 // f16_mul_ru.tv line 15997 3BC7_BF6C_BF37_01 1.01111000111 x 2^-1 * -1.01101101100 x 2^0 = -1.01100110111 x 2^0
+// Skipped denorm f16_mul_ru.tv line 16497 8100_920C_0001_03 -Denorm * -1.01000001100 x 2^-11 = Denorm
+6827_B1FB_3CFF_38_DE35_1 // f16_mul_ru.tv line 16997 6827_B1FB_DE35_01 1.00000100111 x 2^11 * -1.00111111011 x 2^-3 = -1.01000110101 x 2^8
+// Skipped denorm f16_mul_ru.tv line 17497 C3FE_01FC_87EE_01 -1.01111111110 x 2^1 * Denorm = -1.01111101110 x 2^-14
+B903_CBFC_3CFF_38_4901_1 // f16_mul_ru.tv line 17997 B903_CBFC_4901_01 -1.00100000011 x 2^-1 * -1.01111111100 x 2^3 = 1.00100000001 x 2^3
+F77B_3640_3CFF_38_F1D8_1 // f16_mul_ru.tv line 18497 F77B_3640_F1D8_01 -1.01101111011 x 2^14 * 1.01001000000 x 2^-2 = -1.00111011000 x 2^13
+4FBF_AFF0_3CFF_38_C3AF_1 // f16_mul_ru.tv line 18997 4FBF_AFF0_C3AF_01 1.01110111111 x 2^4 * -1.01111110000 x 2^-4 = -1.01110101111 x 2^1
+793D_BFE0_3CFF_38_FBFF_5 // f16_mul_ru.tv line 19497 793D_BFE0_FBFF_05 1.00100111101 x 2^15 * -1.01111100000 x 2^0 = -1.01111111111 x 2^15
+B440_58FE_3CFF_38_D14D_1 // f16_mul_ru.tv line 19997 B440_58FE_D14D_01 -1.00001000000 x 2^-2 * 1.00011111110 x 2^7 = -1.00101001101 x 2^5
+EB76_B37C_3CFF_38_62FB_1 // f16_mul_ru.tv line 20497 EB76_B37C_62FB_01 -1.01101110110 x 2^11 * -1.01101111100 x 2^-3 = 1.01011111011 x 2^9
+887B_34C7_3CFF_38_82AC_3 // f16_mul_ru.tv line 20997 887B_34C7_82AC_03 -1.00001111011 x 2^-13 * 1.00011000111 x 2^-2 = -Denorm
+BB34_BC90_3CFF_38_3C1C_1 // f16_mul_ru.tv line 21497 BB34_BC90_3C1C_01 -1.01100110100 x 2^-1 * -1.00010010000 x 2^0 = 1.00000011100 x 2^0
+4003_2FFB_3CFF_38_3401_1 // f16_mul_ru.tv line 21997 4003_2FFB_3401_01 1.00000000011 x 2^1 * 1.01111111011 x 2^-4 = 1.00000000001 x 2^-2
+A524_4B03_3CFF_38_B481_1 // f16_mul_ru.tv line 22497 A524_4B03_B481_01 -1.00100100100 x 2^-6 * 1.01100000011 x 2^3 = -1.00010000001 x 2^-2
+EA2F_E40C_3CFF_38_7C00_5 // f16_mul_ru.tv line 22997 EA2F_E40C_7C00_05 -1.01000101111 x 2^11 * -1.00000001100 x 2^10 = INF
+BEB4_481F_3CFF_38_CAE7_1 // f16_mul_ru.tv line 23497 BEB4_481F_CAE7_01 -1.01010110100 x 2^0 * 1.00000011111 x 2^3 = -1.01011100111 x 2^3
+36F6_4FF3_3CFF_38_4AEB_1 // f16_mul_ru.tv line 23997 36F6_4FF3_4AEB_01 1.01011110110 x 2^-2 * 1.01111110011 x 2^4 = 1.01011101011 x 2^3
+9F1F_B478_3CFF_38_17F5_1 // f16_mul_ru.tv line 24497 9F1F_B478_17F5_01 -1.01100011111 x 2^-8 * -1.00001111000 x 2^-2 = 1.01111110101 x 2^-10
+1C0A_343F_3CFF_38_144A_1 // f16_mul_ru.tv line 24997 1C0A_343F_144A_01 1.00000001010 x 2^-8 * 1.00000111111 x 2^-2 = 1.00001001010 x 2^-10
+AF61_C7C0_3CFF_38_3B26_1 // f16_mul_ru.tv line 25497 AF61_C7C0_3B26_01 -1.01101100001 x 2^-4 * -1.01111000000 x 2^2 = 1.01100100110 x 2^-1
+D07E_103C_3CFF_38_A4C1_1 // f16_mul_ru.tv line 25997 D07E_103C_A4C1_01 -1.00001111110 x 2^5 * 1.00000111100 x 2^-11 = -1.00011000001 x 2^-6
+9060_FF78_3CFF_38_FF78_0 // f16_mul_ru.tv line 26497 9060_FF78_FF78_00 -1.00001100000 x 2^-11 * NaN = NaN
+B620_C003_3CFF_38_3A25_1 // f16_mul_ru.tv line 26997 B620_C003_3A25_01 -1.01000100000 x 2^-2 * -1.00000000011 x 2^1 = 1.01000100101 x 2^-1
+A82F_8A02_3CFF_38_0065_3 // f16_mul_ru.tv line 27497 A82F_8A02_0065_03 -1.00000101111 x 2^-5 * -1.01000000010 x 2^-13 = Denorm
+437A_A415_3CFF_38_ABA1_1 // f16_mul_ru.tv line 27997 437A_A415_ABA1_01 1.01101111010 x 2^1 * -1.00000010101 x 2^-6 = -1.01110100001 x 2^-5
+2FD7_BD4F_3CFF_38_B133_1 // f16_mul_ru.tv line 28497 2FD7_BD4F_B133_01 1.01111010111 x 2^-4 * -1.00101001111 x 2^0 = -1.00100110011 x 2^-3
+7C3A_B071_3CFF_38_7E3A_0 // f16_mul_ru.tv line 28997 7C3A_B071_7E3A_10 NaN * -1.00001110001 x 2^-3 = NaN
+FC01_BBA2_3CFF_38_FE01_0 // f16_mul_ru.tv line 29497 FC01_BBA2_FE01_10 NaN * -1.01110100010 x 2^-1 = NaN
+7BF3_4804_3CFF_38_7C00_5 // f16_mul_ru.tv line 29997 7BF3_4804_7C00_05 1.01111110011 x 2^15 * 1.00000000100 x 2^3 = INF
+3907_07BF_3CFF_38_04DF_1 // f16_mul_ru.tv line 30497 3907_07BF_04DF_01 1.00100000111 x 2^-1 * 1.01110111111 x 2^-14 = 1.00011011111 x 2^-14
+3FBE_53BF_3CFF_38_5780_1 // f16_mul_ru.tv line 30997 3FBE_53BF_5780_01 1.01110111110 x 2^0 * 1.01110111111 x 2^5 = 1.01110000000 x 2^6
+// Skipped denorm f16_mul_ru.tv line 31497 80C0_3C02_80C0_03 -Denorm * 1.00000000010 x 2^0 = -Denorm
+BC1E_840E_3CFF_38_042D_1 // f16_mul_ru.tv line 31997 BC1E_840E_042D_01 -1.00000011110 x 2^0 * -1.00000001110 x 2^-14 = 1.00000101101 x 2^-14
+// Skipped denorm f16_mul_ru.tv line 32497 6842_03B6_2FE7_01 1.00001000010 x 2^11 * Denorm = 1.01111100111 x 2^-4
+86C8_3818_3CFF_38_8378_3 // f16_mul_ru.tv line 32997 86C8_3818_8378_03 -1.01011001000 x 2^-14 * 1.00000011000 x 2^-1 = -Denorm
+4842_CB79_3CFF_38_D7F4_1 // f16_mul_ru.tv line 33497 4842_CB79_D7F4_01 1.00001000010 x 2^3 * -1.01101111001 x 2^3 = -1.01111110100 x 2^6
+13E8_DC87_3CFF_38_B479_1 // f16_mul_ru.tv line 33997 13E8_DC87_B479_01 1.01111101000 x 2^-11 * -1.00010000111 x 2^8 = -1.00001111001 x 2^-2
+B8F0_EC3B_3CFF_38_6939_1 // f16_mul_ru.tv line 34497 B8F0_EC3B_6939_01 -1.00011110000 x 2^-1 * -1.00000111011 x 2^12 = 1.00100111001 x 2^11
+C5C0_8B1F_3CFF_38_151F_1 // f16_mul_ru.tv line 34997 C5C0_8B1F_151F_01 -1.00111000000 x 2^2 * -1.01100011111 x 2^-13 = 1.00100011111 x 2^-10
+C901_B0C9_3CFF_38_3DFD_1 // f16_mul_ru.tv line 35497 C901_B0C9_3DFD_01 -1.00100000001 x 2^3 * -1.00011001001 x 2^-3 = 1.00111111101 x 2^0
+340F_A5FE_3CFF_38_9E14_1 // f16_mul_ru.tv line 35997 340F_A5FE_9E14_01 1.00000001111 x 2^-2 * -1.00111111110 x 2^-6 = -1.01000010100 x 2^-8
+1A1F_5F5E_3CFF_38_3DA4_1 // f16_mul_ru.tv line 36497 1A1F_5F5E_3DA4_01 1.01000011111 x 2^-9 * 1.01101011110 x 2^8 = 1.00110100100 x 2^0
+DEC5_307F_3CFF_38_D39B_1 // f16_mul_ru.tv line 36997 DEC5_307F_D39B_01 -1.01011000101 x 2^8 * 1.00001111111 x 2^-3 = -1.01110011011 x 2^5
+407A_6DE0_3CFF_38_7294_1 // f16_mul_ru.tv line 37497 407A_6DE0_7294_01 1.00001111010 x 2^1 * 1.00111100000 x 2^12 = 1.01010010100 x 2^13
+7BDF_32BF_3CFF_38_72A4_1 // f16_mul_ru.tv line 37997 7BDF_32BF_72A4_01 1.01111011111 x 2^15 * 1.01010111111 x 2^-3 = 1.01010100100 x 2^13
+B7F2_8A31_3CFF_38_0627_1 // f16_mul_ru.tv line 38497 B7F2_8A31_0627_01 -1.01111110010 x 2^-2 * -1.01000110001 x 2^-13 = 1.01000100111 x 2^-14
+337F_43EB_3CFF_38_3B6C_1 // f16_mul_ru.tv line 38997 337F_43EB_3B6C_01 1.01101111111 x 2^-3 * 1.01111101011 x 2^1 = 1.01101101100 x 2^-1
+B3AE_6B3F_3CFF_38_E2F4_1 // f16_mul_ru.tv line 39497 B3AE_6B3F_E2F4_01 -1.01110101110 x 2^-3 * 1.01100111111 x 2^11 = -1.01011110100 x 2^9
+BFFF_3AFF_3CFF_38_BEFE_1 // f16_mul_ru.tv line 39997 BFFF_3AFF_BEFE_01 -1.01111111111 x 2^0 * 1.01011111111 x 2^-1 = -1.01011111110 x 2^0
+583E_BBAC_3CFF_38_D811_1 // f16_mul_ru.tv line 40497 583E_BBAC_D811_01 1.00000111110 x 2^7 * -1.01110101100 x 2^-1 = -1.00000010001 x 2^7
+A7FF_A3CD_3CFF_38_0FCD_1 // f16_mul_ru.tv line 40997 A7FF_A3CD_0FCD_01 -1.01111111111 x 2^-6 * -1.01111001101 x 2^-7 = 1.01111001101 x 2^-12
+2E38_FBE7_3CFF_38_EE24_1 // f16_mul_ru.tv line 41497 2E38_FBE7_EE24_01 1.01000111000 x 2^-4 * -1.01111100111 x 2^15 = -1.01000100100 x 2^12
+D844_C3FA_3CFF_38_6041_1 // f16_mul_ru.tv line 41997 D844_C3FA_6041_01 -1.00001000100 x 2^7 * -1.01111111010 x 2^1 = 1.00001000001 x 2^9
+2C0B_BBE7_3CFF_38_ABFC_1 // f16_mul_ru.tv line 42497 2C0B_BBE7_ABFC_01 1.00000001011 x 2^-4 * -1.01111100111 x 2^-1 = -1.01111111100 x 2^-5
+B73E_47E0_3CFF_38_C321_1 // f16_mul_ru.tv line 42997 B73E_47E0_C321_01 -1.01100111110 x 2^-2 * 1.01111100000 x 2^2 = -1.01100100001 x 2^1
+4FEA_D3A7_3CFF_38_E791_1 // f16_mul_ru.tv line 43497 4FEA_D3A7_E791_01 1.01111101010 x 2^4 * -1.01110100111 x 2^5 = -1.01110010001 x 2^10
+FB3E_43F9_3CFF_38_FBFF_5 // f16_mul_ru.tv line 43997 FB3E_43F9_FBFF_05 -1.01100111110 x 2^15 * 1.01111111001 x 2^1 = -1.01111111111 x 2^15
+B4DF_BBFE_3CFF_38_34DE_1 // f16_mul_ru.tv line 44497 B4DF_BBFE_34DE_01 -1.00011011111 x 2^-2 * -1.01111111110 x 2^-1 = 1.00011011110 x 2^-2
+07B9_B508_3CFF_38_826D_3 // f16_mul_ru.tv line 44997 07B9_B508_826D_03 1.01110111001 x 2^-14 * -1.00100001000 x 2^-2 = -Denorm
+8575_B405_3CFF_38_015F_3 // f16_mul_ru.tv line 45497 8575_B405_015F_03 -1.00101110101 x 2^-14 * -1.00000000101 x 2^-2 = Denorm
+6ADE_B440_3CFF_38_E34B_1 // f16_mul_ru.tv line 45997 6ADE_B440_E34B_01 1.01011011110 x 2^11 * -1.00001000000 x 2^-2 = -1.01101001011 x 2^9
+
+////////// Testcases from f16_mul_rne.tv of type mul rounding mode 1
+EB08_AD2E_3CFF_18_5C8D_1 // f16_mul_rne.tv line 499 EB08_AD2E_5C8D_01 -1.01100001000 x 2^11 * -1.00100101110 x 2^-4 = 1.00010001101 x 2^8
+CC83_6081_3CFF_18_F115_1 // f16_mul_rne.tv line 999 CC83_6081_F115_01 -1.00010000011 x 2^4 * 1.00010000001 x 2^9 = -1.00100010101 x 2^13
+E2EF_BF7C_3CFF_18_667D_1 // f16_mul_rne.tv line 1499 E2EF_BF7C_667D_01 -1.01011101111 x 2^9 * -1.01101111100 x 2^0 = 1.01001111101 x 2^10
+4F3E_7440_3CFF_18_7C00_5 // f16_mul_rne.tv line 1999 4F3E_7440_7C00_05 1.01100111110 x 2^4 * 1.00001000000 x 2^14 = INF
+3538_FC7F_3CFF_18_FE7F_0 // f16_mul_rne.tv line 2499 3538_FC7F_FE7F_10 1.00100111000 x 2^-2 * NaN = NaN
+CE7E_A80B_3CFF_18_3A90_1 // f16_mul_rne.tv line 2999 CE7E_A80B_3A90_01 -1.01001111110 x 2^4 * -1.00000001011 x 2^-5 = 1.01010010000 x 2^-1
+7BC3_93F6_3CFF_18_D3B9_1 // f16_mul_rne.tv line 3499 7BC3_93F6_D3B9_01 1.01111000011 x 2^15 * -1.01111110110 x 2^-11 = -1.01110111001 x 2^5
+F80D_2B7C_3CFF_18_E794_1 // f16_mul_rne.tv line 3999 F80D_2B7C_E794_01 -1.00000001101 x 2^15 * 1.01101111100 x 2^-5 = -1.01110010100 x 2^10
+8BE8_E2DA_3CFF_18_32C5_1 // f16_mul_rne.tv line 4499 8BE8_E2DA_32C5_01 -1.01111101000 x 2^-13 * -1.01011011010 x 2^9 = 1.01011000101 x 2^-3
+37EF_B089_3CFF_18_AC7F_1 // f16_mul_rne.tv line 4999 37EF_B089_AC7F_01 1.01111101111 x 2^-2 * -1.00010001001 x 2^-3 = -1.00001111111 x 2^-4
+17FF_577F_3CFF_18_337E_1 // f16_mul_rne.tv line 5499 17FF_577F_337E_01 1.01111111111 x 2^-10 * 1.01101111111 x 2^6 = 1.01101111110 x 2^-3
+30BE_CF03_3CFF_18_C428_1 // f16_mul_rne.tv line 5999 30BE_CF03_C428_01 1.00010111110 x 2^-3 * -1.01100000011 x 2^4 = -1.00000101000 x 2^2
+B41F_C5C1_3CFF_18_3DEE_1 // f16_mul_rne.tv line 6499 B41F_C5C1_3DEE_01 -1.00000011111 x 2^-2 * -1.00111000001 x 2^2 = 1.00111101110 x 2^0
+7DB3_B738_3CFF_18_7FB3_0 // f16_mul_rne.tv line 6999 7DB3_B738_7FB3_10 NaN * -1.01100111000 x 2^-2 = NaN
+BFD4_4811_3CFF_18_CBF5_1 // f16_mul_rne.tv line 7499 BFD4_4811_CBF5_01 -1.01111010100 x 2^0 * 1.00000010001 x 2^3 = -1.01111110101 x 2^3
+C643_541F_3CFF_18_DE74_1 // f16_mul_rne.tv line 7999 C643_541F_DE74_01 -1.01001000011 x 2^2 * 1.00000011111 x 2^6 = -1.01001110100 x 2^8
+47B7_AFEE_3CFF_18_BBA6_1 // f16_mul_rne.tv line 8499 47B7_AFEE_BBA6_01 1.01110110111 x 2^2 * -1.01111101110 x 2^-4 = -1.01110100110 x 2^-1
+F45E_B6FB_3CFF_18_6F9F_1 // f16_mul_rne.tv line 8999 F45E_B6FB_6F9F_01 -1.00001011110 x 2^14 * -1.01011111011 x 2^-2 = 1.01110011111 x 2^12
+7F9F_7C0A_3CFF_18_7F9F_0 // f16_mul_rne.tv line 9499 7F9F_7C0A_7F9F_10 NaN * NaN = NaN
+743C_37FE_3CFF_18_703B_1 // f16_mul_rne.tv line 9999 743C_37FE_703B_01 1.00000111100 x 2^14 * 1.01111111110 x 2^-2 = 1.00000111011 x 2^13
+// Skipped denorm f16_mul_rne.tv line 10499 03DB_3F03_06C2_01 Denorm * 1.01100000011 x 2^0 = 1.01011000010 x 2^-14
+5731_A009_3CFF_18_BB41_1 // f16_mul_rne.tv line 10999 5731_A009_BB41_01 1.01100110001 x 2^6 * -1.00000001001 x 2^-7 = -1.01101000001 x 2^-1
+2FBF_09FD_3CFF_18_0173_3 // f16_mul_rne.tv line 11499 2FBF_09FD_0173_03 1.01110111111 x 2^-4 * 1.00111111101 x 2^-13 = Denorm
+1013_4EFA_3CFF_18_231B_1 // f16_mul_rne.tv line 11999 1013_4EFA_231B_01 1.00000010011 x 2^-11 * 1.01011111010 x 2^4 = 1.01100011011 x 2^-7
+1082_14BE_3CFF_18_000B_3 // f16_mul_rne.tv line 12499 1082_14BE_000B_03 1.00010000010 x 2^-11 * 1.00010111110 x 2^-10 = Denorm
+3306_C00A_3CFF_18_B718_1 // f16_mul_rne.tv line 12999 3306_C00A_B718_01 1.01100000110 x 2^-3 * -1.00000001010 x 2^1 = -1.01100011000 x 2^-2
+4C10_06EE_3CFF_18_170A_1 // f16_mul_rne.tv line 13499 4C10_06EE_170A_01 1.00000010000 x 2^4 * 1.01011101110 x 2^-14 = 1.01100001010 x 2^-10
+C3E2_BFFE_3CFF_18_47E0_1 // f16_mul_rne.tv line 13999 C3E2_BFFE_47E0_01 -1.01111100010 x 2^1 * -1.01111111110 x 2^0 = 1.01111100000 x 2^2
+F844_570E_3CFF_18_FC00_5 // f16_mul_rne.tv line 14499 F844_570E_FC00_05 -1.00001000100 x 2^15 * 1.01100001110 x 2^6 = -INF
+C0FD_B403_3CFF_18_3901_1 // f16_mul_rne.tv line 14999 C0FD_B403_3901_01 -1.00011111101 x 2^1 * -1.00000000011 x 2^-2 = 1.00100000001 x 2^-1
+FEFE_84F9_3CFF_18_FEFE_0 // f16_mul_rne.tv line 15499 FEFE_84F9_FEFE_00 NaN * -1.00011111001 x 2^-14 = NaN
+// Skipped denorm f16_mul_rne.tv line 15999 0030_CC91_836D_03 Denorm * -1.00010010001 x 2^4 = -Denorm
+53C8_BB7A_3CFF_18_D346_1 // f16_mul_rne.tv line 16499 53C8_BB7A_D346_01 1.01111001000 x 2^5 * -1.01101111010 x 2^-1 = -1.01101000110 x 2^5
+2102_B42E_3CFF_18_993C_1 // f16_mul_rne.tv line 16999 2102_B42E_993C_01 1.00100000010 x 2^-7 * -1.00000101110 x 2^-2 = -1.00100111100 x 2^-9
+B782_FB15_3CFF_18_76A5_1 // f16_mul_rne.tv line 17499 B782_FB15_76A5_01 -1.01110000010 x 2^-2 * -1.01100010101 x 2^15 = 1.01010100101 x 2^14
+8423_CF98_3CFF_18_17DA_1 // f16_mul_rne.tv line 17999 8423_CF98_17DA_01 -1.00000100011 x 2^-14 * -1.01110011000 x 2^4 = 1.01111011010 x 2^-10
+3322_C566_3CFF_18_BCD0_1 // f16_mul_rne.tv line 18499 3322_C566_BCD0_01 1.01100100010 x 2^-3 * -1.00101100110 x 2^2 = -1.00011010000 x 2^0
+4FDC_07C7_3CFF_18_1BA4_1 // f16_mul_rne.tv line 18999 4FDC_07C7_1BA4_01 1.01111011100 x 2^4 * 1.01111000111 x 2^-14 = 1.01110100100 x 2^-9
+CBFE_C835_3CFF_18_5834_1 // f16_mul_rne.tv line 19499 CBFE_C835_5834_01 -1.01111111110 x 2^3 * -1.00000110101 x 2^3 = 1.00000110100 x 2^7
+27F6_F1C2_3CFF_18_DDBB_1 // f16_mul_rne.tv line 19999 27F6_F1C2_DDBB_01 1.01111110110 x 2^-6 * -1.00111000010 x 2^13 = -1.00110111011 x 2^8
+CA1F_4F6E_3CFF_18_DDAF_1 // f16_mul_rne.tv line 20499 CA1F_4F6E_DDAF_01 -1.01000011111 x 2^3 * 1.01101101110 x 2^4 = -1.00110101111 x 2^8
+477C_ABFF_3CFF_18_B77B_1 // f16_mul_rne.tv line 20999 477C_ABFF_B77B_01 1.01101111100 x 2^2 * -1.01111111111 x 2^-5 = -1.01101111011 x 2^-2
+// Skipped denorm f16_mul_rne.tv line 21499 B841_83EF_0217_03 -1.00001000001 x 2^-1 * -Denorm = Denorm
+8800_4FC4_3CFF_18_9BC4_0 // f16_mul_rne.tv line 21999 8800_4FC4_9BC4_00 -1.00000000000 x 2^-13 * 1.01111000100 x 2^4 = -1.01111000100 x 2^-9
+2840_75BF_3CFF_18_621B_1 // f16_mul_rne.tv line 22499 2840_75BF_621B_01 1.00001000000 x 2^-5 * 1.00110111111 x 2^14 = 1.01000011011 x 2^9
+49F9_CC88_3CFF_18_DAC4_1 // f16_mul_rne.tv line 22999 49F9_CC88_DAC4_01 1.00111111001 x 2^3 * -1.00010001000 x 2^4 = -1.01011000100 x 2^7
+FE1E_FFC3_3CFF_18_FE1E_0 // f16_mul_rne.tv line 23499 FE1E_FFC3_FE1E_00 NaN * NaN = NaN
+879E_060F_3CFF_18_8000_3 // f16_mul_rne.tv line 23999 879E_060F_8000_03 -1.01110011110 x 2^-14 * 1.01000001111 x 2^-14 = -Denorm
+DC1B_F460_3CFF_18_7C00_5 // f16_mul_rne.tv line 24499 DC1B_F460_7C00_05 -1.00000011011 x 2^8 * -1.00001100000 x 2^14 = INF
+047C_FBB7_3CFF_18_C453_1 // f16_mul_rne.tv line 24999 047C_FBB7_C453_01 1.00001111100 x 2^-14 * -1.01110110111 x 2^15 = -1.00001010011 x 2^2
+B03F_CD6E_3CFF_18_41C4_1 // f16_mul_rne.tv line 25499 B03F_CD6E_41C4_01 -1.00000111111 x 2^-3 * -1.00101101110 x 2^4 = 1.00111000100 x 2^1
+// Skipped denorm f16_mul_rne.tv line 25999 00FF_687E_287A_01 Denorm * 1.00001111110 x 2^11 = 1.00001111010 x 2^-5
+BB9F_C44E_3CFF_18_441A_1 // f16_mul_rne.tv line 26499 BB9F_C44E_441A_01 -1.01110011111 x 2^-1 * -1.00001001110 x 2^2 = 1.00000011010 x 2^2
+3FF9_6390_3CFF_18_6789_1 // f16_mul_rne.tv line 26999 3FF9_6390_6789_01 1.01111111001 x 2^0 * 1.01110010000 x 2^9 = 1.01110001001 x 2^10
+0A3F_FC81_3CFF_18_FE81_0 // f16_mul_rne.tv line 27499 0A3F_FC81_FE81_10 1.01000111111 x 2^-13 * NaN = NaN
+363F_CBBF_3CFF_18_C60C_1 // f16_mul_rne.tv line 27999 363F_CBBF_C60C_01 1.01000111111 x 2^-2 * -1.01110111111 x 2^3 = -1.01000001100 x 2^2
+// Skipped denorm f16_mul_rne.tv line 28499 807D_7BE0_B7B1_01 -Denorm * 1.01111100000 x 2^15 = -1.01110110001 x 2^-2
+B27F_4840_3CFF_18_BEE7_1 // f16_mul_rne.tv line 28999 B27F_4840_BEE7_01 -1.01001111111 x 2^-3 * 1.00001000000 x 2^3 = -1.01011100111 x 2^0
+0710_7B89_3CFF_18_46A7_1 // f16_mul_rne.tv line 29499 0710_7B89_46A7_01 1.01100010000 x 2^-14 * 1.01110001001 x 2^15 = 1.01010100111 x 2^2
+4C9F_AEC0_3CFF_18_BFCC_1 // f16_mul_rne.tv line 29999 4C9F_AEC0_BFCC_01 1.00010011111 x 2^4 * -1.01011000000 x 2^-4 = -1.01111001100 x 2^0
+6887_B57F_3CFF_18_E238_1 // f16_mul_rne.tv line 30499 6887_B57F_E238_01 1.00010000111 x 2^11 * -1.00101111111 x 2^-2 = -1.01000111000 x 2^9
+CC1C_E2AF_3CFF_18_72DE_1 // f16_mul_rne.tv line 30999 CC1C_E2AF_72DE_01 -1.00000011100 x 2^4 * -1.01010101111 x 2^9 = 1.01011011110 x 2^13
+1C0C_EBD0_3CFF_18_CBE7_1 // f16_mul_rne.tv line 31499 1C0C_EBD0_CBE7_01 1.00000001100 x 2^-8 * -1.01111010000 x 2^11 = -1.01111100111 x 2^3
+FDF7_3D3E_3CFF_18_FFF7_0 // f16_mul_rne.tv line 31999 FDF7_3D3E_FFF7_10 NaN * 1.00100111110 x 2^0 = NaN
+0B40_B807_3CFF_18_874D_1 // f16_mul_rne.tv line 32499 0B40_B807_874D_01 1.01101000000 x 2^-13 * -1.00000000111 x 2^-1 = -1.01101001101 x 2^-14
+9080_D102_3CFF_18_25A2_1 // f16_mul_rne.tv line 32999 9080_D102_25A2_01 -1.00010000000 x 2^-11 * -1.00100000010 x 2^5 = 1.00110100010 x 2^-6
+// Skipped denorm f16_mul_rne.tv line 33499 B021_03F4_8083_03 -1.00000100001 x 2^-3 * Denorm = -Denorm
+// Skipped denorm f16_mul_rne.tv line 33999 DAFE_03FF_A2FC_01 -1.01011111110 x 2^7 * Denorm = -1.01011111100 x 2^-7
+7F01_D122_3CFF_18_7F01_0 // f16_mul_rne.tv line 34499 7F01_D122_7F01_00 NaN * -1.00100100010 x 2^5 = NaN
+B041_7506_3CFF_18_E958_1 // f16_mul_rne.tv line 34999 B041_7506_E958_01 -1.00001000001 x 2^-3 * 1.00100000110 x 2^14 = -1.00101011000 x 2^11
+C37D_6877_3CFF_18_F02E_1 // f16_mul_rne.tv line 35499 C37D_6877_F02E_01 -1.01101111101 x 2^1 * 1.00001110111 x 2^11 = -1.00000101110 x 2^13
+87DE_7F78_3CFF_18_7F78_0 // f16_mul_rne.tv line 35999 87DE_7F78_7F78_00 -1.01111011110 x 2^-14 * NaN = NaN
+5604_87F7_3CFF_18_A1FD_1 // f16_mul_rne.tv line 36499 5604_87F7_A1FD_01 1.01000000100 x 2^6 * -1.01111110111 x 2^-14 = -1.00111111101 x 2^-7
+38F0_8BFC_3CFF_18_88EE_1 // f16_mul_rne.tv line 36999 38F0_8BFC_88EE_01 1.00011110000 x 2^-1 * -1.01111111100 x 2^-13 = -1.00011101110 x 2^-13
+C274_91CE_3CFF_18_18AF_1 // f16_mul_rne.tv line 37499 C274_91CE_18AF_01 -1.01001110100 x 2^1 * -1.00111001110 x 2^-11 = 1.00010101111 x 2^-9
+A2FE_2DDE_3CFF_18_9521_1 // f16_mul_rne.tv line 37999 A2FE_2DDE_9521_01 -1.01011111110 x 2^-7 * 1.00111011110 x 2^-4 = -1.00100100001 x 2^-10
+37FE_C7EF_3CFF_18_C3ED_1 // f16_mul_rne.tv line 38499 37FE_C7EF_C3ED_01 1.01111111110 x 2^-2 * -1.01111101111 x 2^2 = -1.01111101101 x 2^1
+446F_DBFA_3CFF_18_E46C_1 // f16_mul_rne.tv line 38999 446F_DBFA_E46C_01 1.00001101111 x 2^2 * -1.01111111010 x 2^7 = -1.00001101100 x 2^10
+3BFC_7B80_3CFF_18_7B7C_1 // f16_mul_rne.tv line 39499 3BFC_7B80_7B7C_01 1.01111111100 x 2^-1 * 1.01110000000 x 2^15 = 1.01101111100 x 2^15
+4C02_2507_3CFF_18_350A_1 // f16_mul_rne.tv line 39999 4C02_2507_350A_01 1.00000000010 x 2^4 * 1.00100000111 x 2^-6 = 1.00100001010 x 2^-2
+// Skipped denorm f16_mul_rne.tv line 40499 08C0_010F_0000_03 1.00011000000 x 2^-13 * Denorm = 0
+BFF8_3E3E_3CFF_18_C238_1 // f16_mul_rne.tv line 40999 BFF8_3E3E_C238_01 -1.01111111000 x 2^0 * 1.01000111110 x 2^0 = -1.01000111000 x 2^1
+CBC2_27EC_3CFF_18_B7AF_1 // f16_mul_rne.tv line 41499 CBC2_27EC_B7AF_01 -1.01111000010 x 2^3 * 1.01111101100 x 2^-6 = -1.01110101111 x 2^-2
+4655_DD8E_3CFF_18_E866_1 // f16_mul_rne.tv line 41999 4655_DD8E_E866_01 1.01001010101 x 2^2 * -1.00110001110 x 2^8 = -1.00001100110 x 2^11
+DD46_9340_3CFF_18_34C7_1 // f16_mul_rne.tv line 42499 DD46_9340_34C7_01 -1.00101000110 x 2^8 * -1.01101000000 x 2^-11 = 1.00011000111 x 2^-2
+9200_CDE8_3CFF_18_246E_0 // f16_mul_rne.tv line 42999 9200_CDE8_246E_00 -1.01000000000 x 2^-11 * -1.00111101000 x 2^4 = 1.00001101110 x 2^-6
+// Skipped denorm f16_mul_rne.tv line 43499 5BE0_83E2_A3A5_01 1.01111100000 x 2^7 * -Denorm = -1.01110100101 x 2^-7
+74BF_CAC0_3CFF_18_FC00_5 // f16_mul_rne.tv line 43999 74BF_CAC0_FC00_05 1.00010111111 x 2^14 * -1.01011000000 x 2^3 = -INF
+B6ED_C87E_3CFF_18_43C7_1 // f16_mul_rne.tv line 44499 B6ED_C87E_43C7_01 -1.01011101101 x 2^-2 * -1.00001111110 x 2^3 = 1.01111000111 x 2^1
+41EF_AFC3_3CFF_18_B5C2_1 // f16_mul_rne.tv line 44999 41EF_AFC3_B5C2_01 1.00111101111 x 2^1 * -1.01111000011 x 2^-4 = -1.00111000010 x 2^-2
+C8A0_11F0_3CFF_18_9EDE_1 // f16_mul_rne.tv line 45499 C8A0_11F0_9EDE_01 -1.00010100000 x 2^3 * 1.00111110000 x 2^-11 = -1.01011011110 x 2^-8
+D805_7A09_3CFF_18_FC00_5 // f16_mul_rne.tv line 45999 D805_7A09_FC00_05 -1.00000000101 x 2^7 * 1.01000001001 x 2^15 = -INF
+
+////////// Testcases from f16_mulAdd_rz.tv of type mulAdd rounding mode 0
+0000_0BE3_B9AB_0c_B9AB_0 // f16_mulAdd_rz.tv line 50000 0000_0BE3_B9AB_B9AB_00 0 * 1.01111100011 x 2^-13 + -1.00110101011 x 2^-1 = -1.00110101011 x 2^-1
+2FC7_E793_3FFE_0c_DB4D_1 // f16_mulAdd_rz.tv line 100000 2FC7_E793_3FFE_DB4D_01 1.01111000111 x 2^-4 * -1.01110010011 x 2^10 + 1.01111111110 x 2^0 = -1.01101001101 x 2^7
+4B04_3401_4EC1_0c_4FA1_1 // f16_mulAdd_rz.tv line 150000 4B04_3401_4EC1_4FA1_01 1.01100000100 x 2^3 * 1.00000000001 x 2^-2 + 1.01011000001 x 2^4 = 1.01110100001 x 2^4
+// Skipped denorm f16_mulAdd_rz.tv line 200000 03FF_E800_F732_F732_01 Denorm * -1.00000000000 x 2^11 + -1.01100110010 x 2^14 = -1.01100110010 x 2^14
+// Skipped denorm f16_mulAdd_rz.tv line 250000 03FE_D4FF_B401_B414_01 Denorm * -1.00011111111 x 2^6 + -1.00000000001 x 2^-2 = -1.00000010100 x 2^-2
+C411_63FF_D382_0c_EC1F_1 // f16_mulAdd_rz.tv line 300000 C411_63FF_D382_EC1F_01 -1.00000010001 x 2^2 * 1.01111111111 x 2^9 + -1.01110000010 x 2^5 = -1.00000011111 x 2^12
+B7E7_A09F_CC08_0c_CC07_1 // f16_mulAdd_rz.tv line 350000 B7E7_A09F_CC08_CC07_01 -1.01111100111 x 2^-2 * -1.00010011111 x 2^-7 + -1.00000001000 x 2^4 = -1.00000000111 x 2^4
+90BB_BC01_0400_0c_113C_1 // f16_mulAdd_rz.tv line 400000 90BB_BC01_0400_113C_01 -1.00010111011 x 2^-11 * -1.00000000001 x 2^0 + 1.00000000000 x 2^-14 = 1.00100111100 x 2^-11
+07FF_7C00_37FE_0c_7C00_0 // f16_mulAdd_rz.tv line 450000 07FF_7C00_37FE_7C00_00 1.01111111111 x 2^-14 * INF + 1.01111111110 x 2^-2 = INF
+07FE_C197_6C7F_0c_6C7E_1 // f16_mulAdd_rz.tv line 500000 07FE_C197_6C7F_6C7E_01 1.01111111110 x 2^-14 * -1.00110010111 x 2^1 + 1.00001111111 x 2^12 = 1.00001111110 x 2^12
+BC13_2BD7_7BFE_0c_7BFD_1 // f16_mulAdd_rz.tv line 550000 BC13_2BD7_7BFE_7BFD_01 -1.00000010011 x 2^0 * 1.01111010111 x 2^-5 + 1.01111111110 x 2^15 = 1.01111111101 x 2^15
+B5BB_9001_6846_0c_6846_1 // f16_mulAdd_rz.tv line 600000 B5BB_9001_6846_6846_01 -1.00110111011 x 2^-2 * -1.00000000001 x 2^-11 + 1.00001000110 x 2^11 = 1.00001000110 x 2^11
+1001_4400_C0DF_0c_C0DD_1 // f16_mulAdd_rz.tv line 650000 1001_4400_C0DF_C0DD_01 1.00000000001 x 2^-11 * 1.00000000000 x 2^2 + -1.00011011111 x 2^1 = -1.00011011101 x 2^1
+13FF_2C01_C401_0c_C400_1 // f16_mulAdd_rz.tv line 700000 13FF_2C01_C401_C400_01 1.01111111111 x 2^-11 * 1.00000000001 x 2^-4 + -1.00000000001 x 2^2 = -1.00000000000 x 2^2
+ABBF_BBA9_BB78_0c_BB01_1 // f16_mulAdd_rz.tv line 750000 ABBF_BBA9_BB78_BB01_01 -1.01110111111 x 2^-5 * -1.01110101001 x 2^-1 + -1.01101111000 x 2^-1 = -1.01100000001 x 2^-1
+8409_3401_AEBF_0c_AEBF_1 // f16_mulAdd_rz.tv line 800000 8409_3401_AEBF_AEBF_01 -1.00000001001 x 2^-14 * 1.00000000001 x 2^-2 + -1.01010111111 x 2^-4 = -1.01010111111 x 2^-4
+41FE_3801_3C00_0c_40FF_1 // f16_mulAdd_rz.tv line 850000 41FE_3801_3C00_40FF_01 1.00111111110 x 2^1 * 1.00000000001 x 2^-1 + 1.00000000000 x 2^0 = 1.00011111111 x 2^1
+3400_F800_47FE_0c_EFFE_1 // f16_mulAdd_rz.tv line 900000 3400_F800_47FE_EFFE_01 1.00000000000 x 2^-2 * -1.00000000000 x 2^15 + 1.01111111110 x 2^2 = -1.01111111110 x 2^12
+3401_BFCE_F963_0c_F963_1 // f16_mulAdd_rz.tv line 950000 3401_BFCE_F963_F963_01 1.00000000001 x 2^-2 * -1.01111001110 x 2^0 + -1.00101100011 x 2^15 = -1.00101100011 x 2^15
+C8C0_1018_93FE_0c_9DDC_1 // f16_mulAdd_rz.tv line 1000000 C8C0_1018_93FE_9DDC_01 -1.00011000000 x 2^3 * 1.00000011000 x 2^-11 + -1.01111111110 x 2^-11 = -1.00111011100 x 2^-8
+CA7E_0401_CEEE_0c_CEEE_1 // f16_mulAdd_rz.tv line 1050000 CA7E_0401_CEEE_CEEE_01 -1.01001111110 x 2^3 * 1.00000000001 x 2^-14 + -1.01011101110 x 2^4 = -1.01011101110 x 2^4
+37FE_C000_B301_0c_BCDF_1 // f16_mulAdd_rz.tv line 1100000 37FE_C000_B301_BCDF_01 1.01111111110 x 2^-2 * -1.00000000000 x 2^1 + -1.01100000001 x 2^-3 = -1.00011011111 x 2^0
+// Skipped denorm f16_mulAdd_rz.tv line 1150000 3800_5277_0001_4E77_01 1.00000000000 x 2^-1 * 1.01001110111 x 2^5 + Denorm = 1.01001110111 x 2^4
+747B_6881_F708_0c_7BFF_5 // f16_mulAdd_rz.tv line 1200000 747B_6881_F708_7BFF_05 1.00001111011 x 2^14 * 1.00010000001 x 2^11 + -1.01100001000 x 2^14 = 1.01111111111 x 2^15
+C80C_C67F_93FF_0c_5292_1 // f16_mulAdd_rz.tv line 1250000 C80C_C67F_93FF_5292_01 -1.00000001100 x 2^3 * -1.01001111111 x 2^2 + -1.01111111111 x 2^-11 = 1.01010010010 x 2^5
+46DF_B401_7800_0c_77FF_1 // f16_mulAdd_rz.tv line 1300000 46DF_B401_7800_77FF_01 1.01011011111 x 2^2 * -1.00000000001 x 2^-2 + 1.00000000000 x 2^15 = 1.01111111111 x 2^14
+// Skipped denorm f16_mulAdd_rz.tv line 1350000 3BFE_6800_83FE_67FD_01 1.01111111110 x 2^-1 * 1.00000000000 x 2^11 + -Denorm = 1.01111111101 x 2^10
+3C00_CFBE_AC04_0c_CFC2_1 // f16_mulAdd_rz.tv line 1400000 3C00_CFBE_AC04_CFC2_01 1.00000000000 x 2^0 * -1.01110111110 x 2^4 + -1.00000000100 x 2^-4 = -1.01111000010 x 2^4
+E877_C512_C3FE_0c_71A8_1 // f16_mulAdd_rz.tv line 1450000 E877_C512_C3FE_71A8_01 -1.00001110111 x 2^11 * -1.00100010010 x 2^2 + -1.01111111110 x 2^1 = 1.00110101000 x 2^13
+// Skipped denorm f16_mulAdd_rz.tv line 1500000 C011_8001_400B_400B_01 -1.00000010001 x 2^1 * -Denorm + 1.00000001011 x 2^1 = 1.00000001011 x 2^1
+3FFF_3C01_B43B_0c_3EF2_1 // f16_mulAdd_rz.tv line 1550000 3FFF_3C01_B43B_3EF2_01 1.01111111111 x 2^0 * 1.00000000001 x 2^0 + -1.00000111011 x 2^-2 = 1.01011110010 x 2^0
+3FFF_CD3F_3801_0c_D12E_1 // f16_mulAdd_rz.tv line 1600000 3FFF_CD3F_3801_D12E_01 1.01111111111 x 2^0 * -1.00100111111 x 2^4 + 1.00000000001 x 2^-1 = -1.00100101110 x 2^5
+325F_6B90_1607_0c_6205_1 // f16_mulAdd_rz.tv line 1650000 325F_6B90_1607_6205_01 1.01001011111 x 2^-3 * 1.01110010000 x 2^11 + 1.01000000111 x 2^-10 = 1.01000000101 x 2^9
+7B86_BFFA_1CFC_0c_FBFF_5 // f16_mulAdd_rz.tv line 1700000 7B86_BFFA_1CFC_FBFF_05 1.01110000110 x 2^15 * -1.01111111010 x 2^0 + 1.00011111100 x 2^-8 = -1.01111111111 x 2^15
+D61E_1001_9000_0c_AA2F_1 // f16_mulAdd_rz.tv line 1750000 D61E_1001_9000_AA2F_01 -1.01000011110 x 2^6 * 1.00000000001 x 2^-11 + -1.00000000000 x 2^-11 = -1.01000101111 x 2^-5
+4001_C400_BBFE_0c_C880_1 // f16_mulAdd_rz.tv line 1800000 4001_C400_BBFE_C880_01 1.00000000001 x 2^1 * -1.00000000000 x 2^2 + -1.01111111110 x 2^-1 = -1.00010000000 x 2^3
+43FF_4500_C91D_0c_48E1_1 // f16_mulAdd_rz.tv line 1850000 43FF_4500_C91D_48E1_01 1.01111111111 x 2^1 * 1.00100000000 x 2^2 + -1.00100011101 x 2^3 = 1.00011100001 x 2^3
+B710_BB18_FFFE_0c_FFFE_0 // f16_mulAdd_rz.tv line 1900000 B710_BB18_FFFE_FFFE_00 -1.01100010000 x 2^-2 * -1.01100011000 x 2^-1 + NaN = NaN
+6817_FFFF_B85F_0c_FFFF_0 // f16_mulAdd_rz.tv line 1950000 6817_FFFF_B85F_FFFF_00 1.00000010111 x 2^11 * NaN + -1.00001011111 x 2^-1 = NaN
+4400_B801_D510_0c_D530_1 // f16_mulAdd_rz.tv line 2000000 4400_B801_D510_D530_01 1.00000000000 x 2^2 * -1.00000000001 x 2^-1 + -1.00100010000 x 2^6 = -1.00100110000 x 2^6
+4401_43E6_6801_0c_6808_1 // f16_mulAdd_rz.tv line 2050000 4401_43E6_6801_6808_01 1.00000000001 x 2^2 * 1.01111100110 x 2^1 + 1.00000000001 x 2^11 = 1.00000001000 x 2^11
+// Skipped denorm f16_mulAdd_rz.tv line 2100000 FF2B_4784_0376_FF2B_00 NaN * 1.01110000100 x 2^2 + Denorm = NaN
+497E_BBDB_46E6_0c_C3C6_1 // f16_mulAdd_rz.tv line 2150000 497E_BBDB_46E6_C3C6_01 1.00101111110 x 2^3 * -1.01111011011 x 2^-1 + 1.01011100110 x 2^2 = -1.01111000110 x 2^1
+2FD8_8401_C000_0c_C000_1 // f16_mulAdd_rz.tv line 2200000 2FD8_8401_C000_C000_01 1.01111011000 x 2^-4 * -1.00000000001 x 2^-14 + -1.00000000000 x 2^1 = -1.00000000000 x 2^1
+6800_4000_EBFE_0c_4400_0 // f16_mulAdd_rz.tv line 2250000 6800_4000_EBFE_4400_00 1.00000000000 x 2^11 * 1.00000000000 x 2^1 + -1.01111111110 x 2^11 = 1.00000000000 x 2^2
+// Skipped denorm f16_mulAdd_rz.tv line 2300000 6801_800C_305F_3052_01 1.00000000001 x 2^11 * -Denorm + 1.00001011111 x 2^-3 = 1.00001010010 x 2^-3
+C0E9_B2FF_37FE_0c_3C25_1 // f16_mulAdd_rz.tv line 2350000 C0E9_B2FF_37FE_3C25_01 -1.00011101001 x 2^1 * -1.01011111111 x 2^-3 + 1.01111111110 x 2^-2 = 1.00000100101 x 2^0
+6A7F_7BFF_7405_0c_7BFF_5 // f16_mulAdd_rz.tv line 2400000 6A7F_7BFF_7405_7BFF_05 1.01001111111 x 2^11 * 1.01111111111 x 2^15 + 1.00000000101 x 2^14 = 1.01111111111 x 2^15
+6BFE_3401_B87A_0c_63FE_1 // f16_mulAdd_rz.tv line 2450000 6BFE_3401_B87A_63FE_01 1.01111111110 x 2^11 * 1.00000000001 x 2^-2 + -1.00001111010 x 2^-1 = 1.01111111110 x 2^9
+6BFE_343E_8401_0c_643C_1 // f16_mulAdd_rz.tv line 2500000 6BFE_343E_8401_643C_01 1.01111111110 x 2^11 * 1.00000111110 x 2^-2 + -1.00000000001 x 2^-14 = 1.00000111100 x 2^10
+// Skipped denorm f16_mulAdd_rz.tv line 2550000 3D03_02FB_AFFE_AFFD_01 1.00100000011 x 2^0 * Denorm + -1.01111111110 x 2^-4 = -1.01111111101 x 2^-4
+7A10_47D2_AC4E_0c_7BFF_5 // f16_mulAdd_rz.tv line 2600000 7A10_47D2_AC4E_7BFF_05 1.01000010000 x 2^15 * 1.01111010010 x 2^2 + -1.00001001110 x 2^-4 = 1.01111111111 x 2^15
+// Skipped denorm f16_mulAdd_rz.tv line 2650000 FBFE_0001_FC00_FC00_00 -1.01111111110 x 2^15 * Denorm + -INF = -INF
+7BFF_BC01_07FE_0c_FBFF_5 // f16_mulAdd_rz.tv line 2700000 7BFF_BC01_07FE_FBFF_05 1.01111111111 x 2^15 * -1.00000000001 x 2^0 + 1.01111111110 x 2^-14 = -1.01111111111 x 2^15
+7BFE_310F_5000_0c_7111_1 // f16_mulAdd_rz.tv line 2750000 7BFE_310F_5000_7111_01 1.01111111110 x 2^15 * 1.00100001111 x 2^-3 + 1.00000000000 x 2^5 = 1.00100010001 x 2^13
+7933_17DE_47FE_0c_559C_1 // f16_mulAdd_rz.tv line 2800000 7933_17DE_47FE_559C_01 1.00100110011 x 2^15 * 1.01111011110 x 2^-10 + 1.01111111110 x 2^2 = 1.00110011100 x 2^6
+// Skipped denorm f16_mulAdd_rz.tv line 2850000 0083_EBFF_B00F_B114_01 Denorm * -1.01111111111 x 2^11 + -1.00000001111 x 2^-3 = -1.00100010100 x 2^-3
+7C01_9001_406F_0c_7E01_0 // f16_mulAdd_rz.tv line 2900000 7C01_9001_406F_7E01_10 NaN * -1.00000000001 x 2^-11 + 1.00001101111 x 2^1 = NaN
+7FFF_E3C7_BC01_0c_7FFF_0 // f16_mulAdd_rz.tv line 2950000 7FFF_E3C7_BC01_7FFF_00 NaN * -1.01111000111 x 2^9 + -1.00000000001 x 2^0 = NaN
+C4FF_87CF_2FDC_0c_2FE5_1 // f16_mulAdd_rz.tv line 3000000 C4FF_87CF_2FDC_2FE5_01 -1.00011111111 x 2^2 * -1.01111001111 x 2^-14 + 1.01111011100 x 2^-4 = 1.01111100101 x 2^-4
+87F8_6016_4AB3_0c_4AAA_1 // f16_mulAdd_rz.tv line 3050000 87F8_6016_4AB3_4AAA_01 -1.01111111000 x 2^-14 * 1.00000010110 x 2^9 + 1.01010110011 x 2^3 = 1.01010101010 x 2^3
+785F_7FFF_3400_0c_7FFF_0 // f16_mulAdd_rz.tv line 3100000 785F_7FFF_3400_7FFF_00 1.00001011111 x 2^15 * NaN + 1.00000000000 x 2^-2 = NaN
+// Skipped denorm f16_mulAdd_rz.tv line 3150000 8001_3801_3FFE_3FFD_01 -Denorm * 1.00000000001 x 2^-1 + 1.01111111110 x 2^0 = 1.01111111101 x 2^0
+// Skipped denorm f16_mulAdd_rz.tv line 3200000 8001_9376_03E0_03E0_03 -Denorm * -1.01101110110 x 2^-11 + Denorm = Denorm
+// Skipped denorm f16_mulAdd_rz.tv line 3250000 BBF8_3103_83FE_B0FE_01 -1.01111111000 x 2^-1 * 1.00100000011 x 2^-3 + -Denorm = -1.00011111110 x 2^-3
+4702_47FF_5F80_0c_6030_1 // f16_mulAdd_rz.tv line 3300000 4702_47FF_5F80_6030_01 1.01100000010 x 2^2 * 1.01111111111 x 2^2 + 1.01110000000 x 2^8 = 1.00000110000 x 2^9
+8400_0401_4010_0c_400F_1 // f16_mulAdd_rz.tv line 3350000 8400_0401_4010_400F_01 -1.00000000000 x 2^-14 * 1.00000000001 x 2^-14 + 1.00000010000 x 2^1 = 1.00000001111 x 2^1
+8400_33B6_F801_0c_F801_1 // f16_mulAdd_rz.tv line 3400000 8400_33B6_F801_F801_01 -1.00000000000 x 2^-14 * 1.01110110110 x 2^-3 + -1.00000000001 x 2^15 = -1.00000000001 x 2^15
+DAAF_4B90_C7BD_0c_EA55_1 // f16_mulAdd_rz.tv line 3450000 DAAF_4B90_C7BD_EA55_01 -1.01010101111 x 2^7 * 1.01110010000 x 2^3 + -1.01110111101 x 2^2 = -1.01001010101 x 2^11
+9021_32AD_B399_0c_B399_1 // f16_mulAdd_rz.tv line 3500000 9021_32AD_B399_B399_01 -1.00000100001 x 2^-11 * 1.01010101101 x 2^-3 + -1.01110011001 x 2^-3 = -1.01110011001 x 2^-3
+AF8F_FBFF_4400_0c_6F8F_1 // f16_mulAdd_rz.tv line 3550000 AF8F_FBFF_4400_6F8F_01 -1.01110001111 x 2^-4 * -1.01111111111 x 2^15 + 1.00000000000 x 2^2 = 1.01110001111 x 2^12
+87FE_B401_7BFE_0c_7BFE_1 // f16_mulAdd_rz.tv line 3600000 87FE_B401_7BFE_7BFE_01 -1.01111111110 x 2^-14 * -1.00000000001 x 2^-2 + 1.01111111110 x 2^15 = 1.01111111110 x 2^15
+9000_8E7C_0BAF_0c_0BB0_1 // f16_mulAdd_rz.tv line 3650000 9000_8E7C_0BAF_0BB0_01 -1.00000000000 x 2^-11 * -1.01001111100 x 2^-12 + 1.01110101111 x 2^-13 = 1.01110110000 x 2^-13
+744C_95FA_BBFE_0c_CEAB_1 // f16_mulAdd_rz.tv line 3700000 744C_95FA_BBFE_CEAB_01 1.00001001100 x 2^14 * -1.00111111010 x 2^-10 + -1.01111111110 x 2^-1 = -1.01010101011 x 2^4
+42FE_C3FF_B81C_0c_CB3E_1 // f16_mulAdd_rz.tv line 3750000 42FE_C3FF_B81C_CB3E_01 1.01011111110 x 2^1 * -1.01111111111 x 2^1 + -1.00000011100 x 2^-1 = -1.01100111110 x 2^3
+// Skipped denorm f16_mulAdd_rz.tv line 3800000 93FF_8001_88FE_88FD_01 -1.01111111111 x 2^-11 * -Denorm + -1.00011111110 x 2^-13 = -1.00011111101 x 2^-13
+93FE_7401_1001_0c_CBFF_1 // f16_mulAdd_rz.tv line 3850000 93FE_7401_1001_CBFF_01 -1.01111111110 x 2^-11 * 1.00000000001 x 2^14 + 1.00000000001 x 2^-11 = -1.01111111111 x 2^3
+3C16_42F4_43E1_0c_477D_1 // f16_mulAdd_rz.tv line 3900000 3C16_42F4_43E1_477D_01 1.00000010110 x 2^0 * 1.01011110100 x 2^1 + 1.01111100001 x 2^1 = 1.01101111101 x 2^2
+7FBF_47FF_C18F_0c_7FBF_0 // f16_mulAdd_rz.tv line 3950000 7FBF_47FF_C18F_7FBF_00 NaN * 1.01111111111 x 2^2 + -1.00110001111 x 2^1 = NaN
+// Skipped denorm f16_mulAdd_rz.tv line 4000000 441E_6BFF_8000_741D_01 1.00000011110 x 2^2 * 1.01111111111 x 2^11 + -Denorm = 1.00000011101 x 2^14
+B7FF_1001_93FE_0c_94FF_1 // f16_mulAdd_rz.tv line 4050000 B7FF_1001_93FE_94FF_01 -1.01111111111 x 2^-2 * 1.00000000001 x 2^-11 + -1.01111111110 x 2^-11 = -1.00011111111 x 2^-10
+B7FF_C9C0_47DF_0c_4ACF_1 // f16_mulAdd_rz.tv line 4100000 B7FF_C9C0_47DF_4ACF_01 -1.01111111111 x 2^-2 * -1.00111000000 x 2^3 + 1.01111011111 x 2^2 = 1.01011001111 x 2^3
+C40F_AB7F_EBFE_0c_EBFD_1 // f16_mulAdd_rz.tv line 4150000 C40F_AB7F_EBFE_EBFD_01 -1.00000001111 x 2^2 * -1.01101111111 x 2^-5 + -1.01111111110 x 2^11 = -1.01111111101 x 2^11
+D404_3FFE_EAF9_0c_EB39_1 // f16_mulAdd_rz.tv line 4200000 D404_3FFE_EAF9_EB39_01 -1.00000000100 x 2^6 * 1.01111111110 x 2^0 + -1.01011111001 x 2^11 = -1.01100111001 x 2^11
+B800_FFFF_F201_0c_FFFF_0 // f16_mulAdd_rz.tv line 4250000 B800_FFFF_F201_FFFF_00 -1.00000000000 x 2^-1 * NaN + -1.01000000001 x 2^13 = NaN
+B801_3D3F_4001_0c_3D61_1 // f16_mulAdd_rz.tv line 4300000 B801_3D3F_4001_3D61_01 -1.00000000001 x 2^-1 * 1.00100111111 x 2^0 + 1.00000000001 x 2^1 = 1.00101100001 x 2^0
+4FFF_4D63_77FF_0c_7815_1 // f16_mulAdd_rz.tv line 4350000 4FFF_4D63_77FF_7815_01 1.01111111111 x 2^4 * 1.00101100011 x 2^4 + 1.01111111111 x 2^14 = 1.00000010101 x 2^15
+C41B_0FA0_C902_0c_C902_1 // f16_mulAdd_rz.tv line 4400000 C41B_0FA0_C902_C902_01 -1.00000011011 x 2^2 * 1.01110100000 x 2^-12 + -1.00100000010 x 2^3 = -1.00100000010 x 2^3
+B7C2_C7FF_B800_0c_42C1_1 // f16_mulAdd_rz.tv line 4450000 B7C2_C7FF_B800_42C1_01 -1.01111000010 x 2^-2 * -1.01111111111 x 2^2 + -1.00000000000 x 2^-1 = 1.01011000001 x 2^1
+BC00_8401_C3FE_0c_C3FD_1 // f16_mulAdd_rz.tv line 4500000 BC00_8401_C3FE_C3FD_01 -1.00000000000 x 2^0 * -1.00000000001 x 2^-14 + -1.01111111110 x 2^1 = -1.01111111101 x 2^1
+BC01_6800_D06F_0c_E812_1 // f16_mulAdd_rz.tv line 4550000 BC01_6800_D06F_E812_01 -1.00000000001 x 2^0 * 1.00000000000 x 2^11 + -1.00001101111 x 2^5 = -1.00000010010 x 2^11
+CFBC_931A_07FE_0c_26E5_1 // f16_mulAdd_rz.tv line 4600000 CFBC_931A_07FE_26E5_01 -1.01110111100 x 2^4 * -1.01100011010 x 2^-11 + 1.01111111110 x 2^-14 = 1.01011100101 x 2^-6
+7C70_BBFE_27F8_0c_7E70_0 // f16_mulAdd_rz.tv line 4650000 7C70_BBFE_27F8_7E70_10 NaN * -1.01111111110 x 2^-1 + 1.01111111000 x 2^-6 = NaN
+BFFE_7BFF_D3DF_0c_FBFF_5 // f16_mulAdd_rz.tv line 4700000 BFFE_7BFF_D3DF_FBFF_05 -1.01111111110 x 2^0 * 1.01111111111 x 2^15 + -1.01111011111 x 2^5 = -1.01111111111 x 2^15
+C000_2383_7C01_0c_7E01_0 // f16_mulAdd_rz.tv line 4750000 C000_2383_7C01_7E01_10 -1.00000000000 x 2^1 * 1.01110000011 x 2^-7 + NaN = NaN
+// Skipped denorm f16_mulAdd_rz.tv line 4800000 AFBC_8020_87F2_87EE_01 -1.01110111100 x 2^-4 * -Denorm + -1.01111110010 x 2^-14 = -1.01111101110 x 2^-14
+D00C_B8F6_B3CF_0c_4CF5_1 // f16_mulAdd_rz.tv line 4850000 D00C_B8F6_B3CF_4CF5_01 -1.00000001100 x 2^5 * -1.00011110110 x 2^-1 + -1.01111001111 x 2^-3 = 1.00011110101 x 2^4
+8BEB_43FF_E800_0c_E800_1 // f16_mulAdd_rz.tv line 4900000 8BEB_43FF_E800_E800_01 -1.01111101011 x 2^-13 * 1.01111111111 x 2^1 + -1.00000000000 x 2^11 = -1.00000000000 x 2^11
+// Skipped denorm f16_mulAdd_rz.tv line 4950000 C3FE_0001_FFFE_FFFE_00 -1.01111111110 x 2^1 * Denorm + NaN = NaN
+C3FE_B1FF_A600_0c_39CD_1 // f16_mulAdd_rz.tv line 5000000 C3FE_B1FF_A600_39CD_01 -1.01111111110 x 2^1 * -1.00111111111 x 2^-3 + -1.01000000000 x 2^-6 = 1.00111001101 x 2^-1
+B004_FC44_3FFE_0c_FE44_0 // f16_mulAdd_rz.tv line 5050000 B004_FC44_3FFE_FE44_10 -1.00000000100 x 2^-3 * NaN + 1.01111111110 x 2^0 = NaN
+85FF_37FE_31FE_0c_31FD_1 // f16_mulAdd_rz.tv line 5100000 85FF_37FE_31FE_31FD_01 -1.00111111111 x 2^-14 * 1.01111111110 x 2^-2 + 1.00111111110 x 2^-3 = 1.00111111101 x 2^-3
+C401_EBFF_92C2_0c_7400_1 // f16_mulAdd_rz.tv line 5150000 C401_EBFF_92C2_7400_01 -1.00000000001 x 2^2 * -1.01111111111 x 2^11 + -1.01011000010 x 2^-11 = 1.00000000000 x 2^14
+C7FF_B408_B401_0c_3F0E_1 // f16_mulAdd_rz.tv line 5200000 C7FF_B408_B401_3F0E_01 -1.01111111111 x 2^2 * -1.00000001000 x 2^-2 + -1.00000000001 x 2^-2 = 1.01100001110 x 2^0
+43E0_C6FB_2360_0c_CEDE_1 // f16_mulAdd_rz.tv line 5250000 43E0_C6FB_2360_CEDE_01 1.01111100000 x 2^1 * -1.01011111011 x 2^2 + 1.01101100000 x 2^-7 = -1.01011011110 x 2^4
+8B87_2C17_4F43_0c_4F42_1 // f16_mulAdd_rz.tv line 5300000 8B87_2C17_4F43_4F42_01 -1.01110000111 x 2^-13 * 1.00000010111 x 2^-4 + 1.01101000011 x 2^4 = 1.01101000010 x 2^4
+// Skipped denorm f16_mulAdd_rz.tv line 5350000 830F_BFFE_0400_090E_01 -Denorm * -1.01111111110 x 2^0 + 1.00000000000 x 2^-14 = 1.00100001110 x 2^-13
+E801_7FFF_37FE_0c_7FFF_0 // f16_mulAdd_rz.tv line 5400000 E801_7FFF_37FE_7FFF_00 -1.00000000001 x 2^11 * NaN + 1.01111111110 x 2^-2 = NaN
+EBFF_483F_C7C1_0c_F83E_1 // f16_mulAdd_rz.tv line 5450000 EBFF_483F_C7C1_F83E_01 -1.01111111111 x 2^11 * 1.00000111111 x 2^3 + -1.01111000001 x 2^2 = -1.00000111110 x 2^15
+49FE_3703_7BFE_0c_7BFE_1 // f16_mulAdd_rz.tv line 5500000 49FE_3703_7BFE_7BFE_01 1.00111111110 x 2^3 * 1.01100000011 x 2^-2 + 1.01111111110 x 2^15 = 1.01111111110 x 2^15
+84BE_93FE_33DE_0c_33DE_1 // f16_mulAdd_rz.tv line 5550000 84BE_93FE_33DE_33DE_01 -1.00010111110 x 2^-14 * -1.01111111110 x 2^-11 + 1.01111011110 x 2^-3 = 1.01111011110 x 2^-3
+F800_47FF_40FE_0c_FBFF_5 // f16_mulAdd_rz.tv line 5600000 F800_47FF_40FE_FBFF_05 -1.00000000000 x 2^15 * 1.01111111111 x 2^2 + 1.00011111110 x 2^1 = -1.01111111111 x 2^15
+F801_E3FE_C401_0c_7BFF_5 // f16_mulAdd_rz.tv line 5650000 F801_E3FE_C401_7BFF_05 -1.00000000001 x 2^15 * -1.01111111110 x 2^9 + -1.00000000001 x 2^2 = 1.01111111111 x 2^15
+0E80_0810_E912_0c_E911_1 // f16_mulAdd_rz.tv line 5700000 0E80_0810_E912_E911_01 1.01010000000 x 2^-12 * 1.00000010000 x 2^-13 + -1.00100010010 x 2^11 = -1.00100010001 x 2^11
+A67F_49FF_4D3E_0c_4D2A_1 // f16_mulAdd_rz.tv line 5750000 A67F_49FF_4D3E_4D2A_01 -1.01001111111 x 2^-6 * 1.00111111111 x 2^3 + 1.00100111110 x 2^4 = 1.00100101010 x 2^4
+22DC_3BFE_3C00_0c_3C0D_1 // f16_mulAdd_rz.tv line 5800000 22DC_3BFE_3C00_3C0D_01 1.01011011100 x 2^-7 * 1.01111111110 x 2^-1 + 1.00000000000 x 2^0 = 1.00000001101 x 2^0
+FBFE_FBFF_47FE_0c_7BFF_5 // f16_mulAdd_rz.tv line 5850000 FBFE_FBFF_47FE_7BFF_05 -1.01111111110 x 2^15 * -1.01111111111 x 2^15 + 1.01111111110 x 2^2 = 1.01111111111 x 2^15
+FC00_CE07_47C3_0c_7C00_0 // f16_mulAdd_rz.tv line 5900000 FC00_CE07_47C3_7C00_00 -INF * -1.01000000111 x 2^4 + 1.01111000011 x 2^2 = INF
+343D_C5C9_93FE_0c_BE22_1 // f16_mulAdd_rz.tv line 5950000 343D_C5C9_93FE_BE22_01 1.00000111101 x 2^-2 * -1.00111001001 x 2^2 + -1.01111111110 x 2^-11 = -1.01000100010 x 2^0
+EA10_07FE_C803_0c_C833_1 // f16_mulAdd_rz.tv line 6000000 EA10_07FE_C803_C833_01 -1.01000010000 x 2^11 * 1.01111111110 x 2^-14 + -1.00000000011 x 2^3 = -1.00000110011 x 2^3
+FFFF_C3FF_EA40_0c_FFFF_0 // f16_mulAdd_rz.tv line 6050000 FFFF_C3FF_EA40_FFFF_00 NaN * -1.01111111111 x 2^1 + -1.01001000000 x 2^11 = NaN
+// Skipped denorm f16_mulAdd_rz.tv line 6100000 FFFE_80F8_0001_FFFE_00 NaN * -Denorm + Denorm = NaN
+
+////////// Testcases from f16_mulAdd_rd.tv of type mulAdd rounding mode 2
+0B01_93FB_E83F_2c_E840_1 // f16_mulAdd_rd.tv line 49998 0B01_93FB_E83F_E840_01 1.01100000001 x 2^-13 * -1.01111111011 x 2^-11 + -1.00000111111 x 2^11 = -1.00001000000 x 2^11
+FC82_C91F_A6FD_2c_FE82_0 // f16_mulAdd_rd.tv line 99998 FC82_C91F_A6FD_FE82_10 NaN * -1.00100011111 x 2^3 + -1.01011111101 x 2^-6 = NaN
+06EF_3401_6BFF_2c_6BFF_1 // f16_mulAdd_rd.tv line 149998 06EF_3401_6BFF_6BFF_01 1.01011101111 x 2^-14 * 1.00000000001 x 2^-2 + 1.01111111111 x 2^11 = 1.01111111111 x 2^11
+// Skipped denorm f16_mulAdd_rd.tv line 199998 03FF_E800_8001_AFFF_01 Denorm * -1.00000000000 x 2^11 + -Denorm = -1.01111111111 x 2^-4
+// Skipped denorm f16_mulAdd_rd.tv line 249998 03FE_30FE_4903_4903_01 Denorm * 1.00011111110 x 2^-3 + 1.00100000011 x 2^3 = 1.00100000011 x 2^3
+3812_AC1B_C001_2c_C012_1 // f16_mulAdd_rd.tv line 299998 3812_AC1B_C001_C012_01 1.00000010010 x 2^-1 * -1.00000011011 x 2^-4 + -1.00000000001 x 2^1 = -1.00000010010 x 2^1
+// Skipped denorm f16_mulAdd_rd.tv line 349998 F570_0001_CC03_CC04_01 -1.00101110000 x 2^14 * Denorm + -1.00000000011 x 2^4 = -1.00000000100 x 2^4
+0401_BC01_487C_2c_487B_1 // f16_mulAdd_rd.tv line 399998 0401_BC01_487C_487B_01 1.00000000001 x 2^-14 * -1.00000000001 x 2^0 + 1.00001111100 x 2^3 = 1.00001111011 x 2^3
+07FF_B388_37FE_2c_37FD_1 // f16_mulAdd_rd.tv line 449998 07FF_B388_37FE_37FD_01 1.01111111111 x 2^-14 * -1.01110001000 x 2^-3 + 1.01111111110 x 2^-2 = 1.01111111101 x 2^-2
+C821_EFFF_B477_2c_7BFF_5 // f16_mulAdd_rd.tv line 499998 C821_EFFF_B477_7BFF_05 -1.00000100001 x 2^3 * -1.01111111111 x 2^12 + -1.00001110111 x 2^-2 = 1.01111111111 x 2^15
+107F_7D02_B304_2c_7F02_0 // f16_mulAdd_rd.tv line 549998 107F_7D02_B304_7F02_10 1.00001111111 x 2^-11 * NaN + -1.01100000100 x 2^-3 = NaN
+3AFF_9001_87FF_2c_9081_1 // f16_mulAdd_rd.tv line 599998 3AFF_9001_87FF_9081_01 1.01011111111 x 2^-1 * -1.00000000001 x 2^-11 + -1.01111111111 x 2^-14 = -1.00010000001 x 2^-11
+1001_4400_B801_2c_B7FA_1 // f16_mulAdd_rd.tv line 649998 1001_4400_B801_B7FA_01 1.00000000001 x 2^-11 * 1.00000000000 x 2^2 + -1.00000000001 x 2^-1 = -1.01111111010 x 2^-2
+13FF_FB7E_FC14_2c_FE14_0 // f16_mulAdd_rd.tv line 699998 13FF_FB7E_FC14_FE14_10 1.01111111111 x 2^-11 * -1.01101111110 x 2^15 + NaN = NaN
+4F88_2C3F_FC01_2c_FE01_0 // f16_mulAdd_rd.tv line 749998 4F88_2C3F_FC01_FE01_10 1.01110001000 x 2^4 * 1.00000111111 x 2^-4 + NaN = NaN
+// Skipped denorm f16_mulAdd_rd.tv line 799998 5B66_7FFF_83C6_7FFF_00 1.01101100110 x 2^7 * NaN + -Denorm = NaN
+3400_3801_33CD_2c_35E7_0 // f16_mulAdd_rd.tv line 849998 3400_3801_33CD_35E7_00 1.00000000000 x 2^-2 * 1.00000000001 x 2^-1 + 1.01111001101 x 2^-3 = 1.00111100111 x 2^-2
+3400_C1F0_47FE_2c_4740_0 // f16_mulAdd_rd.tv line 899998 3400_C1F0_47FE_4740_00 1.00000000000 x 2^-2 * -1.00111110000 x 2^1 + 1.01111111110 x 2^2 = 1.01101000000 x 2^2
+3102_87F7_3C1F_2c_3C1E_1 // f16_mulAdd_rd.tv line 949998 3102_87F7_3C1F_3C1E_01 1.00100000010 x 2^-3 * -1.01111110111 x 2^-14 + 1.00000011111 x 2^0 = 1.00000011110 x 2^0
+13FB_F8FD_4E75_2c_CAFE_1 // f16_mulAdd_rd.tv line 999998 13FB_F8FD_4E75_CAFE_01 1.01111111011 x 2^-11 * -1.00011111101 x 2^15 + 1.01001110101 x 2^4 = -1.01011111110 x 2^3
+FFEF_0401_BFFF_2c_FFEF_0 // f16_mulAdd_rd.tv line 1049998 FFEF_0401_BFFF_FFEF_00 NaN * 1.00000000001 x 2^-14 + -1.01111111111 x 2^0 = NaN
+37FE_C000_E801_2c_E802_1 // f16_mulAdd_rd.tv line 1099998 37FE_C000_E801_E802_01 1.01111111110 x 2^-2 * -1.00000000000 x 2^1 + -1.00000000001 x 2^11 = -1.00000000010 x 2^11
+3800_5AB8_FBF7_2c_FBF4_1 // f16_mulAdd_rd.tv line 1149998 3800_5AB8_FBF7_FBF4_01 1.00000000000 x 2^-1 * 1.01010111000 x 2^7 + -1.01111110111 x 2^15 = -1.01111110100 x 2^15
+04FB_286D_3401_2c_3401_1 // f16_mulAdd_rd.tv line 1199998 04FB_286D_3401_3401_01 1.00011111011 x 2^-14 * 1.00001101101 x 2^-5 + 1.00000000001 x 2^-2 = 1.00000000001 x 2^-2
+3C86_FBFF_D0FF_2c_FC00_5 // f16_mulAdd_rd.tv line 1249998 3C86_FBFF_D0FF_FC00_05 1.00010000110 x 2^0 * -1.01111111111 x 2^15 + -1.00011111111 x 2^5 = -INF
+3BFF_B401_23FE_2c_B382_1 // f16_mulAdd_rd.tv line 1299998 3BFF_B401_23FE_B382_01 1.01111111111 x 2^-1 * -1.00000000001 x 2^-2 + 1.01111111110 x 2^-7 = -1.01110000010 x 2^-3
+// Skipped denorm f16_mulAdd_rd.tv line 1349998 3BFE_4BD0_83FE_4BCE_01 1.01111111110 x 2^-1 * 1.01111010000 x 2^3 + -Denorm = 1.01111001110 x 2^3
+2FF6_3B84_47EF_2c_4806_1 // f16_mulAdd_rd.tv line 1399998 2FF6_3B84_47EF_4806_01 1.01111110110 x 2^-4 * 1.01110000100 x 2^-1 + 1.01111101111 x 2^2 = 1.00000000110 x 2^3
+8BFE_BBF1_1D3C_2c_1D7B_1 // f16_mulAdd_rd.tv line 1449998 8BFE_BBF1_1D3C_1D7B_01 -1.01111111110 x 2^-13 * -1.01111110001 x 2^-1 + 1.00100111100 x 2^-8 = 1.00101111011 x 2^-8
+// Skipped denorm f16_mulAdd_rd.tv line 1499998 F7F6_8001_FBFF_FBFF_01 -1.01111110110 x 2^14 * -Denorm + -1.01111111111 x 2^15 = -1.01111111111 x 2^15
+3FFF_3C01_0401_2c_4000_1 // f16_mulAdd_rd.tv line 1549998 3FFF_3C01_0401_4000_01 1.01111111111 x 2^0 * 1.00000000001 x 2^0 + 1.00000000001 x 2^-14 = 1.00000000000 x 2^1
+3FFF_3420_B410_2c_342E_1 // f16_mulAdd_rd.tv line 1599998 3FFF_3420_B410_342E_01 1.01111111111 x 2^0 * 1.00000100000 x 2^-2 + -1.00000010000 x 2^-2 = 1.00000101110 x 2^-2
+B0B7_6A6F_4401_2c_DF86_1 // f16_mulAdd_rd.tv line 1649998 B0B7_6A6F_4401_DF86_01 -1.00010110111 x 2^-3 * 1.01001101111 x 2^11 + 1.00000000001 x 2^2 = -1.01110000110 x 2^8
+0774_6BFF_DEC4_2c_DEC3_1 // f16_mulAdd_rd.tv line 1699998 0774_6BFF_DEC4_DEC3_01 1.01101110100 x 2^-14 * 1.01111111111 x 2^11 + -1.01011000100 x 2^8 = -1.01011000011 x 2^8
+4001_1001_BF3F_2c_BF3E_1 // f16_mulAdd_rd.tv line 1749998 4001_1001_BF3F_BF3E_01 1.00000000001 x 2^1 * 1.00000000001 x 2^-11 + -1.01100111111 x 2^0 = -1.01100111110 x 2^0
+4001_7FDF_BBFE_2c_7FDF_0 // f16_mulAdd_rd.tv line 1799998 4001_7FDF_BBFE_7FDF_00 1.00000000001 x 2^1 * NaN + -1.01111111110 x 2^-1 = NaN
+FF7C_7FFA_747E_2c_FF7C_0 // f16_mulAdd_rd.tv line 1849998 FF7C_7FFA_747E_FF7C_00 NaN * NaN + 1.00001111110 x 2^14 = NaN
+4903_D4FE_BBF5_2c_E244_1 // f16_mulAdd_rd.tv line 1899998 4903_D4FE_BBF5_E244_01 1.00100000011 x 2^3 * -1.00011111110 x 2^6 + -1.01111110101 x 2^-1 = -1.01001000100 x 2^9
+440F_FFFF_13FF_2c_FFFF_0 // f16_mulAdd_rd.tv line 1949998 440F_FFFF_13FF_FFFF_00 1.00000001111 x 2^2 * NaN + 1.01111111111 x 2^-11 = NaN
+4400_B801_3C01_2c_BC01_0 // f16_mulAdd_rd.tv line 1999998 4400_B801_3C01_BC01_00 1.00000000000 x 2^2 * -1.00000000001 x 2^-1 + 1.00000000001 x 2^0 = -1.00000000001 x 2^0
+4401_2BFA_B423_2c_A0A1_1 // f16_mulAdd_rd.tv line 2049998 4401_2BFA_B423_A0A1_01 1.00000000001 x 2^2 * 1.01111111010 x 2^-5 + -1.00000100011 x 2^-2 = -1.00010100001 x 2^-7
+// Skipped denorm f16_mulAdd_rd.tv line 2099998 3016_3E80_8001_32A3_01 1.00000010110 x 2^-3 * 1.01010000000 x 2^0 + -Denorm = 1.01010100011 x 2^-3
+F420_C7FF_B8F7_2c_7BFF_5 // f16_mulAdd_rd.tv line 2149998 F420_C7FF_B8F7_7BFF_05 -1.00000100000 x 2^14 * -1.01111111111 x 2^2 + -1.00011110111 x 2^-1 = 1.01111111111 x 2^15
+47FE_8401_B7FF_2c_B801_1 // f16_mulAdd_rd.tv line 2199998 47FE_8401_B7FF_B801_01 1.01111111110 x 2^2 * -1.00000000001 x 2^-14 + -1.01111111111 x 2^-2 = -1.00000000001 x 2^-1
+6800_433C_EBFE_2c_6A7A_0 // f16_mulAdd_rd.tv line 2249998 6800_433C_EBFE_6A7A_00 1.00000000000 x 2^11 * 1.01100111100 x 2^1 + -1.01111111110 x 2^11 = 1.01001111010 x 2^11
+4240_2EEF_123F_2c_356D_1 // f16_mulAdd_rd.tv line 2299998 4240_2EEF_123F_356D_01 1.01001000000 x 2^1 * 1.01011101111 x 2^-4 + 1.01000111111 x 2^-11 = 1.00101101101 x 2^-2
+// Skipped denorm f16_mulAdd_rd.tv line 2349998 0074_F0AE_889A_AC40_01 Denorm * -1.00010101110 x 2^13 + -1.00010011010 x 2^-13 = -1.00001000000 x 2^-4
+7C4E_7BFF_43FF_2c_7E4E_0 // f16_mulAdd_rd.tv line 2399998 7C4E_7BFF_43FF_7E4E_10 NaN * 1.01111111111 x 2^15 + 1.01111111111 x 2^1 = NaN
+6BFE_3401_7801_2c_7820_1 // f16_mulAdd_rd.tv line 2449998 6BFE_3401_7801_7820_01 1.01111111110 x 2^11 * 1.00000000001 x 2^-2 + 1.00000000001 x 2^15 = 1.00000100000 x 2^15
+6BFE_23FA_C010_2c_53B7_1 // f16_mulAdd_rd.tv line 2499998 6BFE_23FA_C010_53B7_01 1.01111111110 x 2^11 * 1.01111111010 x 2^-7 + -1.00000010000 x 2^1 = 1.01110110111 x 2^5
+5023_8BFF_B801_2c_B812_1 // f16_mulAdd_rd.tv line 2549998 5023_8BFF_B801_B812_01 1.00000100011 x 2^5 * -1.01111111111 x 2^-13 + -1.00000000001 x 2^-1 = -1.00000010010 x 2^-1
+FA01_43FF_EA16_2c_FC00_5 // f16_mulAdd_rd.tv line 2599998 FA01_43FF_EA16_FC00_05 -1.01000000001 x 2^15 * 1.01111111111 x 2^1 + -1.01000010110 x 2^11 = -INF
+// Skipped denorm f16_mulAdd_rd.tv line 2649998 7BFF_0001_407E_407F_01 1.01111111111 x 2^15 * Denorm + 1.00001111110 x 2^1 = 1.00001111111 x 2^1
+// Skipped denorm f16_mulAdd_rd.tv line 2699998 7BFF_0106_07FE_3C17_01 1.01111111111 x 2^15 * Denorm + 1.01111111110 x 2^-14 = 1.00000010111 x 2^0
+BCFA_B081_AD7F_2c_2DB5_1 // f16_mulAdd_rd.tv line 2749998 BCFA_B081_AD7F_2DB5_01 -1.00011111010 x 2^0 * -1.00010000001 x 2^-3 + -1.00101111111 x 2^-4 = 1.00110110101 x 2^-4
+42F6_8B87_7C52_2c_7E52_0 // f16_mulAdd_rd.tv line 2799998 42F6_8B87_7C52_7E52_10 1.01011110110 x 2^1 * -1.01110000111 x 2^-13 + NaN = NaN
+6C47_EBFF_7FFF_2c_7FFF_0 // f16_mulAdd_rd.tv line 2849998 6C47_EBFF_7FFF_7FFF_00 1.00001000111 x 2^12 * -1.01111111111 x 2^11 + NaN = NaN
+7C01_9001_9001_2c_7E01_0 // f16_mulAdd_rd.tv line 2899998 7C01_9001_9001_7E01_10 NaN * -1.00000000001 x 2^-11 + -1.00000000001 x 2^-11 = NaN
+7FFF_4C06_B843_2c_7FFF_0 // f16_mulAdd_rd.tv line 2949998 7FFF_4C06_B843_7FFF_00 NaN * 1.00000000110 x 2^4 + -1.00001000011 x 2^-1 = NaN
+BC20_93DE_E801_2c_E801_1 // f16_mulAdd_rd.tv line 2999998 BC20_93DE_E801_E801_01 -1.00000100000 x 2^0 * -1.01111011110 x 2^-11 + -1.00000000001 x 2^11 = -1.00000000001 x 2^11
+0FFF_BFFE_F427_2c_F428_1 // f16_mulAdd_rd.tv line 3049998 0FFF_BFFE_F427_F428_01 1.01111111111 x 2^-12 * -1.01111111110 x 2^0 + -1.00000100111 x 2^14 = -1.00000101000 x 2^14
+// Skipped denorm f16_mulAdd_rd.tv line 3099998 8000_7FFF_B2FE_7FFF_00 -Denorm * NaN + -1.01011111110 x 2^-3 = NaN
+// Skipped denorm f16_mulAdd_rd.tv line 3149998 8001_0B9F_3FFE_3FFD_01 -Denorm * 1.01110011111 x 2^-13 + 1.01111111110 x 2^0 = 1.01111111101 x 2^0
+751F_3AFC_365D_2c_7478_1 // f16_mulAdd_rd.tv line 3199998 751F_3AFC_365D_7478_01 1.00100011111 x 2^14 * 1.01011111100 x 2^-1 + 1.01001011101 x 2^-2 = 1.00001111000 x 2^14
+8482_3C86_CB10_2c_CB11_1 // f16_mulAdd_rd.tv line 3249998 8482_3C86_CB10_CB11_01 -1.00010000010 x 2^-14 * 1.00010000110 x 2^0 + -1.01100010000 x 2^3 = -1.01100010001 x 2^3
+2BF9_47FF_B7FF_2c_9700_1 // f16_mulAdd_rd.tv line 3299998 2BF9_47FF_B7FF_9700_01 1.01111111001 x 2^-5 * 1.01111111111 x 2^2 + -1.01111111111 x 2^-2 = -1.01100000000 x 2^-10
+8400_0401_C001_2c_C002_1 // f16_mulAdd_rd.tv line 3349998 8400_0401_C001_C002_01 -1.00000000000 x 2^-14 * 1.00000000001 x 2^-14 + -1.00000000001 x 2^1 = -1.00000000010 x 2^1
+8400_48FF_3FFA_2c_3FF9_1 // f16_mulAdd_rd.tv line 3399998 8400_48FF_3FFA_3FF9_01 -1.00000000000 x 2^-14 * 1.00011111111 x 2^3 + 1.01111111010 x 2^0 = 1.01111111001 x 2^0
+D7C7_0B40_0401_2c_A709_1 // f16_mulAdd_rd.tv line 3449998 D7C7_0B40_0401_A709_01 -1.01111000111 x 2^6 * 1.01101000000 x 2^-13 + 1.00000000001 x 2^-14 = -1.01100001001 x 2^-6
+4411_3BFE_4818_2c_4A1F_1 // f16_mulAdd_rd.tv line 3499998 4411_3BFE_4818_4A1F_01 1.00000010001 x 2^2 * 1.01111111110 x 2^-1 + 1.00000011000 x 2^3 = 1.01000011111 x 2^3
+87FF_FBFF_DFAF_2c_DF90_1 // f16_mulAdd_rd.tv line 3549998 87FF_FBFF_DFAF_DF90_01 -1.01111111111 x 2^-14 * -1.01111111111 x 2^15 + -1.01110101111 x 2^8 = -1.01110010000 x 2^8
+87FE_BBDB_7BFE_2c_7BFE_1 // f16_mulAdd_rd.tv line 3599998 87FE_BBDB_7BFE_7BFE_01 -1.01111111110 x 2^-14 * -1.01111011011 x 2^-1 + 1.01111111110 x 2^15 = 1.01111111110 x 2^15
+7662_B80C_E47B_2c_F305_1 // f16_mulAdd_rd.tv line 3649998 7662_B80C_E47B_F305_01 1.01001100010 x 2^14 * -1.00000001100 x 2^-1 + -1.00001111011 x 2^10 = -1.01100000101 x 2^13
+B580_267F_B3B7_2c_B3FF_1 // f16_mulAdd_rd.tv line 3699998 B580_267F_B3B7_B3FF_01 -1.00110000000 x 2^-2 * 1.01001111111 x 2^-6 + -1.01110110111 x 2^-3 = -1.01111111111 x 2^-3
+79FA_C3FF_C7FF_2c_FC00_5 // f16_mulAdd_rd.tv line 3749998 79FA_C3FF_C7FF_FC00_05 1.00111111010 x 2^15 * -1.01111111111 x 2^1 + -1.01111111111 x 2^2 = -INF
+// Skipped denorm f16_mulAdd_rd.tv line 3799998 93FF_8001_FC01_FE01_10 -1.01111111111 x 2^-11 * -Denorm + NaN = NaN
+93FE_BD9D_2D35_2c_2D4B_1 // f16_mulAdd_rd.tv line 3849998 93FE_BD9D_2D35_2D4B_01 -1.01111111110 x 2^-11 * -1.00110011101 x 2^0 + 1.00100110101 x 2^-4 = 1.00101001011 x 2^-4
+F417_2FD1_3C01_2c_E7FD_1 // f16_mulAdd_rd.tv line 3899998 F417_2FD1_3C01_E7FD_01 -1.00000010111 x 2^14 * 1.01111010001 x 2^-4 + 1.00000000001 x 2^0 = -1.01111111101 x 2^10
+360F_B7FE_BFFD_2c_C060_1 // f16_mulAdd_rd.tv line 3949998 360F_B7FE_BFFD_C060_01 1.01000001111 x 2^-2 * -1.01111111110 x 2^-2 + -1.01111111101 x 2^0 = -1.00001100000 x 2^1
+B401_6BFF_A827_2c_E401_1 // f16_mulAdd_rd.tv line 3999998 B401_6BFF_A827_E401_01 -1.00000000001 x 2^-2 * 1.01111111111 x 2^11 + -1.00000100111 x 2^-5 = -1.00000000001 x 2^10
+B7FF_3C12_93FE_2c_B814_1 // f16_mulAdd_rd.tv line 4049998 B7FF_3C12_93FE_B814_01 -1.01111111111 x 2^-2 * 1.00000010010 x 2^0 + -1.01111111110 x 2^-11 = -1.00000010100 x 2^-1
+0607_0A6D_F440_2c_F440_1 // f16_mulAdd_rd.tv line 4099998 0607_0A6D_F440_F440_01 1.01000000111 x 2^-14 * 1.01001101101 x 2^-13 + -1.00001000000 x 2^14 = -1.00001000000 x 2^14
+E7FF_2080_BADA_2c_CCB7_1 // f16_mulAdd_rd.tv line 4149998 E7FF_2080_BADA_CCB7_01 -1.01111111111 x 2^10 * 1.00010000000 x 2^-7 + -1.01011011010 x 2^-1 = -1.00010110111 x 2^4
+// Skipped denorm f16_mulAdd_rd.tv line 4199998 F06F_3FFE_03FF_F46E_01 -1.00001101111 x 2^13 * 1.01111111110 x 2^0 + Denorm = -1.00001101110 x 2^14
+B800_FFFF_3401_2c_FFFF_0 // f16_mulAdd_rd.tv line 4249998 B800_FFFF_3401_FFFF_00 -1.00000000000 x 2^-1 * NaN + 1.00000000001 x 2^-2 = NaN
+B801_EBE0_F9FF_2c_F9C0_1 // f16_mulAdd_rd.tv line 4299998 B801_EBE0_F9FF_F9C0_01 -1.00000000001 x 2^-1 * -1.01111100000 x 2^11 + -1.00111111111 x 2^15 = -1.00111000000 x 2^15
+2DD3_B478_7801_2c_7800_1 // f16_mulAdd_rd.tv line 4349998 2DD3_B478_7801_7800_01 1.00111010011 x 2^-4 * -1.00001111000 x 2^-2 + 1.00000000001 x 2^15 = 1.00000000000 x 2^15
+EBDB_13FE_5F06_2c_5EF6_1 // f16_mulAdd_rd.tv line 4399998 EBDB_13FE_5F06_5EF6_01 -1.01111011011 x 2^11 * 1.01111111110 x 2^-11 + 1.01100000110 x 2^8 = 1.01011110110 x 2^8
+BBFE_C7FF_E7FC_2c_E7F5_1 // f16_mulAdd_rd.tv line 4449998 BBFE_C7FF_E7FC_E7F5_01 -1.01111111110 x 2^-1 * -1.01111111111 x 2^2 + -1.01111111100 x 2^10 = -1.01111110101 x 2^10
+BC00_30BF_C3FE_2c_C425_1 // f16_mulAdd_rd.tv line 4499998 BC00_30BF_C3FE_C425_01 -1.00000000000 x 2^0 * 1.00010111111 x 2^-3 + -1.01111111110 x 2^1 = -1.00000100101 x 2^2
+ABCF_397E_216D_2c_A802_1 // f16_mulAdd_rd.tv line 4549998 ABCF_397E_216D_A802_01 -1.01111001111 x 2^-5 * 1.00101111110 x 2^-1 + 1.00101101101 x 2^-7 = -1.00000000010 x 2^-5
+424C_CC7A_0BDB_2c_D30D_1 // f16_mulAdd_rd.tv line 4599998 424C_CC7A_0BDB_D30D_01 1.01001001100 x 2^1 * -1.00001111010 x 2^4 + 1.01111011011 x 2^-13 = -1.01100001101 x 2^5
+241D_BBFE_3BFF_2c_3BDE_1 // f16_mulAdd_rd.tv line 4649998 241D_BBFE_3BFF_3BDE_01 1.00000011101 x 2^-6 * -1.01111111110 x 2^-1 + 1.01111111111 x 2^-1 = 1.01111011110 x 2^-1
+BFFE_7BFF_4401_2c_FC00_5 // f16_mulAdd_rd.tv line 4699998 BFFE_7BFF_4401_FC00_05 -1.01111111110 x 2^0 * 1.01111111111 x 2^15 + 1.00000000001 x 2^2 = -INF
+C000_882F_4B10_2c_4B10_1 // f16_mulAdd_rd.tv line 4749998 C000_882F_4B10_4B10_01 -1.00000000000 x 2^1 * -1.00000101111 x 2^-13 + 1.01100010000 x 2^3 = 1.01100010000 x 2^3
+3A4E_B929_9001_2c_B813_1 // f16_mulAdd_rd.tv line 4799998 3A4E_B929_9001_B813_01 1.01001001110 x 2^-1 * -1.00100101001 x 2^-1 + -1.00000000001 x 2^-11 = -1.00000010011 x 2^-1
+C290_87FE_FD07_2c_FF07_0 // f16_mulAdd_rd.tv line 4849998 C290_87FE_FD07_FF07_10 -1.01010010000 x 2^1 * -1.01111111110 x 2^-14 + NaN = NaN
+C3FF_43FF_380D_2c_CBBE_1 // f16_mulAdd_rd.tv line 4899998 C3FF_43FF_380D_CBBE_01 -1.01111111111 x 2^1 * 1.01111111111 x 2^1 + 1.00000001101 x 2^-1 = -1.01110111110 x 2^3
+C3FE_28E0_FFFE_2c_FFFE_0 // f16_mulAdd_rd.tv line 4949998 C3FE_28E0_FFFE_FFFE_00 -1.01111111110 x 2^1 * 1.00011100000 x 2^-5 + NaN = NaN
+CFE3_4B04_CF81_2c_DF63_1 // f16_mulAdd_rd.tv line 4999998 CFE3_4B04_CF81_DF63_01 -1.01111100011 x 2^4 * 1.01100000100 x 2^3 + -1.01110000001 x 2^4 = -1.01101100011 x 2^8
+120A_BBAF_C6DF_2c_C6E0_1 // f16_mulAdd_rd.tv line 5049998 120A_BBAF_C6DF_C6E0_01 1.01000001010 x 2^-11 * -1.01110101111 x 2^-1 + -1.01011011111 x 2^2 = -1.01011100000 x 2^2
+2CFF_37FE_6BFF_2c_6BFF_1 // f16_mulAdd_rd.tv line 5099998 2CFF_37FE_6BFF_6BFF_01 1.00011111111 x 2^-4 * 1.01111111110 x 2^-2 + 1.01111111111 x 2^11 = 1.01111111111 x 2^11
+// Skipped denorm f16_mulAdd_rd.tv line 5149998 C401_EBFF_8001_7400_01 -1.00000000001 x 2^2 * -1.01111111111 x 2^11 + -Denorm = 1.00000000000 x 2^14
+C7FF_E804_4C50_2c_7404_1 // f16_mulAdd_rd.tv line 5199998 C7FF_E804_4C50_7404_01 -1.01111111111 x 2^2 * -1.00000000100 x 2^11 + 1.00001010000 x 2^4 = 1.00000000100 x 2^14
+350C_5307_C001_2c_4BDD_1 // f16_mulAdd_rd.tv line 5249998 350C_5307_C001_4BDD_01 1.00100001100 x 2^-2 * 1.01100000111 x 2^5 + -1.00000000001 x 2^1 = 1.01111011101 x 2^3
+// Skipped denorm f16_mulAdd_rd.tv line 5299998 F3F0_03FE_C83F_C8BE_01 -1.01111110000 x 2^13 * Denorm + -1.00000111111 x 2^3 = -1.00010111110 x 2^3
+E800_BFFE_53FE_2c_6C0E_1 // f16_mulAdd_rd.tv line 5349998 E800_BFFE_53FE_6C0E_01 -1.00000000000 x 2^11 * -1.01111111110 x 2^0 + 1.01111111110 x 2^5 = 1.00000001110 x 2^12
+E801_B5BF_37FE_2c_61C1_1 // f16_mulAdd_rd.tv line 5399998 E801_B5BF_37FE_61C1_01 -1.00000000001 x 2^11 * -1.00110111111 x 2^-2 + 1.01111111110 x 2^-2 = 1.00111000001 x 2^9
+4422_C01B_8807_2c_C83E_1 // f16_mulAdd_rd.tv line 5449998 4422_C01B_8807_C83E_01 1.00000100010 x 2^2 * -1.00000011011 x 2^1 + -1.00000000111 x 2^-13 = -1.00000111110 x 2^3
+367F_4633_86FD_2c_4108_1 // f16_mulAdd_rd.tv line 5499998 367F_4633_86FD_4108_01 1.01001111111 x 2^-2 * 1.01000110011 x 2^2 + -1.01011111101 x 2^-14 = 1.00100001000 x 2^1
+D88E_93FE_87FF_2c_308B_1 // f16_mulAdd_rd.tv line 5549998 D88E_93FE_87FF_308B_01 -1.00010001110 x 2^7 * -1.01111111110 x 2^-11 + -1.01111111111 x 2^-14 = 1.00010001011 x 2^-3
+F800_47FF_B801_2c_FC00_5 // f16_mulAdd_rd.tv line 5599998 F800_47FF_B801_FC00_05 -1.00000000000 x 2^15 * 1.01111111111 x 2^2 + -1.00000000001 x 2^-1 = -INF
+F801_BDFC_740C_2c_7BFF_5 // f16_mulAdd_rd.tv line 5649998 F801_BDFC_740C_7BFF_05 -1.00000000001 x 2^15 * -1.00111111100 x 2^0 + 1.00000001100 x 2^14 = 1.01111111111 x 2^15
+11F7_3C60_FC01_2c_FE01_0 // f16_mulAdd_rd.tv line 5699998 11F7_3C60_FC01_FE01_10 1.00111110111 x 2^-11 * 1.00001100000 x 2^0 + NaN = NaN
+// Skipped denorm f16_mulAdd_rd.tv line 5749998 CBF0_8000_8C11_8C11_00 -1.01111110000 x 2^3 * -Denorm + -1.00000010001 x 2^-12 = -1.00000010001 x 2^-12
+FBFE_3BFE_B7E4_2c_FBFD_1 // f16_mulAdd_rd.tv line 5799998 FBFE_3BFE_B7E4_FBFD_01 -1.01111111110 x 2^15 * 1.01111111110 x 2^-1 + -1.01111100100 x 2^-2 = -1.01111111101 x 2^15
+FBFE_F8FA_47FE_2c_7BFF_5 // f16_mulAdd_rd.tv line 5849998 FBFE_F8FA_47FE_7BFF_05 -1.01111111110 x 2^15 * -1.00011111010 x 2^15 + 1.01111111110 x 2^2 = 1.01111111111 x 2^15
+B40F_CA3F_B7FE_2c_4156_1 // f16_mulAdd_rd.tv line 5899998 B40F_CA3F_B7FE_4156_01 -1.00000001111 x 2^-2 * -1.01000111111 x 2^3 + -1.01111111110 x 2^-2 = 1.00101010110 x 2^1
+A1FE_3B0F_47CF_2c_47CC_1 // f16_mulAdd_rd.tv line 5949998 A1FE_3B0F_47CF_47CC_01 -1.00111111110 x 2^-7 * 1.01100001111 x 2^-1 + 1.01111001111 x 2^2 = 1.01111001100 x 2^2
+BC04_07FE_BFFF_2c_C000_1 // f16_mulAdd_rd.tv line 5999998 BC04_07FE_BFFF_C000_01 -1.00000000100 x 2^0 * 1.01111111110 x 2^-14 + -1.01111111111 x 2^0 = -1.00000000000 x 2^1
+FFFF_C3FF_E801_2c_FFFF_0 // f16_mulAdd_rd.tv line 6049998 FFFF_C3FF_E801_FFFF_00 NaN * -1.01111111111 x 2^1 + -1.00000000001 x 2^11 = NaN
+FFFE_697C_D7DB_2c_FFFE_0 // f16_mulAdd_rd.tv line 6099998 FFFE_697C_D7DB_FFFE_00 NaN * 1.00101111100 x 2^11 + -1.01111011011 x 2^6 = NaN
+
+////////// Testcases from f16_mulAdd_ru.tv of type mulAdd rounding mode 3
+0000_BBFE_0778_3c_0778_0 // f16_mulAdd_ru.tv line 49997 0000_BBFE_0778_0778_00 0 * -1.01111111110 x 2^-1 + 1.01101111000 x 2^-14 = 1.01101111000 x 2^-14
+// Skipped denorm f16_mulAdd_ru.tv line 99997 0001_92FC_3FFF_3FFF_01 Denorm * -1.01011111100 x 2^-11 + 1.01111111111 x 2^0 = 1.01111111111 x 2^0
+// Skipped denorm f16_mulAdd_ru.tv line 149997 838A_3C3D_45FB_45FB_01 -Denorm * 1.00000111101 x 2^0 + 1.00111111011 x 2^2 = 1.00111111011 x 2^2
+786E_D80F_91B8_3c_FBFF_5 // f16_mulAdd_ru.tv line 199997 786E_D80F_91B8_FBFF_05 1.00001101110 x 2^15 * -1.00000001111 x 2^7 + -1.00110111000 x 2^-11 = -1.01111111111 x 2^15
+A077_87FE_B401_3c_B400_1 // f16_mulAdd_ru.tv line 249997 A077_87FE_B401_B400_01 -1.00001110111 x 2^-7 * -1.01111111110 x 2^-14 + -1.00000000001 x 2^-2 = -1.00000000000 x 2^-2
+0400_43FF_C000_3c_BFFF_1 // f16_mulAdd_ru.tv line 299997 0400_43FF_C000_BFFF_01 1.00000000000 x 2^-14 * 1.01111111111 x 2^1 + -1.00000000000 x 2^1 = -1.01111111111 x 2^0
+0401_0BFF_243B_3c_243C_1 // f16_mulAdd_ru.tv line 349997 0401_0BFF_243B_243C_01 1.00000000001 x 2^-14 * 1.01111111111 x 2^-13 + 1.00000111011 x 2^-6 = 1.00000111100 x 2^-6
+2847_B3E7_0400_3c_A031_1 // f16_mulAdd_ru.tv line 399997 2847_B3E7_0400_A031_01 1.00001000111 x 2^-5 * -1.01111100111 x 2^-3 + 1.00000000000 x 2^-14 = -1.00000110001 x 2^-7
+// Skipped denorm f16_mulAdd_ru.tv line 449997 F43D_7C00_810E_FC00_00 -1.00000111101 x 2^14 * INF + -Denorm = -INF
+07FE_37FE_A406_3c_A402_1 // f16_mulAdd_ru.tv line 499997 07FE_37FE_A406_A402_01 1.01111111110 x 2^-14 * 1.01111111110 x 2^-2 + -1.00000000110 x 2^-6 = -1.00000000010 x 2^-6
+07FE_BDB7_7BFF_3c_7BFF_1 // f16_mulAdd_ru.tv line 549997 07FE_BDB7_7BFF_7BFF_01 1.01111111110 x 2^-14 * -1.00110110111 x 2^0 + 1.01111111111 x 2^15 = 1.01111111111 x 2^15
+FB84_2377_F87F_3c_F89B_1 // f16_mulAdd_ru.tv line 599997 FB84_2377_F87F_F89B_01 -1.01110000100 x 2^15 * 1.01101110111 x 2^-7 + -1.00001111111 x 2^15 = -1.00010011011 x 2^15
+A3A2_3CF7_B610_3c_B65B_1 // f16_mulAdd_ru.tv line 649997 A3A2_3CF7_B610_B65B_01 -1.01110100010 x 2^-7 * 1.00011110111 x 2^0 + -1.01000010000 x 2^-2 = -1.01001011011 x 2^-2
+// Skipped denorm f16_mulAdd_ru.tv line 699997 BC06_03FE_C401_C401_01 -1.00000000110 x 2^0 * Denorm + -1.00000000001 x 2^2 = -1.00000000001 x 2^2
+13FF_BFFF_FC00_3c_FC00_0 // f16_mulAdd_ru.tv line 749997 13FF_BFFF_FC00_FC00_00 1.01111111111 x 2^-11 * -1.01111111111 x 2^0 + -INF = -INF
+13FE_8420_3A2B_3c_3A2B_1 // f16_mulAdd_ru.tv line 799997 13FE_8420_3A2B_3A2B_01 1.01111111110 x 2^-11 * -1.00000100000 x 2^-14 + 1.01000101011 x 2^-1 = 1.01000101011 x 2^-1
+CBCE_3BC0_3C00_3c_CB0F_1 // f16_mulAdd_ru.tv line 849997 CBCE_3BC0_3C00_CB0F_01 -1.01111001110 x 2^3 * 1.01111000000 x 2^-1 + 1.00000000000 x 2^0 = -1.01100001111 x 2^3
+D33F_F800_52FF_3c_7C00_5 // f16_mulAdd_ru.tv line 899997 D33F_F800_52FF_7C00_05 -1.01100111111 x 2^5 * -1.00000000000 x 2^15 + 1.01011111111 x 2^5 = INF
+3401_93FE_4FAF_3c_4FAF_1 // f16_mulAdd_ru.tv line 949997 3401_93FE_4FAF_4FAF_01 1.00000000001 x 2^-2 * -1.01111111110 x 2^-11 + 1.01110101111 x 2^4 = 1.01110101111 x 2^4
+37FF_3402_93FF_3c_2FF4_1 // f16_mulAdd_ru.tv line 999997 37FF_3402_93FF_2FF4_01 1.01111111111 x 2^-2 * 1.00000000010 x 2^-2 + -1.01111111111 x 2^-11 = 1.01111110100 x 2^-4
+EADE_ED3B_6000_3c_7C00_5 // f16_mulAdd_ru.tv line 1049997 EADE_ED3B_6000_7C00_05 -1.01011011110 x 2^11 * -1.00100111011 x 2^12 + 1.00000000000 x 2^9 = INF
+2C7A_3BA0_BBDF_3c_BB56_1 // f16_mulAdd_ru.tv line 1099997 2C7A_3BA0_BBDF_BB56_01 1.00001111010 x 2^-4 * 1.01110100000 x 2^-1 + -1.01111011111 x 2^-1 = -1.01101010110 x 2^-1
+// Skipped denorm f16_mulAdd_ru.tv line 1149997 DD9A_8000_0001_0001_00 -1.00110011010 x 2^8 * -Denorm + Denorm = Denorm
+3801_3BFE_3400_3c_3A00_1 // f16_mulAdd_ru.tv line 1199997 3801_3BFE_3400_3A00_01 1.00000000001 x 2^-1 * 1.01111111110 x 2^-1 + 1.00000000000 x 2^-2 = 1.01000000000 x 2^-1
+3801_C81E_D907_3c_D927_1 // f16_mulAdd_ru.tv line 1249997 3801_C81E_D907_D927_01 1.00000000001 x 2^-1 * -1.00000011110 x 2^3 + -1.00100000111 x 2^7 = -1.00100100111 x 2^7
+31C8_B7EF_7800_3c_7800_1 // f16_mulAdd_ru.tv line 1299997 31C8_B7EF_7800_7800_01 1.00111001000 x 2^-3 * -1.01111101111 x 2^-2 + 1.00000000000 x 2^15 = 1.00000000000 x 2^15
+545A_6800_BDEF_3c_7C00_5 // f16_mulAdd_ru.tv line 1349997 545A_6800_BDEF_7C00_05 1.00001011010 x 2^6 * 1.00000000000 x 2^11 + -1.00111101111 x 2^0 = INF
+3C00_07FE_285F_3c_2863_1 // f16_mulAdd_ru.tv line 1399997 3C00_07FE_285F_2863_01 1.00000000000 x 2^0 * 1.01111111110 x 2^-14 + 1.00001011111 x 2^-5 = 1.00001100011 x 2^-5
+3C00_D790_C3FF_3c_D7CF_1 // f16_mulAdd_ru.tv line 1449997 3C00_D790_C3FF_D7CF_01 1.00000000000 x 2^0 * -1.01110010000 x 2^6 + -1.01111111111 x 2^1 = -1.01111001111 x 2^6
+CC0D_C6FF_238E_3c_5716_1 // f16_mulAdd_ru.tv line 1499997 CC0D_C6FF_238E_5716_01 -1.00000001101 x 2^4 * -1.01011111111 x 2^2 + 1.01110001110 x 2^-7 = 1.01100010110 x 2^6
+4BC2_9060_C783_3c_C785_1 // f16_mulAdd_ru.tv line 1549997 4BC2_9060_C783_C785_01 1.01111000010 x 2^3 * -1.00001100000 x 2^-11 + -1.01110000011 x 2^2 = -1.01110000101 x 2^2
+CE06_FC00_3801_3c_7C00_0 // f16_mulAdd_ru.tv line 1599997 CE06_FC00_3801_7C00_00 -1.01000000110 x 2^4 * -INF + 1.00000000001 x 2^-1 = INF
+3FFE_B7FE_4400_3c_4201_1 // f16_mulAdd_ru.tv line 1649997 3FFE_B7FE_4400_4201_01 1.01111111110 x 2^0 * -1.01111111110 x 2^-2 + 1.00000000000 x 2^2 = 1.01000000001 x 2^1
+4000_ABDC_48D0_3c_48C1_1 // f16_mulAdd_ru.tv line 1699997 4000_ABDC_48D0_48C1_01 1.00000000000 x 2^1 * -1.01111011100 x 2^-5 + 1.00011010000 x 2^3 = 1.00011000001 x 2^3
+C880_CFF8_9000_3c_5C7C_1 // f16_mulAdd_ru.tv line 1749997 C880_CFF8_9000_5C7C_01 -1.00010000000 x 2^3 * -1.01111111000 x 2^4 + -1.00000000000 x 2^-11 = 1.00001111100 x 2^8
+C843_C400_F410_3c_F40D_1 // f16_mulAdd_ru.tv line 1799997 C843_C400_F410_F40D_01 -1.00001000011 x 2^3 * -1.00000000000 x 2^2 + -1.00000010000 x 2^14 = -1.00000001101 x 2^14
+// Skipped denorm f16_mulAdd_ru.tv line 1849997 43FF_83FE_7623_7623_01 1.01111111111 x 2^1 * -Denorm + 1.01000100011 x 2^14 = 1.01000100011 x 2^14
+43FE_C5EA_FFFF_3c_FFFF_0 // f16_mulAdd_ru.tv line 1899997 43FE_C5EA_FFFF_FFFF_00 1.01111111110 x 2^1 * -1.00111101010 x 2^2 + NaN = NaN
+C415_2360_FBEC_3c_FBEC_1 // f16_mulAdd_ru.tv line 1949997 C415_2360_FBEC_FBEC_01 -1.00000010101 x 2^2 * 1.01101100000 x 2^-7 + -1.01111101100 x 2^15 = -1.01111101100 x 2^15
+E7BE_BC0A_4422_3c_67D6_1 // f16_mulAdd_ru.tv line 1999997 E7BE_BC0A_4422_67D6_01 -1.01110111110 x 2^10 * -1.00000001010 x 2^0 + 1.00000100010 x 2^2 = 1.01111010110 x 2^10
+4A3A_7800_6801_3c_7C00_5 // f16_mulAdd_ru.tv line 2049997 4A3A_7800_6801_7C00_05 1.01000111010 x 2^3 * 1.00000000000 x 2^15 + 1.00000000001 x 2^11 = INF
+// Skipped denorm f16_mulAdd_ru.tv line 2099997 47FF_13FE_8000_1FFE_01 1.01111111111 x 2^2 * 1.01111111110 x 2^-11 + -Denorm = 1.01111111110 x 2^-8
+47FF_BEFB_463B_3c_C7B9_1 // f16_mulAdd_ru.tv line 2149997 47FF_BEFB_463B_C7B9_01 1.01111111111 x 2^2 * -1.01011111011 x 2^0 + 1.01000111011 x 2^2 = -1.01110111001 x 2^2
+ACD3_B753_C000_3c_BFDC_1 // f16_mulAdd_ru.tv line 2199997 ACD3_B753_C000_BFDC_01 -1.00011010011 x 2^-4 * -1.01101010011 x 2^-2 + -1.00000000000 x 2^1 = -1.01111011100 x 2^0
+0403_4000_41FC_3c_41FD_1 // f16_mulAdd_ru.tv line 2249997 0403_4000_41FC_41FD_01 1.00000000011 x 2^-14 * 1.00000000000 x 2^1 + 1.00111111100 x 2^1 = 1.00111111101 x 2^1
+6801_0000_081D_3c_081D_0 // f16_mulAdd_ru.tv line 2299997 6801_0000_081D_081D_00 1.00000000001 x 2^11 * 0 + 1.00000011101 x 2^-13 = 1.00000011101 x 2^-13
+6801_1920_37FF_3c_45A2_1 // f16_mulAdd_ru.tv line 2349997 6801_1920_37FF_45A2_01 1.00000000001 x 2^11 * 1.00100100000 x 2^-9 + 1.01111111111 x 2^-2 = 1.00110100010 x 2^2
+37E0_8807_8448_3c_881F_1 // f16_mulAdd_ru.tv line 2399997 37E0_8807_8448_881F_01 1.01111100000 x 2^-2 * -1.00000000111 x 2^-13 + -1.00001001000 x 2^-14 = -1.00000011111 x 2^-13
+07F9_3202_31C3_3c_31C4_1 // f16_mulAdd_ru.tv line 2449997 07F9_3202_31C3_31C4_01 1.01111111001 x 2^-14 * 1.01000000010 x 2^-3 + 1.00111000011 x 2^-3 = 1.00111000100 x 2^-3
+BB83_E800_8401_3c_6783_1 // f16_mulAdd_ru.tv line 2499997 BB83_E800_8401_6783_01 -1.01110000011 x 2^-1 * -1.00000000000 x 2^11 + -1.00000000001 x 2^-14 = 1.01110000011 x 2^10
+7800_87FE_B800_3c_C47F_0 // f16_mulAdd_ru.tv line 2549997 7800_87FE_B800_C47F_00 1.00000000000 x 2^15 * -1.01111111110 x 2^-14 + -1.00000000000 x 2^-1 = -1.00001111111 x 2^2
+7801_4BF2_4C8E_3c_7C00_5 // f16_mulAdd_ru.tv line 2599997 7801_4BF2_4C8E_7C00_05 1.00000000001 x 2^15 * 1.01111110010 x 2^3 + 1.00010001110 x 2^4 = INF
+3C7E_123F_FC00_3c_FC00_0 // f16_mulAdd_ru.tv line 2649997 3C7E_123F_FC00_FC00_00 1.00001111110 x 2^0 * 1.01000111111 x 2^-11 + -INF = -INF
+// Skipped denorm f16_mulAdd_ru.tv line 2699997 8165_BC01_FBFF_FBFE_01 -Denorm * -1.00000000001 x 2^0 + -1.01111111111 x 2^15 = -1.01111111110 x 2^15
+7BFE_7C00_FC03_3c_FE03_0 // f16_mulAdd_ru.tv line 2749997 7BFE_7C00_FC03_FE03_10 1.01111111110 x 2^15 * INF + NaN = NaN
+7C00_C03E_47FF_3c_FC00_0 // f16_mulAdd_ru.tv line 2799997 7C00_C03E_47FF_FC00_00 INF * -1.00000111110 x 2^1 + 1.01111111111 x 2^2 = -INF
+3FF4_4907_3044_3c_4D08_1 // f16_mulAdd_ru.tv line 2849997 3FF4_4907_3044_4D08_01 1.01111110100 x 2^0 * 1.00100000111 x 2^3 + 1.00001000100 x 2^-3 = 1.00100001000 x 2^4
+37E0_4CBA_3201_3c_48C0_1 // f16_mulAdd_ru.tv line 2899997 37E0_4CBA_3201_48C0_01 1.01111100000 x 2^-2 * 1.00010111010 x 2^4 + 1.01000000001 x 2^-3 = 1.00011000000 x 2^3
+F801_4400_BC01_3c_FBFF_5 // f16_mulAdd_ru.tv line 2949997 F801_4400_BC01_FBFF_05 -1.00000000001 x 2^15 * 1.00000000000 x 2^2 + -1.00000000001 x 2^0 = -1.01111111111 x 2^15
+// Skipped denorm f16_mulAdd_ru.tv line 2999997 7FFE_03FE_E800_7FFE_00 NaN * Denorm + -1.00000000000 x 2^11 = NaN
+7FFE_0A01_43F8_3c_7FFE_0 // f16_mulAdd_ru.tv line 3049997 7FFE_0A01_43F8_7FFE_00 NaN * 1.01000000001 x 2^-13 + 1.01111111000 x 2^1 = NaN
+386F_4404_3400_3c_40F4_1 // f16_mulAdd_ru.tv line 3099997 386F_4404_3400_40F4_01 1.00001101111 x 2^-1 * 1.00000000100 x 2^2 + 1.00000000000 x 2^-2 = 1.00011110100 x 2^1
+BBFB_3801_187F_3c_B7F4_1 // f16_mulAdd_ru.tv line 3149997 BBFB_3801_187F_B7F4_01 -1.01111111011 x 2^-1 * 1.00000000001 x 2^-1 + 1.00001111111 x 2^-9 = -1.01111110100 x 2^-2
+// Skipped denorm f16_mulAdd_ru.tv line 3199997 8001_F800_B7FF_B7F7_00 -Denorm * -1.00000000000 x 2^15 + -1.01111111111 x 2^-2 = -1.01111110111 x 2^-2
+// Skipped denorm f16_mulAdd_ru.tv line 3249997 83FF_647F_83FF_AC7E_01 -Denorm * 1.00001111111 x 2^10 + -Denorm = -1.00001111110 x 2^-4
+6FDF_8ED4_CC42_3c_CD18_1 // f16_mulAdd_ru.tv line 3299997 6FDF_8ED4_CC42_CD18_01 1.01111011111 x 2^12 * -1.01011010100 x 2^-12 + -1.00001000010 x 2^4 = -1.00100011000 x 2^4
+146F_7BAF_6336_3c_63BF_1 // f16_mulAdd_ru.tv line 3349997 146F_7BAF_6336_63BF_01 1.00001101111 x 2^-10 * 1.01110101111 x 2^15 + 1.01100110110 x 2^9 = 1.01110111111 x 2^9
+B349_C000_F801_3c_F800_1 // f16_mulAdd_ru.tv line 3399997 B349_C000_F801_F800_01 -1.01101001001 x 2^-3 * -1.00000000000 x 2^1 + -1.00000000001 x 2^15 = -1.00000000000 x 2^15
+// Skipped denorm f16_mulAdd_ru.tv line 3449997 8401_8000_0400_0400_00 -1.00000000001 x 2^-14 * -Denorm + 1.00000000000 x 2^-14 = 1.00000000000 x 2^-14
+87FF_93E1_7778_3c_7779_1 // f16_mulAdd_ru.tv line 3499997 87FF_93E1_7778_7779_01 -1.01111111111 x 2^-14 * -1.01111100001 x 2^-11 + 1.01101111000 x 2^14 = 1.01101111001 x 2^14
+3D35_341E_4400_3c_4456_1 // f16_mulAdd_ru.tv line 3549997 3D35_341E_4400_4456_01 1.00100110101 x 2^0 * 1.00000011110 x 2^-2 + 1.00000000000 x 2^2 = 1.00001010110 x 2^2
+3E00_B401_057F_3c_B601_1 // f16_mulAdd_ru.tv line 3599997 3E00_B401_057F_B601_01 1.01000000000 x 2^0 * -1.00000000001 x 2^-2 + 1.00101111111 x 2^-14 = -1.01000000001 x 2^-2
+9000_6800_7C36_3c_7E36_0 // f16_mulAdd_ru.tv line 3649997 9000_6800_7C36_7E36_10 -1.00000000000 x 2^-11 * 1.00000000000 x 2^11 + NaN = NaN
+9001_CFBF_BBFF_3c_BBDF_1 // f16_mulAdd_ru.tv line 3699997 9001_CFBF_BBFF_BBDF_01 -1.00000000001 x 2^-11 * -1.01110111111 x 2^4 + -1.01111111111 x 2^-1 = -1.01111011111 x 2^-1
+7C04_B180_6F81_3c_7E04_0 // f16_mulAdd_ru.tv line 3749997 7C04_B180_6F81_7E04_10 NaN * -1.00110000000 x 2^-3 + 1.01110000001 x 2^12 = NaN
+// Skipped denorm f16_mulAdd_ru.tv line 3799997 D402_86BF_001F_1EC3_01 -1.00000000010 x 2^6 * -1.01010111111 x 2^-14 + Denorm = 1.01011000011 x 2^-8
+07F5_3C01_1001_3c_1100_1 // f16_mulAdd_ru.tv line 3849997 07F5_3C01_1001_1100_01 1.01111110101 x 2^-14 * 1.00000000001 x 2^0 + 1.00000000001 x 2^-11 = 1.00100000000 x 2^-11
+93FE_FC00_3C00_3c_7C00_0 // f16_mulAdd_ru.tv line 3899997 93FE_FC00_3C00_7C00_00 -1.01111111110 x 2^-11 * -INF + 1.00000000000 x 2^0 = INF
+B400_C840_C05F_3c_ABC0_0 // f16_mulAdd_ru.tv line 3949997 B400_C840_C05F_ABC0_00 -1.00000000000 x 2^-2 * -1.00001000000 x 2^3 + -1.00001011111 x 2^1 = -1.01111000000 x 2^-5
+// Skipped denorm f16_mulAdd_ru.tv line 3999997 040B_1040_8000_0001_03 1.00000001011 x 2^-14 * 1.00001000000 x 2^-11 + -Denorm = Denorm
+E7A0_1001_DBD8_3c_DBDF_1 // f16_mulAdd_ru.tv line 4049997 E7A0_1001_DBD8_DBDF_01 -1.01110100000 x 2^10 * 1.00000000001 x 2^-11 + -1.01111011000 x 2^7 = -1.01111011111 x 2^7
+B7FF_C400_CFEC_3c_CF6C_1 // f16_mulAdd_ru.tv line 4099997 B7FF_C400_CFEC_CF6C_01 -1.01111111111 x 2^-2 * -1.00000000000 x 2^2 + -1.01111101100 x 2^4 = -1.01101101100 x 2^4
+B7FE_F7FE_EBFF_3c_71FD_1 // f16_mulAdd_ru.tv line 4149997 B7FE_F7FE_EBFF_71FD_01 -1.01111111110 x 2^-2 * -1.01111111110 x 2^14 + -1.01111111111 x 2^11 = 1.00111111101 x 2^13
+F404_39B1_77FB_3c_7520_1 // f16_mulAdd_ru.tv line 4199997 F404_39B1_77FB_7520_01 -1.00000000100 x 2^14 * 1.00110110001 x 2^-1 + 1.01111111011 x 2^14 = 1.00100100000 x 2^14
+30DF_3603_BFBA_3c_BF7F_1 // f16_mulAdd_ru.tv line 4249997 30DF_3603_BFBA_BF7F_01 1.00011011111 x 2^-3 * 1.01000000011 x 2^-2 + -1.01110111010 x 2^0 = -1.01101111111 x 2^0
+F600_B801_4001_3c_7202_1 // f16_mulAdd_ru.tv line 4299997 F600_B801_4001_7202_01 -1.01000000000 x 2^14 * -1.00000000001 x 2^-1 + 1.00000000001 x 2^1 = 1.01000000010 x 2^13
+BBFF_7800_7800_3c_4C00_0 // f16_mulAdd_ru.tv line 4349997 BBFF_7800_7800_4C00_00 -1.01111111111 x 2^-1 * 1.00000000000 x 2^15 + 1.00000000000 x 2^15 = 1.00000000000 x 2^4
+BBFE_13C2_3BF2_3c_3BF1_1 // f16_mulAdd_ru.tv line 4399997 BBFE_13C2_3BF2_3BF1_01 -1.01111111110 x 2^-1 * 1.01111000010 x 2^-11 + 1.01111110010 x 2^-1 = 1.01111110001 x 2^-1
+77DF_C900_B800_3c_FBFF_5 // f16_mulAdd_ru.tv line 4449997 77DF_C900_B800_FBFF_05 1.01111011111 x 2^14 * -1.00100000000 x 2^3 + -1.00000000000 x 2^-1 = -1.01111111111 x 2^15
+47E7_8401_7FF8_3c_7FF8_0 // f16_mulAdd_ru.tv line 4499997 47E7_8401_7FF8_7FF8_00 1.01111100111 x 2^2 * -1.00000000001 x 2^-14 + NaN = NaN
+BC01_4000_4F9F_3c_4F1F_1 // f16_mulAdd_ru.tv line 4549997 BC01_4000_4F9F_4F1F_01 -1.00000000001 x 2^0 * 1.00000000000 x 2^1 + 1.01110011111 x 2^4 = 1.01100011111 x 2^4
+BFFF_EBFA_07FF_3c_6FFA_1 // f16_mulAdd_ru.tv line 4599997 BFFF_EBFA_07FF_6FFA_01 -1.01111111111 x 2^0 * -1.01111111010 x 2^11 + 1.01111111111 x 2^-14 = 1.01111111010 x 2^12
+5522_FC86_B777_3c_FE86_0 // f16_mulAdd_ru.tv line 4649997 5522_FC86_B777_FE86_10 1.00100100010 x 2^6 * NaN + -1.01101110111 x 2^-2 = NaN
+3502_388E_1322_3c_31BB_1 // f16_mulAdd_ru.tv line 4699997 3502_388E_1322_31BB_01 1.00100000010 x 2^-2 * 1.00010001110 x 2^-1 + 1.01100100010 x 2^-11 = 1.00110111011 x 2^-3
+// Skipped denorm f16_mulAdd_ru.tv line 4749997 014A_3401_7C01_7E01_10 Denorm * 1.00000000001 x 2^-2 + NaN = NaN
+C000_E800_9000_3c_6C00_1 // f16_mulAdd_ru.tv line 4799997 C000_E800_9000_6C00_01 -1.00000000000 x 2^1 * -1.00000000000 x 2^11 + -1.00000000000 x 2^-11 = 1.00000000000 x 2^12
+// Skipped denorm f16_mulAdd_ru.tv line 4849997 C001_B09F_827F_34A0_01 -1.00000000001 x 2^1 * -1.00010011111 x 2^-3 + -Denorm = 1.00010100000 x 2^-2
+ABE7_877F_E800_3c_E7FF_1 // f16_mulAdd_ru.tv line 4899997 ABE7_877F_E800_E7FF_01 -1.01111100111 x 2^-5 * -1.01101111111 x 2^-14 + -1.00000000000 x 2^11 = -1.01111111111 x 2^10
+// Skipped denorm f16_mulAdd_ru.tv line 4949997 4FC0_0001_34FF_3500_01 1.01111000000 x 2^4 * Denorm + 1.00011111111 x 2^-2 = 1.00100000000 x 2^-2
+C3FE_BC01_2C7E_3c_4412_1 // f16_mulAdd_ru.tv line 4999997 C3FE_BC01_2C7E_4412_01 -1.01111111110 x 2^1 * -1.00000000001 x 2^0 + 1.00001111110 x 2^-4 = 1.00000010010 x 2^2
+// Skipped denorm f16_mulAdd_ru.tv line 5049997 C400_0009_3FFF_3FFF_01 -1.00000000000 x 2^2 * Denorm + 1.01111111111 x 2^0 = 1.01111111111 x 2^0
+7694_C44F_8BE2_3c_FBFF_5 // f16_mulAdd_ru.tv line 5099997 7694_C44F_8BE2_FBFF_05 1.01010010100 x 2^14 * -1.00001001111 x 2^2 + -1.01111100010 x 2^-13 = -1.01111111111 x 2^15
+// Skipped denorm f16_mulAdd_ru.tv line 5149997 E5EE_8100_B483_B424_01 -1.00111101110 x 2^10 * -Denorm + -1.00010000011 x 2^-2 = -1.00000100100 x 2^-2
+CCFF_9001_B401_3c_B3B1_1 // f16_mulAdd_ru.tv line 5199997 CCFF_9001_B401_B3B1_01 -1.00011111111 x 2^4 * -1.00000000001 x 2^-11 + -1.00000000001 x 2^-2 = -1.01110110001 x 2^-3
+C7FE_4400_C000_3c_D03F_0 // f16_mulAdd_ru.tv line 5249997 C7FE_4400_C000_D03F_00 -1.01111111110 x 2^2 * 1.00000000000 x 2^2 + -1.00000000000 x 2^1 = -1.00000111111 x 2^5
+E800_471F_7C3E_3c_7E3E_0 // f16_mulAdd_ru.tv line 5299997 E800_471F_7C3E_7E3E_10 -1.00000000000 x 2^11 * 1.01100011111 x 2^2 + NaN = NaN
+3421_AAFE_0400_3c_A32F_1 // f16_mulAdd_ru.tv line 5349997 3421_AAFE_0400_A32F_01 1.00000100001 x 2^-2 * -1.01011111110 x 2^-5 + 1.00000000000 x 2^-14 = -1.01100101111 x 2^-7
+3B7B_7FFF_C47D_3c_7FFF_0 // f16_mulAdd_ru.tv line 5399997 3B7B_7FFF_C47D_7FFF_00 1.01101111011 x 2^-1 * NaN + -1.00001111101 x 2^2 = NaN
+// Skipped denorm f16_mulAdd_ru.tv line 5449997 EBFF_3801_82DA_E800_01 -1.01111111111 x 2^11 * 1.00000000001 x 2^-1 + -Denorm = -1.00000000000 x 2^11
+EBFF_A7B6_7BFF_3c_7C00_5 // f16_mulAdd_ru.tv line 5499997 EBFF_A7B6_7BFF_7C00_05 -1.01111111111 x 2^11 * -1.01110110110 x 2^-6 + 1.01111111111 x 2^15 = INF
+3FFD_36BE_3BB1_3c_3F37_1 // f16_mulAdd_ru.tv line 5549997 3FFD_36BE_3BB1_3F37_01 1.01111111101 x 2^0 * 1.01010111110 x 2^-2 + 1.01110110001 x 2^-1 = 1.01100110111 x 2^0
+4EDF_076E_84FF_3c_1A3A_1 // f16_mulAdd_ru.tv line 5599997 4EDF_076E_84FF_1A3A_01 1.01011011111 x 2^4 * 1.01101101110 x 2^-14 + -1.00011111111 x 2^-14 = 1.01000111010 x 2^-9
+C340_0401_C401_3c_C401_1 // f16_mulAdd_ru.tv line 5649997 C340_0401_C401_C401_01 -1.01101000000 x 2^1 * 1.00000000001 x 2^-14 + -1.00000000001 x 2^2 = -1.00000000001 x 2^2
+F801_C000_FC00_3c_FC00_0 // f16_mulAdd_ru.tv line 5699997 F801_C000_FC00_FC00_00 -1.00000000001 x 2^15 * -1.00000000000 x 2^1 + -INF = -INF
+FBFF_082F_77E7_3c_77E7_1 // f16_mulAdd_ru.tv line 5749997 FBFF_082F_77E7_77E7_01 -1.01111111111 x 2^15 * 1.00000101111 x 2^-13 + 1.01111100111 x 2^14 = 1.01111100111 x 2^14
+3BF8_F03E_3C00_3c_F039_1 // f16_mulAdd_ru.tv line 5799997 3BF8_F03E_3C00_F039_01 1.01111111000 x 2^-1 * -1.00000111110 x 2^13 + 1.00000000000 x 2^0 = -1.00000111001 x 2^13
+2FE3_FBFF_2C92_3c_EFE1_1 // f16_mulAdd_ru.tv line 5849997 2FE3_FBFF_2C92_EFE1_01 1.01111100011 x 2^-4 * -1.01111111111 x 2^15 + 1.00010010010 x 2^-4 = -1.01111100001 x 2^12
+FC00_B401_FC6F_3c_FE6F_0 // f16_mulAdd_ru.tv line 5899997 FC00_B401_FC6F_FE6F_10 -INF * -1.00000000001 x 2^-2 + NaN = NaN
+FC01_7FE1_93FF_3c_FE01_0 // f16_mulAdd_ru.tv line 5949997 FC01_7FE1_93FF_FE01_10 NaN * NaN + -1.01111111111 x 2^-11 = NaN
+AEF8_E814_8BFF_3c_5B1B_1 // f16_mulAdd_ru.tv line 5999997 AEF8_E814_8BFF_5B1B_01 -1.01011111000 x 2^-4 * -1.00000010100 x 2^11 + -1.01111111111 x 2^-13 = 1.01100011011 x 2^7
+// Skipped denorm f16_mulAdd_ru.tv line 6049997 BBEF_3726_83DE_B717_01 -1.01111101111 x 2^-1 * 1.01100100110 x 2^-2 + -Denorm = -1.01100010111 x 2^-2
+// Skipped denorm f16_mulAdd_ru.tv line 6099997 37EF_83FF_0001_81FA_03 1.01111101111 x 2^-2 * -Denorm + Denorm = -Denorm
+
+////////// Testcases from f16_mulAdd_rne.tv of type mulAdd rounding mode 1
+EFBE_BBFE_13FE_1c_6FBC_1 // f16_mulAdd_rne.tv line 49999 EFBE_BBFE_13FE_6FBC_01 -1.01110111110 x 2^12 * -1.01111111110 x 2^-1 + 1.01111111110 x 2^-11 = 1.01110111100 x 2^12
+// Skipped denorm f16_mulAdd_rne.tv line 99999 0001_7BFF_3FFF_4001_01 Denorm * 1.01111111111 x 2^15 + 1.01111111111 x 2^0 = 1.00000000001 x 2^1
+// Skipped denorm f16_mulAdd_rne.tv line 149999 03FF_FCFC_EBE1_FEFC_10 Denorm * NaN + -1.01111100001 x 2^11 = NaN
+// Skipped denorm f16_mulAdd_rne.tv line 199999 BD0F_2FFC_83FF_B10D_01 -1.00100001111 x 2^0 * 1.01111111100 x 2^-4 + -Denorm = -1.00100001101 x 2^-3
+8BF2_87FE_48F7_1c_48F7_1 // f16_mulAdd_rne.tv line 249999 8BF2_87FE_48F7_48F7_01 -1.01111110010 x 2^-13 * -1.01111111110 x 2^-14 + 1.00011110111 x 2^3 = 1.00011110111 x 2^3
+0400_43FF_449B_1c_449B_1 // f16_mulAdd_rne.tv line 299999 0400_43FF_449B_449B_01 1.00000000000 x 2^-14 * 1.01111111111 x 2^1 + 1.00010011011 x 2^2 = 1.00010011011 x 2^2
+0401_F37D_F800_1c_F800_1 // f16_mulAdd_rne.tv line 349999 0401_F37D_F800_F800_01 1.00000000001 x 2^-14 * -1.01101111101 x 2^13 + -1.00000000000 x 2^15 = -1.00000000000 x 2^15
+507D_B0B6_8800_1c_C549_1 // f16_mulAdd_rne.tv line 399999 507D_B0B6_8800_C549_01 1.00001111101 x 2^5 * -1.00010110110 x 2^-3 + -1.00000000000 x 2^-13 = -1.00101001001 x 2^2
+227D_9810_C1C3_1c_C1C3_1 // f16_mulAdd_rne.tv line 449999 227D_9810_C1C3_C1C3_01 1.01001111101 x 2^-7 * -1.00000010000 x 2^-9 + -1.00111000011 x 2^1 = -1.00111000011 x 2^1
+F4EF_37FE_43FE_1c_F0ED_1 // f16_mulAdd_rne.tv line 499999 F4EF_37FE_43FE_F0ED_01 -1.00011101111 x 2^14 * 1.01111111110 x 2^-2 + 1.01111111110 x 2^1 = -1.00011101101 x 2^13
+07FE_EBFF_7BFF_1c_7BFF_1 // f16_mulAdd_rne.tv line 549999 07FE_EBFF_7BFF_7BFF_01 1.01111111110 x 2^-14 * -1.01111111111 x 2^11 + 1.01111111111 x 2^15 = 1.01111111111 x 2^15
+1000_0902_A05E_1c_A05E_1 // f16_mulAdd_rne.tv line 599999 1000_0902_A05E_A05E_01 1.00000000000 x 2^-11 * 1.00100000010 x 2^-13 + -1.00001011110 x 2^-7 = -1.00001011110 x 2^-7
+47C0_4F6E_BBFF_1c_5B2B_1 // f16_mulAdd_rne.tv line 649999 47C0_4F6E_BBFF_5B2B_01 1.01111000000 x 2^2 * 1.01101101110 x 2^4 + -1.01111111111 x 2^-1 = 1.01100101011 x 2^7
+// Skipped denorm f16_mulAdd_rne.tv line 699999 CC16_03FE_DADE_DADE_01 -1.00000010110 x 2^4 * Denorm + -1.01011011110 x 2^7 = -1.01011011110 x 2^7
+13FF_BFFF_FACB_1c_FACB_1 // f16_mulAdd_rne.tv line 749999 13FF_BFFF_FACB_FACB_01 1.01111111111 x 2^-11 * -1.01111111111 x 2^0 + -1.01011001011 x 2^15 = -1.01011001011 x 2^15
+13FE_5589_1000_1c_2D90_1 // f16_mulAdd_rne.tv line 799999 13FE_5589_1000_2D90_01 1.01111111110 x 2^-11 * 1.00110001001 x 2^6 + 1.00000000000 x 2^-11 = 1.00110010000 x 2^-4
+// Skipped denorm f16_mulAdd_rne.tv line 849999 B3DF_2E0C_02F8_A5F0_01 -1.01111011111 x 2^-3 * 1.01000001100 x 2^-4 + Denorm = -1.00111110000 x 2^-6
+0BEF_D8EB_BC0A_1c_BC31_1 // f16_mulAdd_rne.tv line 899999 0BEF_D8EB_BC0A_BC31_01 1.01111101111 x 2^-13 * -1.00011101011 x 2^7 + -1.00000001010 x 2^0 = -1.00000110001 x 2^0
+7C06_93FE_7FFE_1c_7E06_0 // f16_mulAdd_rne.tv line 949999 7C06_93FE_7FFE_7E06_10 NaN * -1.01111111110 x 2^-11 + NaN = NaN
+37FF_47FF_93FF_1c_43FE_1 // f16_mulAdd_rne.tv line 999999 37FF_47FF_93FF_43FE_01 1.01111111111 x 2^-2 * 1.01111111111 x 2^2 + -1.01111111111 x 2^-11 = 1.01111111110 x 2^1
+// Skipped denorm f16_mulAdd_rne.tv line 1049999 37FE_8039_33EA_33EA_01 1.01111111110 x 2^-2 * -Denorm + 1.01111101010 x 2^-3 = 1.01111101010 x 2^-3
+CC18_C080_EBFF_1c_EBED_1 // f16_mulAdd_rne.tv line 1099999 CC18_C080_EBFF_EBED_01 -1.00000011000 x 2^4 * -1.00010000000 x 2^1 + -1.01111111111 x 2^11 = -1.01111101101 x 2^11
+// Skipped denorm f16_mulAdd_rne.tv line 1149999 413F_8000_2C02_2C02_00 1.00100111111 x 2^1 * -Denorm + 1.00000000010 x 2^-4 = 1.00000000010 x 2^-4
+3801_3BFE_4C01_1c_4C21_1 // f16_mulAdd_rne.tv line 1199999 3801_3BFE_4C01_4C21_01 1.00000000001 x 2^-1 * 1.01111111110 x 2^-1 + 1.00000000001 x 2^4 = 1.00000100001 x 2^4
+3801_4477_4000_1c_443C_1 // f16_mulAdd_rne.tv line 1249999 3801_4477_4000_443C_01 1.00000000001 x 2^-1 * 1.00001110111 x 2^2 + 1.00000000000 x 2^1 = 1.00000111100 x 2^2
+E9DE_F5FC_3259_1c_7C00_5 // f16_mulAdd_rne.tv line 1299999 E9DE_F5FC_3259_7C00_05 -1.00111011110 x 2^11 * -1.00111111100 x 2^14 + 1.01001011001 x 2^-3 = INF
+4D0F_4D7F_BD83_1c_5EEE_1 // f16_mulAdd_rne.tv line 1349999 4D0F_4D7F_BD83_5EEE_01 1.00100001111 x 2^4 * 1.00101111111 x 2^4 + -1.00110000011 x 2^0 = 1.01011101110 x 2^8
+E9BE_07FE_B7FE_1c_BADD_1 // f16_mulAdd_rne.tv line 1399999 E9BE_07FE_B7FE_BADD_01 -1.00110111110 x 2^11 * 1.01111111110 x 2^-14 + -1.01111111110 x 2^-2 = -1.01011011101 x 2^-1
+3C00_C3FF_C3FF_1c_C7FF_0 // f16_mulAdd_rne.tv line 1449999 3C00_C3FF_C3FF_C7FF_00 1.00000000000 x 2^0 * -1.01111111111 x 2^1 + -1.01111111111 x 2^1 = -1.01111111111 x 2^2
+3C01_FC06_F440_1c_FE06_0 // f16_mulAdd_rne.tv line 1499999 3C01_FC06_F440_FE06_10 1.00000000001 x 2^0 * NaN + -1.00001000000 x 2^14 = NaN
+// Skipped denorm f16_mulAdd_rne.tv line 1549999 03F9_CDB7_07FF_952D_01 Denorm * -1.00110110111 x 2^4 + 1.01111111111 x 2^-14 = -1.00100101101 x 2^-10
+AE01_FC00_B9FF_1c_7C00_0 // f16_mulAdd_rne.tv line 1599999 AE01_FC00_B9FF_7C00_00 -1.01000000001 x 2^-4 * -INF + -1.00111111111 x 2^-1 = INF
+3FFE_B7FE_39FF_1c_B3F4_1 // f16_mulAdd_rne.tv line 1649999 3FFE_B7FE_39FF_B3F4_01 1.01111111110 x 2^0 * -1.01111111110 x 2^-2 + 1.00111111111 x 2^-1 = -1.01111110100 x 2^-3
+4000_4CEF_7C00_1c_7C00_0 // f16_mulAdd_rne.tv line 1699999 4000_4CEF_7C00_7C00_00 1.00000000000 x 2^1 * 1.00011101111 x 2^4 + INF = INF
+13FE_6BAF_CEE0_1c_CDEA_1 // f16_mulAdd_rne.tv line 1749999 13FE_6BAF_CEE0_CDEA_01 1.01111111110 x 2^-11 * 1.01110101111 x 2^11 + -1.01011100000 x 2^4 = -1.00111101010 x 2^4
+76F7_C41B_3842_1c_FC00_5 // f16_mulAdd_rne.tv line 1799999 76F7_C41B_3842_FC00_05 1.01011110111 x 2^14 * -1.00000011011 x 2^2 + 1.00001000010 x 2^-1 = -INF
+// Skipped denorm f16_mulAdd_rne.tv line 1849999 43FF_83FE_C7FE_C7FE_01 1.01111111111 x 2^1 * -Denorm + -1.01111111110 x 2^2 = -1.01111111110 x 2^2
+43FE_3FFF_FFFF_1c_FFFF_0 // f16_mulAdd_rne.tv line 1899999 43FE_3FFF_FFFF_FFFF_00 1.01111111110 x 2^1 * 1.01111111111 x 2^0 + NaN = NaN
+43FE_0AF7_32F8_1c_32FF_1 // f16_mulAdd_rne.tv line 1949999 43FE_0AF7_32F8_32FF_01 1.01111111110 x 2^1 * 1.01011110111 x 2^-13 + 1.01011111000 x 2^-3 = 1.01011111111 x 2^-3
+D3BE_3CFB_3FFF_1c_D4B2_1 // f16_mulAdd_rne.tv line 1999999 D3BE_3CFB_3FFF_D4B2_01 -1.01110111110 x 2^5 * 1.00011111011 x 2^0 + 1.01111111111 x 2^0 = -1.00010110010 x 2^6
+1C46_7800_C88F_1c_57FA_1 // f16_mulAdd_rne.tv line 2049999 1C46_7800_C88F_57FA_01 1.00001000110 x 2^-8 * 1.00000000000 x 2^15 + -1.00010001111 x 2^3 = 1.01111111010 x 2^6
+47FF_13FE_8723_1c_1FE0_1 // f16_mulAdd_rne.tv line 2099999 47FF_13FE_8723_1FE0_01 1.01111111111 x 2^2 * 1.01111111110 x 2^-11 + -1.01100100011 x 2^-14 = 1.01111100000 x 2^-8
+// Skipped denorm f16_mulAdd_rne.tv line 2149999 47FF_02EE_B400_B3FD_01 1.01111111111 x 2^2 * Denorm + -1.00000000000 x 2^-2 = -1.01111111101 x 2^-3
+CDFC_6BFE_1803_1c_FC00_5 // f16_mulAdd_rne.tv line 2199999 CDFC_6BFE_1803_FC00_05 -1.00111111100 x 2^4 * 1.01111111110 x 2^11 + 1.00000000011 x 2^-9 = -INF
+C9CD_8790_CF7E_1c_CF7E_1 // f16_mulAdd_rne.tv line 2249999 C9CD_8790_CF7E_CF7E_01 -1.00111001101 x 2^3 * -1.01110010000 x 2^-14 + -1.01101111110 x 2^4 = -1.01101111110 x 2^4
+// Skipped denorm f16_mulAdd_rne.tv line 2299999 F1F0_0000_03FE_03FE_00 -1.00111110000 x 2^13 * 0 + Denorm = Denorm
+6801_BBFE_37FF_1c_E7FF_1 // f16_mulAdd_rne.tv line 2349999 6801_BBFE_37FF_E7FF_01 1.00000000001 x 2^11 * -1.01111111110 x 2^-1 + 1.01111111111 x 2^-2 = -1.01111111111 x 2^10
+6BFF_43FD_C702_1c_73FB_1 // f16_mulAdd_rne.tv line 2399999 6BFF_43FD_C702_73FB_01 1.01111111111 x 2^11 * 1.01111111101 x 2^1 + -1.01100000010 x 2^2 = 1.01111111011 x 2^13
+// Skipped denorm f16_mulAdd_rne.tv line 2449999 82FF_9180_7BFF_7BFF_01 -Denorm * -1.00110000000 x 2^-11 + 1.01111111111 x 2^15 = 1.01111111111 x 2^15
+7B80_E800_9002_1c_FC00_5 // f16_mulAdd_rne.tv line 2499999 7B80_E800_9002_FC00_05 1.01110000000 x 2^15 * -1.00000000000 x 2^11 + -1.00000000010 x 2^-11 = -INF
+7800_87FE_39FF_1c_C27E_1 // f16_mulAdd_rne.tv line 2549999 7800_87FE_39FF_C27E_01 1.00000000000 x 2^15 * -1.01111111110 x 2^-14 + 1.00111111111 x 2^-1 = -1.01001111110 x 2^1
+7801_07CE_C400_1c_AE02_1 // f16_mulAdd_rne.tv line 2599999 7801_07CE_C400_AE02_01 1.00000000001 x 2^15 * 1.01111001110 x 2^-14 + -1.00000000000 x 2^2 = -1.01000000010 x 2^-4
+8B0F_CFFF_F3EF_1c_F3EF_1 // f16_mulAdd_rne.tv line 2649999 8B0F_CFFF_F3EF_F3EF_01 -1.01100001111 x 2^-13 * -1.01111111111 x 2^4 + -1.01111101111 x 2^13 = -1.01111101111 x 2^13
+B405_B477_4704_1c_4716_1 // f16_mulAdd_rne.tv line 2699999 B405_B477_4704_4716_01 -1.00000000101 x 2^-2 * -1.00001110111 x 2^-2 + 1.01100000100 x 2^2 = 1.01100010110 x 2^2
+AFBD_7C00_3BFE_1c_FC00_0 // f16_mulAdd_rne.tv line 2749999 AFBD_7C00_3BFE_FC00_00 -1.01110111101 x 2^-4 * INF + 1.01111111110 x 2^-1 = -INF
+7C00_37FE_47FF_1c_7C00_0 // f16_mulAdd_rne.tv line 2799999 7C00_37FE_47FF_7C00_00 INF * 1.01111111110 x 2^-2 + 1.01111111111 x 2^2 = INF
+7C00_0BB0_B818_1c_7C00_0 // f16_mulAdd_rne.tv line 2849999 7C00_0BB0_B818_7C00_00 INF * 1.01110110000 x 2^-13 + -1.00000011000 x 2^-1 = INF
+5376_BFB7_93FF_1c_D732_1 // f16_mulAdd_rne.tv line 2899999 5376_BFB7_93FF_D732_01 1.01101110110 x 2^5 * -1.01110110111 x 2^0 + -1.01111111111 x 2^-11 = -1.01100110010 x 2^6
+387B_4400_B990_1c_3E2E_0 // f16_mulAdd_rne.tv line 2949999 387B_4400_B990_3E2E_00 1.00001111011 x 2^-1 * 1.00000000000 x 2^2 + -1.00110010000 x 2^-1 = 1.01000101110 x 2^0
+// Skipped denorm f16_mulAdd_rne.tv line 2999999 7FFE_03FE_577C_7FFE_00 NaN * Denorm + 1.01101111100 x 2^6 = NaN
+7FFE_BB65_0000_1c_7FFE_0 // f16_mulAdd_rne.tv line 3049999 7FFE_BB65_0000_7FFE_00 NaN * -1.01101100101 x 2^-1 + 0 = NaN
+8B40_5022_7FAB_1c_7FAB_0 // f16_mulAdd_rne.tv line 3099999 8B40_5022_7FAB_7FAB_00 -1.01101000000 x 2^-13 * 1.00000100010 x 2^5 + NaN = NaN
+FE00_2363_B711_1c_FE00_0 // f16_mulAdd_rne.tv line 3149999 FE00_2363_B711_FE00_00 NaN * 1.01101100011 x 2^-7 + -1.01100010001 x 2^-2 = NaN
+F703_F800_6BFE_1c_7C00_5 // f16_mulAdd_rne.tv line 3199999 F703_F800_6BFE_7C00_05 -1.01100000011 x 2^14 * -1.00000000000 x 2^15 + 1.01111111110 x 2^11 = INF
+// Skipped denorm f16_mulAdd_rne.tv line 3249999 83FF_93FE_83FF_83FE_03 -Denorm * -1.01111111110 x 2^-11 + -Denorm = -Denorm
+// Skipped denorm f16_mulAdd_rne.tv line 3299999 83FE_77F8_C3BF_C5DD_01 -Denorm * 1.01111111000 x 2^14 + -1.01110111111 x 2^1 = -1.00111011101 x 2^2
+CBC3_3EA6_C3FF_1c_CF73_1 // f16_mulAdd_rne.tv line 3349999 CBC3_3EA6_C3FF_CF73_01 -1.01111000011 x 2^3 * 1.01010100110 x 2^0 + -1.01111111111 x 2^1 = -1.01101110011 x 2^4
+7B9A_C000_080A_1c_FC00_5 // f16_mulAdd_rne.tv line 3399999 7B9A_C000_080A_FC00_05 1.01110011010 x 2^15 * -1.00000000000 x 2^1 + 1.00000001010 x 2^-13 = -INF
+// Skipped denorm f16_mulAdd_rne.tv line 3449999 8401_8000_3076_3076_00 -1.00000000001 x 2^-14 * -Denorm + 1.00001110110 x 2^-3 = 1.00001110110 x 2^-3
+87FF_079F_3800_1c_3800_1 // f16_mulAdd_rne.tv line 3499999 87FF_079F_3800_3800_01 -1.01111111111 x 2^-14 * 1.01110011111 x 2^-14 + 1.00000000000 x 2^-1 = 1.00000000000 x 2^-1
+0C7B_AC6E_CFF6_1c_CFF6_1 // f16_mulAdd_rne.tv line 3549999 0C7B_AC6E_CFF6_CFF6_01 1.00001111011 x 2^-12 * -1.00001101110 x 2^-4 + -1.01111110110 x 2^4 = -1.01111110110 x 2^4
+3154_C500_CDC0_1c_CDF5_1 // f16_mulAdd_rne.tv line 3599999 3154_C500_CDC0_CDF5_01 1.00101010100 x 2^-3 * -1.00100000000 x 2^2 + -1.00111000000 x 2^4 = -1.00111110101 x 2^4
+0403_6800_87FE_1c_3002_1 // f16_mulAdd_rne.tv line 3649999 0403_6800_87FE_3002_01 1.00000000011 x 2^-14 * 1.00000000000 x 2^11 + -1.01111111110 x 2^-14 = 1.00000000010 x 2^-3
+9001_07FE_BBFF_1c_BBFF_1 // f16_mulAdd_rne.tv line 3699999 9001_07FE_BBFF_BBFF_01 -1.00000000001 x 2^-11 * 1.01111111110 x 2^-14 + -1.01111111111 x 2^-1 = -1.01111111111 x 2^-1
+9001_B8DE_4FB0_1c_4FB0_1 // f16_mulAdd_rne.tv line 3749999 9001_B8DE_4FB0_4FB0_01 -1.00000000001 x 2^-11 * -1.00011011110 x 2^-1 + 1.01110110000 x 2^4 = 1.01110110000 x 2^4
+// Skipped denorm f16_mulAdd_rne.tv line 3799999 07F9_00BE_FFFF_FFFF_00 1.01111111001 x 2^-14 * Denorm + NaN = NaN
+400C_3C01_B3E3_1c_3F1E_1 // f16_mulAdd_rne.tv line 3849999 400C_3C01_B3E3_3F1E_01 1.00000001100 x 2^1 * 1.00000000001 x 2^0 + -1.01111100011 x 2^-3 = 1.01100011110 x 2^0
+93FE_FC00_CBB0_1c_7C00_0 // f16_mulAdd_rne.tv line 3899999 93FE_FC00_CBB0_7C00_00 -1.01111111110 x 2^-11 * -INF + -1.01110110000 x 2^3 = INF
+B400_A05F_6800_1c_6800_1 // f16_mulAdd_rne.tv line 3949999 B400_A05F_6800_6800_01 -1.00000000000 x 2^-2 * -1.00001011111 x 2^-7 + 1.00000000000 x 2^11 = 1.00000000000 x 2^11
+30CA_35A5_3820_1c_388C_1 // f16_mulAdd_rne.tv line 3999999 30CA_35A5_3820_388C_01 1.00011001010 x 2^-3 * 1.00110100101 x 2^-2 + 1.00000100000 x 2^-1 = 1.00010001100 x 2^-1
+377D_B087_C26C_1c_C28E_1 // f16_mulAdd_rne.tv line 4049999 377D_B087_C26C_C28E_01 1.01101111101 x 2^-2 * -1.00010000111 x 2^-3 + -1.01001101100 x 2^1 = -1.01010001110 x 2^1
+FFF8_C400_BFFE_1c_FFF8_0 // f16_mulAdd_rne.tv line 4099999 FFF8_C400_BFFE_FFF8_00 NaN * -1.00000000000 x 2^2 + -1.01111111110 x 2^0 = NaN
+// Skipped denorm f16_mulAdd_rne.tv line 4149999 B7FE_83FE_EBFF_EBFF_01 -1.01111111110 x 2^-2 * -Denorm + -1.01111111111 x 2^11 = -1.01111111111 x 2^11
+B800_CA00_3038_1c_4622_1 // f16_mulAdd_rne.tv line 4199999 B800_CA00_3038_4622_01 -1.00000000000 x 2^-1 * -1.01000000000 x 2^3 + 1.00000111000 x 2^-3 = 1.01000100010 x 2^2
+D417_557E_37FF_1c_ED9D_1 // f16_mulAdd_rne.tv line 4249999 D417_557E_37FF_ED9D_01 -1.00000010111 x 2^6 * 1.00101111110 x 2^6 + 1.01111111111 x 2^-2 = -1.00110011101 x 2^12
+E8FE_B801_3BF8_1c_6500_1 // f16_mulAdd_rne.tv line 4299999 E8FE_B801_3BF8_6500_01 -1.00011111110 x 2^11 * -1.00000000001 x 2^-1 + 1.01111111000 x 2^-1 = 1.00100000000 x 2^10
+BBFF_7800_C6BE_1c_F7FF_1 // f16_mulAdd_rne.tv line 4349999 BBFF_7800_C6BE_F7FF_01 -1.01111111111 x 2^-1 * 1.00000000000 x 2^15 + -1.01010111110 x 2^2 = -1.01111111111 x 2^14
+BBFE_37DF_8400_1c_B7DD_1 // f16_mulAdd_rne.tv line 4399999 BBFE_37DF_8400_B7DD_01 -1.01111111110 x 2^-1 * 1.01111011111 x 2^-2 + -1.00000000000 x 2^-14 = -1.01111011101 x 2^-2
+D404_BB77_F7EE_1c_F7EA_1 // f16_mulAdd_rne.tv line 4449999 D404_BB77_F7EE_F7EA_01 -1.00000000100 x 2^6 * -1.01101110111 x 2^-1 + -1.01111101110 x 2^14 = -1.01111101010 x 2^14
+// Skipped denorm f16_mulAdd_rne.tv line 4499999 10BF_83D0_A06E_A06E_01 1.00010111111 x 2^-11 * -Denorm + -1.00001101110 x 2^-7 = -1.00001101110 x 2^-7
+B62E_4000_FBFE_1c_FBFE_1 // f16_mulAdd_rne.tv line 4549999 B62E_4000_FBFE_FBFE_01 -1.01000101110 x 2^-2 * 1.00000000000 x 2^1 + -1.01111111110 x 2^15 = -1.01111111110 x 2^15
+BFFF_0000_07FF_1c_07FF_0 // f16_mulAdd_rne.tv line 4599999 BFFF_0000_07FF_07FF_00 -1.01111111111 x 2^0 * 0 + 1.01111111111 x 2^-14 = 1.01111111111 x 2^-14
+BFFF_3A1E_4C00_1c_4B3C_1 // f16_mulAdd_rne.tv line 4649999 BFFF_3A1E_4C00_4B3C_01 -1.01111111111 x 2^0 * 1.01000011110 x 2^-1 + 1.00000000000 x 2^4 = 1.01100111100 x 2^3
+C83C_F803_47FF_1c_7C00_5 // f16_mulAdd_rne.tv line 4699999 C83C_F803_47FF_7C00_05 -1.00000111100 x 2^3 * -1.00000000011 x 2^15 + 1.01111111111 x 2^2 = INF
+6005_3401_77FD_1c_7803_1 // f16_mulAdd_rne.tv line 4749999 6005_3401_77FD_7803_01 1.00000000101 x 2^9 * 1.00000000001 x 2^-2 + 1.01111111101 x 2^14 = 1.00000000011 x 2^15
+C000_E800_B86F_1c_6C00_1 // f16_mulAdd_rne.tv line 4799999 C000_E800_B86F_6C00_01 -1.00000000000 x 2^1 * -1.00000000000 x 2^11 + -1.00001101111 x 2^-1 = 1.00000000000 x 2^12
+C001_B779_BC00_1c_AC29_1 // f16_mulAdd_rne.tv line 4849999 C001_B779_BC00_AC29_01 -1.00000000001 x 2^1 * -1.01101111001 x 2^-2 + -1.00000000000 x 2^0 = -1.00000101001 x 2^-4
+C001_C386_C882_1c_BDF0_1 // f16_mulAdd_rne.tv line 4899999 C001_C386_C882_BDF0_01 -1.00000000001 x 2^1 * -1.01110000110 x 2^1 + -1.00010000010 x 2^3 = -1.00111110000 x 2^0
+// Skipped denorm f16_mulAdd_rne.tv line 4949999 8388_3476_F629_F629_01 -Denorm * 1.00001110110 x 2^-2 + -1.01000101001 x 2^14 = -1.01000101001 x 2^14
+B293_BC01_13FE_1c_329D_1 // f16_mulAdd_rne.tv line 4999999 B293_BC01_13FE_329D_01 -1.01010010011 x 2^-3 * -1.00000000001 x 2^0 + 1.01111111110 x 2^-11 = 1.01010011101 x 2^-3
+C400_7C00_3FFF_1c_FC00_0 // f16_mulAdd_rne.tv line 5049999 C400_7C00_3FFF_FC00_00 -1.00000000000 x 2^2 * INF + 1.01111111111 x 2^0 = -INF
+C401_BA20_5B00_1c_5B19_1 // f16_mulAdd_rne.tv line 5099999 C401_BA20_5B00_5B19_01 -1.00000000001 x 2^2 * -1.01000100000 x 2^-1 + 1.01100000000 x 2^7 = 1.01100011001 x 2^7
+// Skipped denorm f16_mulAdd_rne.tv line 5149999 7881_3E00_83FF_7AC1_01 1.00010000001 x 2^15 * 1.01000000000 x 2^0 + -Denorm = 1.01011000001 x 2^15
+C4FC_9001_34EE_1c_34F8_1 // f16_mulAdd_rne.tv line 5199999 C4FC_9001_34EE_34F8_01 -1.00011111100 x 2^2 * -1.00000000001 x 2^-11 + 1.00011101110 x 2^-2 = 1.00011111000 x 2^-2
+C7FE_4400_3809_1c_CFDE_1 // f16_mulAdd_rne.tv line 5249999 C7FE_4400_3809_CFDE_01 -1.01111111110 x 2^2 * 1.00000000000 x 2^2 + 1.00000001001 x 2^-1 = -1.01111011110 x 2^4
+E800_3C71_F800_1c_F847_1 // f16_mulAdd_rne.tv line 5299999 E800_3C71_F800_F847_01 -1.00000000000 x 2^11 * 1.00001110001 x 2^0 + -1.00000000000 x 2^15 = -1.00001000111 x 2^15
+3408_F5F7_5400_1c_EDF3_1 // f16_mulAdd_rne.tv line 5349999 3408_F5F7_5400_EDF3_01 1.00000001000 x 2^-2 * -1.00111110111 x 2^14 + 1.00000000000 x 2^6 = -1.00111110011 x 2^12
+8D0F_B640_EA1F_1c_EA1F_1 // f16_mulAdd_rne.tv line 5399999 8D0F_B640_EA1F_EA1F_01 -1.00100001111 x 2^-12 * -1.01001000000 x 2^-2 + -1.01000011111 x 2^11 = -1.01000011111 x 2^11
+CDFE_3801_43FE_1c_C800_1 // f16_mulAdd_rne.tv line 5449999 CDFE_3801_43FE_C800_01 -1.00111111110 x 2^4 * 1.00000000001 x 2^-1 + 1.01111111110 x 2^1 = -1.00000000000 x 2^3
+EBFF_F800_7BFF_1c_7C00_5 // f16_mulAdd_rne.tv line 5499999 EBFF_F800_7BFF_7C00_05 -1.01111111111 x 2^11 * -1.00000000000 x 2^15 + 1.01111111111 x 2^15 = INF
+EBFE_2412_F616_1c_F61A_1 // f16_mulAdd_rne.tv line 5549999 EBFE_2412_F616_F61A_01 -1.01111111110 x 2^11 * 1.00000010010 x 2^-6 + -1.01000010110 x 2^14 = -1.01000011010 x 2^14
+FA1B_7817_BBFF_1c_FC00_5 // f16_mulAdd_rne.tv line 5599999 FA1B_7817_BBFF_FC00_05 -1.01000011011 x 2^15 * 1.00000010111 x 2^15 + -1.01111111111 x 2^-1 = -INF
+// Skipped denorm f16_mulAdd_rne.tv line 5649999 83FA_0401_E3E3_E3E3_01 -Denorm * 1.00000000001 x 2^-14 + -1.01111100011 x 2^9 = -1.01111100011 x 2^9
+F801_C000_13EC_1c_7C00_5 // f16_mulAdd_rne.tv line 5699999 F801_C000_13EC_7C00_05 -1.00000000001 x 2^15 * -1.00000000000 x 2^1 + 1.01111101100 x 2^-11 = INF
+FBFF_C7F7_1000_1c_7C00_5 // f16_mulAdd_rne.tv line 5749999 FBFF_C7F7_1000_7C00_05 -1.01111111111 x 2^15 * -1.01111110111 x 2^2 + 1.00000000000 x 2^-11 = INF
+// Skipped denorm f16_mulAdd_rne.tv line 5799999 37F5_8153_7BEA_7BEA_01 1.01111110101 x 2^-2 * -Denorm + 1.01111101010 x 2^15 = 1.01111101010 x 2^15
+E7F6_F437_4DFC_1c_7C00_5 // f16_mulAdd_rne.tv line 5849999 E7F6_F437_4DFC_7C00_05 -1.01111110110 x 2^10 * -1.00000110111 x 2^14 + 1.00111111100 x 2^4 = INF
+0440_B401_7FFE_1c_7FFE_0 // f16_mulAdd_rne.tv line 5899999 0440_B401_7FFE_7FFE_00 1.00001000000 x 2^-14 * -1.00000000001 x 2^-2 + NaN = NaN
+FC01_6800_93FF_1c_FE01_0 // f16_mulAdd_rne.tv line 5949999 FC01_6800_93FF_FE01_10 NaN * 1.00000000000 x 2^11 + -1.01111111111 x 2^-11 = NaN
+// Skipped denorm f16_mulAdd_rne.tv line 5999999 FFFF_8060_C6BE_FFFF_00 NaN * -Denorm + -1.01010111110 x 2^2 = NaN
+7801_3B78_EBFF_1c_767A_1 // f16_mulAdd_rne.tv line 6049999 7801_3B78_EBFF_767A_01 1.00000000001 x 2^15 * 1.01101111000 x 2^-1 + -1.01111111111 x 2^11 = 1.01001111010 x 2^14
+// Skipped denorm f16_mulAdd_rne.tv line 6099999 4F3F_83FF_6AFE_6AFE_01 1.01100111111 x 2^4 * -Denorm + 1.01011111110 x 2^11 = 1.01011111110 x 2^11
diff --git a/pipelined/src/fma/baby_torture_rz.tv b/pipelined/src/fma/baby_torture_rz.tv
new file mode 100644
index 00000000..beecf696
--- /dev/null
+++ b/pipelined/src/fma/baby_torture_rz.tv
@@ -0,0 +1,313 @@
+// Torture tests generated Tue Apr 19 15:10:52 2022 by ./torturegen.pl
+
+////////// Testcases from f16_add_rz.tv of type add rounding mode 0
+0000_0000_FA02_04_FA02_0 // f16_add_rz.tv line 500 0000_FA02_FA02_00 0 + -1.01000000010 x 2^15 = -1.01000000010 x 2^15
+93FF_0000_EBFF_04_EBFF_1 // f16_add_rz.tv line 1000 93FF_EBFF_EBFF_01 -1.01111111111 x 2^-11 + -1.01111111111 x 2^11 = -1.01111111111 x 2^11
+// Skipped denorm f16_add_rz.tv line 1500 03FF_C401_C400_01 Denorm + -1.00000000001 x 2^2 = -1.00000000000 x 2^2
+// Skipped denorm f16_add_rz.tv line 2000 03FE_0001_03FF_00 Denorm + Denorm = Denorm
+54CE_0000_BC00_04_54BE_0 // f16_add_rz.tv line 2500 54CE_BC00_54BE_00 1.00011001110 x 2^6 + -1.00000000000 x 2^0 = 1.00010111110 x 2^6
+0401_0000_B7FE_04_B7FD_1 // f16_add_rz.tv line 3000 0401_B7FE_B7FD_01 1.00000000001 x 2^-14 + -1.01111111110 x 2^-2 = -1.01111111101 x 2^-2
+07FF_0000_C3FF_04_C3FE_1 // f16_add_rz.tv line 3500 07FF_C3FF_C3FE_01 1.01111111111 x 2^-14 + -1.01111111111 x 2^1 = -1.01111111110 x 2^1
+9C3B_0000_87FF_04_9C5A_1 // f16_add_rz.tv line 4000 9C3B_87FF_9C5A_01 -1.00000111011 x 2^-8 + -1.01111111111 x 2^-14 = -1.00001011010 x 2^-8
+// Skipped denorm f16_add_rz.tv line 4500 1000_8001_0FFF_01 1.00000000000 x 2^-11 + -Denorm = 1.01111111111 x 2^-12
+1001_0000_2FBB_04_2FC3_1 // f16_add_rz.tv line 5000 1001_2FBB_2FC3_01 1.00000000001 x 2^-11 + 1.01110111011 x 2^-4 = 1.01111000011 x 2^-4
+37EE_0000_7800_04_7800_1 // f16_add_rz.tv line 5500 37EE_7800_7800_01 1.01111101110 x 2^-2 + 1.00000000000 x 2^15 = 1.00000000000 x 2^15
+13FE_0000_47FE_04_47FE_1 // f16_add_rz.tv line 6000 13FE_47FE_47FE_01 1.01111111110 x 2^-11 + 1.01111111110 x 2^2 = 1.01111111110 x 2^2
+3400_0000_CA47_04_CA27_0 // f16_add_rz.tv line 6500 3400_CA47_CA27_00 1.00000000000 x 2^-2 + -1.01001000111 x 2^3 = -1.01000100111 x 2^3
+30EE_0000_3FFF_04_404E_1 // f16_add_rz.tv line 7000 30EE_3FFF_404E_01 1.00011101110 x 2^-3 + 1.01111111111 x 2^0 = 1.00001001110 x 2^1
+37FF_0000_3801_04_3C00_1 // f16_add_rz.tv line 7500 37FF_3801_3C00_01 1.01111111111 x 2^-2 + 1.00000000001 x 2^-1 = 1.00000000000 x 2^0
+37FE_0000_B783_04_27B0_0 // f16_add_rz.tv line 8000 37FE_B783_27B0_00 1.01111111110 x 2^-2 + -1.01110000011 x 2^-2 = 1.01110110000 x 2^-6
+0EBE_0000_1000_04_135F_0 // f16_add_rz.tv line 8500 0EBE_1000_135F_00 1.01010111110 x 2^-12 + 1.00000000000 x 2^-11 = 1.01101011111 x 2^-11
+// Skipped denorm f16_add_rz.tv line 9000 3801_03FE_3801_01 1.00000000001 x 2^-1 + Denorm = 1.00000000001 x 2^-1
+3801_0000_480F_04_484F_1 // f16_add_rz.tv line 9500 3801_480F_484F_01 1.00000000001 x 2^-1 + 1.00000001111 x 2^3 = 1.00001001111 x 2^3
+// Skipped denorm f16_add_rz.tv line 10000 003E_FBFF_FBFE_01 Denorm + -1.01111111111 x 2^15 = -1.01111111110 x 2^15
+3BFE_0000_E801_04_E800_1 // f16_add_rz.tv line 10500 3BFE_E801_E800_01 1.01111111110 x 2^-1 + -1.00000000001 x 2^11 = -1.00000000000 x 2^11
+3C00_0000_88D3_04_3BFF_1 // f16_add_rz.tv line 11000 3C00_88D3_3BFF_01 1.00000000000 x 2^0 + -1.00011010011 x 2^-13 = 1.01111111111 x 2^-1
+257F_0000_C000_04_BFEA_1 // f16_add_rz.tv line 11500 257F_C000_BFEA_01 1.00101111111 x 2^-6 + -1.00000000000 x 2^1 = -1.01111101010 x 2^0
+3FFF_0000_BBFE_04_3C00_0 // f16_add_rz.tv line 12000 3FFF_BBFE_3C00_00 1.01111111111 x 2^0 + -1.01111111110 x 2^-1 = 1.00000000000 x 2^0
+3FFE_0000_4AFD_04_4BFC_1 // f16_add_rz.tv line 12500 3FFE_4AFD_4BFC_01 1.01111111110 x 2^0 + 1.01011111101 x 2^3 = 1.01111111100 x 2^3
+B7FF_0000_93FF_04_B801_1 // f16_add_rz.tv line 13000 B7FF_93FF_B801_01 -1.01111111111 x 2^-2 + -1.01111111111 x 2^-11 = -1.00000000001 x 2^-1
+4001_0000_8401_04_4000_1 // f16_add_rz.tv line 13500 4001_8401_4000_01 1.00000000001 x 2^1 + -1.00000000001 x 2^-14 = 1.00000000000 x 2^1
+43FF_0000_3808_04_4480_1 // f16_add_rz.tv line 14000 43FF_3808_4480_01 1.01111111111 x 2^1 + 1.00000001000 x 2^-1 = 1.00010000000 x 2^2
+AC0A_0000_7C00_04_7C00_0 // f16_add_rz.tv line 14500 AC0A_7C00_7C00_00 -1.00000001010 x 2^-4 + INF = INF
+4400_0000_6BFE_04_6C00_0 // f16_add_rz.tv line 15000 4400_6BFE_6C00_00 1.00000000000 x 2^2 + 1.01111111110 x 2^11 = 1.00000000000 x 2^12
+4401_0000_D3F2_04_D371_1 // f16_add_rz.tv line 15500 4401_D3F2_D371_01 1.00000000001 x 2^2 + -1.01111110010 x 2^5 = -1.01101110001 x 2^5
+5BC2_0000_43FF_04_5BE1_1 // f16_add_rz.tv line 16000 5BC2_43FF_5BE1_01 1.01111000010 x 2^7 + 1.01111111111 x 2^1 = 1.01111100001 x 2^7
+47FE_0000_3C01_04_487F_1 // f16_add_rz.tv line 16500 47FE_3C01_487F_01 1.01111111110 x 2^2 + 1.00000000001 x 2^0 = 1.00001111111 x 2^3
+6800_0000_13F1_04_6800_1 // f16_add_rz.tv line 17000 6800_13F1_6800_01 1.00000000000 x 2^11 + 1.01111110001 x 2^-11 = 1.00000000000 x 2^11
+78FB_0000_3400_04_78FB_1 // f16_add_rz.tv line 17500 78FB_3400_78FB_01 1.00011111011 x 2^15 + 1.00000000000 x 2^-2 = 1.00011111011 x 2^15
+6BFF_0000_07FE_04_6BFF_1 // f16_add_rz.tv line 18000 6BFF_07FE_6BFF_01 1.01111111111 x 2^11 + 1.01111111110 x 2^-14 = 1.01111111111 x 2^11
+6BFE_0000_13FE_04_6BFE_1 // f16_add_rz.tv line 18500 6BFE_13FE_6BFE_01 1.01111111110 x 2^11 + 1.01111111110 x 2^-11 = 1.01111111110 x 2^11
+382F_0000_FFFF_04_FFFF_0 // f16_add_rz.tv line 19000 382F_FFFF_FFFF_00 1.00000101111 x 2^-1 + NaN = NaN
+7800_0000_F801_04_D000_0 // f16_add_rz.tv line 19500 7800_F801_D000_00 1.00000000000 x 2^15 + -1.00000000001 x 2^15 = -1.00000000000 x 2^5
+7801_0000_4877_04_7801_1 // f16_add_rz.tv line 20000 7801_4877_7801_01 1.00000000001 x 2^15 + 1.00001110111 x 2^3 = 1.00000000001 x 2^15
+// Skipped denorm f16_add_rz.tv line 20500 0090_C400_C3FF_01 Denorm + -1.00000000000 x 2^2 = -1.01111111111 x 2^1
+7BFE_0000_BFFE_04_7BFD_1 // f16_add_rz.tv line 21000 7BFE_BFFE_7BFD_01 1.01111111110 x 2^15 + -1.01111111110 x 2^0 = 1.01111111101 x 2^15
+7C00_0000_4F08_04_7C00_0 // f16_add_rz.tv line 21500 7C00_4F08_7C00_00 INF + 1.01100001000 x 2^4 = INF
+BFFA_0000_B7FF_04_C0FC_1 // f16_add_rz.tv line 22000 BFFA_B7FF_C0FC_01 -1.01111111010 x 2^0 + -1.01111111111 x 2^-2 = -1.00011111100 x 2^1
+7FFF_0000_9001_04_7FFF_0 // f16_add_rz.tv line 22500 7FFF_9001_7FFF_00 NaN + -1.00000000001 x 2^-11 = NaN
+7FFE_0000_B82F_04_7FFE_0 // f16_add_rz.tv line 23000 7FFE_B82F_7FFE_00 NaN + -1.00000101111 x 2^-1 = NaN
+// Skipped denorm f16_add_rz.tv line 23500 2F68_8000_2F68_00 1.01101101000 x 2^-4 + -Denorm = 1.01101101000 x 2^-4
+// Skipped denorm f16_add_rz.tv line 24000 8001_7BFE_7BFD_01 -Denorm + 1.01111111110 x 2^15 = 1.01111111101 x 2^15
+// Skipped denorm f16_add_rz.tv line 24500 83FF_EB8E_EB8E_01 -Denorm + -1.01110001110 x 2^11 = -1.01110001110 x 2^11
+75FF_0000_47FF_04_75FF_1 // f16_add_rz.tv line 25000 75FF_47FF_75FF_01 1.00111111111 x 2^14 + 1.01111111111 x 2^2 = 1.00111111111 x 2^14
+8400_0000_4001_04_4000_1 // f16_add_rz.tv line 25500 8400_4001_4000_01 -1.00000000000 x 2^-14 + 1.00000000001 x 2^1 = 1.00000000000 x 2^1
+8401_0000_C3E7_04_C3E7_1 // f16_add_rz.tv line 26000 8401_C3E7_C3E7_01 -1.00000000001 x 2^-14 + -1.01111100111 x 2^1 = -1.01111100111 x 2^1
+CC00_0000_3800_04_CBC0_0 // f16_add_rz.tv line 26500 CC00_3800_CBC0_00 -1.00000000000 x 2^4 + 1.00000000000 x 2^-1 = -1.01111000000 x 2^3
+87FE_0000_13FE_04_12FE_1 // f16_add_rz.tv line 27000 87FE_13FE_12FE_01 -1.01111111110 x 2^-14 + 1.01111111110 x 2^-11 = 1.01011111110 x 2^-11
+9000_0000_7FF2_04_7FF2_0 // f16_add_rz.tv line 27500 9000_7FF2_7FF2_00 -1.00000000000 x 2^-11 + NaN = NaN
+// Skipped denorm f16_add_rz.tv line 28000 C082_03FF_C081_01 -1.00010000010 x 2^1 + Denorm = -1.00010000001 x 2^1
+9001_0000_FC01_04_FE01_0 // f16_add_rz.tv line 28500 9001_FC01_FE01_10 -1.00000000001 x 2^-11 + NaN = NaN
+93FF_0000_2DFF_04_2DEF_1 // f16_add_rz.tv line 29000 93FF_2DFF_2DEF_01 -1.01111111111 x 2^-11 + 1.00111111111 x 2^-4 = 1.00111101111 x 2^-4
+BE01_0000_E800_04_E800_1 // f16_add_rz.tv line 29500 BE01_E800_E800_01 -1.01000000001 x 2^0 + -1.00000000000 x 2^11 = -1.00000000000 x 2^11
+B400_0000_C3FE_04_C43F_0 // f16_add_rz.tv line 30000 B400_C3FE_C43F_00 -1.00000000000 x 2^-2 + -1.01111111110 x 2^1 = -1.00000111111 x 2^2
+B401_0000_2702_04_B321_1 // f16_add_rz.tv line 30500 B401_2702_B321_01 -1.00000000001 x 2^-2 + 1.01100000010 x 2^-6 = -1.01100100001 x 2^-3
+E09F_0000_BBFF_04_E0A0_1 // f16_add_rz.tv line 31000 E09F_BBFF_E0A0_01 -1.00010011111 x 2^9 + -1.01111111111 x 2^-1 = -1.00010100000 x 2^9
+B7FE_0000_B401_04_B9FF_1 // f16_add_rz.tv line 31500 B7FE_B401_B9FF_01 -1.01111111110 x 2^-2 + -1.00000000001 x 2^-2 = -1.00111111111 x 2^-1
+// Skipped denorm f16_add_rz.tv line 32000 B800_80BF_B800_01 -1.00000000000 x 2^-1 + -Denorm = -1.00000000000 x 2^-1
+6BBC_0000_8400_04_6BBB_1 // f16_add_rz.tv line 32500 6BBC_8400_6BBB_01 1.01110111100 x 2^11 + -1.00000000000 x 2^-14 = 1.01110111011 x 2^11
+BBFF_0000_7FFE_04_7FFE_0 // f16_add_rz.tv line 33000 BBFF_7FFE_7FFE_00 -1.01111111111 x 2^-1 + NaN = NaN
+BBFE_0000_09DF_04_BBFD_1 // f16_add_rz.tv line 33500 BBFE_09DF_BBFD_01 -1.01111111110 x 2^-1 + 1.00111011111 x 2^-13 = -1.01111111101 x 2^-1
+124E_0000_6BFF_04_6BFF_1 // f16_add_rz.tv line 34000 124E_6BFF_6BFF_01 1.01001001110 x 2^-11 + 1.01111111111 x 2^11 = 1.01111111111 x 2^11
+BC01_0000_4401_04_4201_1 // f16_add_rz.tv line 34500 BC01_4401_4201_01 -1.00000000001 x 2^0 + 1.00000000001 x 2^2 = 1.01000000001 x 2^1
+BFFF_0000_10BF_04_BFFE_1 // f16_add_rz.tv line 35000 BFFF_10BF_BFFE_01 -1.01111111111 x 2^0 + 1.00010111111 x 2^-11 = -1.01111111110 x 2^0
+48EF_0000_3C00_04_496F_0 // f16_add_rz.tv line 35500 48EF_3C00_496F_00 1.00011101111 x 2^3 + 1.00000000000 x 2^0 = 1.00101101111 x 2^3
+C000_0000_37FE_04_BE00_1 // f16_add_rz.tv line 36000 C000_37FE_BE00_01 -1.00000000000 x 2^1 + 1.01111111110 x 2^-2 = -1.01000000000 x 2^0
+// Skipped denorm f16_add_rz.tv line 36500 C001_021F_C000_01 -1.00000000001 x 2^1 + Denorm = -1.00000000000 x 2^1
+1180_0000_07FF_04_127F_1 // f16_add_rz.tv line 37000 1180_07FF_127F_01 1.00110000000 x 2^-11 + 1.01111111111 x 2^-14 = 1.01001111111 x 2^-11
+// Skipped denorm f16_add_rz.tv line 37500 C3FE_0001_C3FD_01 -1.01111111110 x 2^1 + Denorm = -1.01111111101 x 2^1
+// Skipped denorm f16_add_rz.tv line 38000 C3FE_00FF_C3FD_01 -1.01111111110 x 2^1 + Denorm = -1.01111111101 x 2^1
+1A7C_0000_F800_04_F7FF_1 // f16_add_rz.tv line 38500 1A7C_F800_F7FF_01 1.01001111100 x 2^-9 + -1.00000000000 x 2^15 = -1.01111111111 x 2^14
+C401_0000_C7FE_04_C9FF_1 // f16_add_rz.tv line 39000 C401_C7FE_C9FF_01 -1.00000000001 x 2^2 + -1.01111111110 x 2^2 = -1.00111111111 x 2^3
+C7FF_0000_C73F_04_CB9F_0 // f16_add_rz.tv line 39500 C7FF_C73F_CB9F_00 -1.01111111111 x 2^2 + -1.01100111111 x 2^2 = -1.01110011111 x 2^3
+3F10_0000_BFFF_04_B378_0 // f16_add_rz.tv line 40000 3F10_BFFF_B378_00 1.01100010000 x 2^0 + -1.01111111111 x 2^0 = -1.01101111000 x 2^-3
+E800_0000_B801_04_E800_1 // f16_add_rz.tv line 40500 E800_B801_E800_01 -1.00000000000 x 2^11 + -1.00000000001 x 2^-1 = -1.00000000000 x 2^11
+E801_0000_B387_04_E801_1 // f16_add_rz.tv line 41000 E801_B387_E801_01 -1.00000000001 x 2^11 + -1.01110000111 x 2^-3 = -1.00000000001 x 2^11
+CBE1_0000_9000_04_CBE1_1 // f16_add_rz.tv line 41500 CBE1_9000_CBE1_01 -1.01111100001 x 2^3 + -1.00000000000 x 2^-11 = -1.01111100001 x 2^3
+// Skipped denorm f16_add_rz.tv line 42000 EBFE_83FE_EBFE_01 -1.01111111110 x 2^11 + -Denorm = -1.01111111110 x 2^11
+F800_0000_3F00_04_F7FF_1 // f16_add_rz.tv line 42500 F800_3F00_F7FF_01 -1.00000000000 x 2^15 + 1.01100000000 x 2^0 = -1.01111111111 x 2^14
+CFBF_0000_7BFF_04_7BFE_1 // f16_add_rz.tv line 43000 CFBF_7BFF_7BFE_01 -1.01110111111 x 2^4 + 1.01111111111 x 2^15 = 1.01111111110 x 2^15
+FBFF_0000_6801_04_FBBE_1 // f16_add_rz.tv line 43500 FBFF_6801_FBBE_01 -1.01111111111 x 2^15 + 1.00000000001 x 2^11 = -1.01110111110 x 2^15
+FBFE_0000_11FF_04_FBFD_1 // f16_add_rz.tv line 44000 FBFE_11FF_FBFD_01 -1.01111111110 x 2^15 + 1.00111111111 x 2^-11 = -1.01111111101 x 2^15
+3CD8_0000_4000_04_426C_0 // f16_add_rz.tv line 44500 3CD8_4000_426C_00 1.00011011000 x 2^0 + 1.00000000000 x 2^1 = 1.01001101100 x 2^1
+FC01_0000_3BFE_04_FE01_0 // f16_add_rz.tv line 45000 FC01_3BFE_FE01_10 NaN + 1.01111111110 x 2^-1 = NaN
+FFFF_0000_44F7_04_FFFF_0 // f16_add_rz.tv line 45500 FFFF_44F7_FFFF_00 NaN + 1.00011110111 x 2^2 = NaN
+CB78_0000_13FF_04_CB77_1 // f16_add_rz.tv line 46000 CB78_13FF_CB77_01 -1.01101111000 x 2^3 + 1.01111111111 x 2^-11 = -1.01101110111 x 2^3
+
+////////// Testcases from f16_mul_rz.tv of type mul rounding mode 0
+0000_FA02_3CFF_08_8000_0 // f16_mul_rz.tv line 500 0000_FA02_8000_00 0 * -1.01000000010 x 2^15 = -Denorm
+93FF_EBFF_3CFF_08_43FE_1 // f16_mul_rz.tv line 1000 93FF_EBFF_43FE_01 -1.01111111111 x 2^-11 * -1.01111111111 x 2^11 = 1.01111111110 x 2^1
+// Skipped denorm f16_mul_rz.tv line 1500 03FF_C401_8BFF_01 Denorm * -1.00000000001 x 2^2 = -1.01111111111 x 2^-13
+// Skipped denorm f16_mul_rz.tv line 2000 03FE_0001_0000_03 Denorm * Denorm = 0
+54CE_BC00_3CFF_08_D4CE_0 // f16_mul_rz.tv line 2500 54CE_BC00_D4CE_00 1.00011001110 x 2^6 * -1.00000000000 x 2^0 = -1.00011001110 x 2^6
+0401_B7FE_3CFF_08_81FF_3 // f16_mul_rz.tv line 3000 0401_B7FE_81FF_03 1.00000000001 x 2^-14 * -1.01111111110 x 2^-2 = -Denorm
+07FF_C3FF_3CFF_08_8FFE_1 // f16_mul_rz.tv line 3500 07FF_C3FF_8FFE_01 1.01111111111 x 2^-14 * -1.01111111111 x 2^1 = -1.01111111110 x 2^-12
+9C3B_87FF_3CFF_08_0008_3 // f16_mul_rz.tv line 4000 9C3B_87FF_0008_03 -1.00000111011 x 2^-8 * -1.01111111111 x 2^-14 = Denorm
+// Skipped denorm f16_mul_rz.tv line 4500 1000_8001_8000_03 1.00000000000 x 2^-11 * -Denorm = -Denorm
+1001_2FBB_3CFF_08_03DE_3 // f16_mul_rz.tv line 5000 1001_2FBB_03DE_03 1.00000000001 x 2^-11 * 1.01110111011 x 2^-4 = Denorm
+37EE_7800_3CFF_08_73EE_0 // f16_mul_rz.tv line 5500 37EE_7800_73EE_00 1.01111101110 x 2^-2 * 1.00000000000 x 2^15 = 1.01111101110 x 2^13
+13FE_47FE_3CFF_08_1FFC_1 // f16_mul_rz.tv line 6000 13FE_47FE_1FFC_01 1.01111111110 x 2^-11 * 1.01111111110 x 2^2 = 1.01111111100 x 2^-8
+3400_CA47_3CFF_08_C247_0 // f16_mul_rz.tv line 6500 3400_CA47_C247_00 1.00000000000 x 2^-2 * -1.01001000111 x 2^3 = -1.01001000111 x 2^1
+30EE_3FFF_3CFF_08_34ED_1 // f16_mul_rz.tv line 7000 30EE_3FFF_34ED_01 1.00011101110 x 2^-3 * 1.01111111111 x 2^0 = 1.00011101101 x 2^-2
+37FF_3801_3CFF_08_3400_1 // f16_mul_rz.tv line 7500 37FF_3801_3400_01 1.01111111111 x 2^-2 * 1.00000000001 x 2^-1 = 1.00000000000 x 2^-2
+37FE_B783_3CFF_08_B381_1 // f16_mul_rz.tv line 8000 37FE_B783_B381_01 1.01111111110 x 2^-2 * -1.01110000011 x 2^-2 = -1.01110000001 x 2^-3
+0EBE_1000_3CFF_08_0003_3 // f16_mul_rz.tv line 8500 0EBE_1000_0003_03 1.01010111110 x 2^-12 * 1.00000000000 x 2^-11 = Denorm
+// Skipped denorm f16_mul_rz.tv line 9000 3801_03FE_01FF_03 1.00000000001 x 2^-1 * Denorm = Denorm
+3801_480F_3CFF_08_4410_1 // f16_mul_rz.tv line 9500 3801_480F_4410_01 1.00000000001 x 2^-1 * 1.00000001111 x 2^3 = 1.00000010000 x 2^2
+// Skipped denorm f16_mul_rz.tv line 10000 003E_FBFF_B3BF_01 Denorm * -1.01111111111 x 2^15 = -1.01110111111 x 2^-3
+3BFE_E801_3CFF_08_E7FF_1 // f16_mul_rz.tv line 10500 3BFE_E801_E7FF_01 1.01111111110 x 2^-1 * -1.00000000001 x 2^11 = -1.01111111111 x 2^10
+3C00_88D3_3CFF_08_88D3_0 // f16_mul_rz.tv line 11000 3C00_88D3_88D3_00 1.00000000000 x 2^0 * -1.00011010011 x 2^-13 = -1.00011010011 x 2^-13
+257F_C000_3CFF_08_A97F_0 // f16_mul_rz.tv line 11500 257F_C000_A97F_00 1.00101111111 x 2^-6 * -1.00000000000 x 2^1 = -1.00101111111 x 2^-5
+3FFF_BBFE_3CFF_08_BFFD_1 // f16_mul_rz.tv line 12000 3FFF_BBFE_BFFD_01 1.01111111111 x 2^0 * -1.01111111110 x 2^-1 = -1.01111111101 x 2^0
+3FFE_4AFD_3CFF_08_4EFB_1 // f16_mul_rz.tv line 12500 3FFE_4AFD_4EFB_01 1.01111111110 x 2^0 * 1.01011111101 x 2^3 = 1.01011111011 x 2^4
+B7FF_93FF_3CFF_08_0FFE_1 // f16_mul_rz.tv line 13000 B7FF_93FF_0FFE_01 -1.01111111111 x 2^-2 * -1.01111111111 x 2^-11 = 1.01111111110 x 2^-12
+4001_8401_3CFF_08_8802_1 // f16_mul_rz.tv line 13500 4001_8401_8802_01 1.00000000001 x 2^1 * -1.00000000001 x 2^-14 = -1.00000000010 x 2^-13
+43FF_3808_3CFF_08_4007_1 // f16_mul_rz.tv line 14000 43FF_3808_4007_01 1.01111111111 x 2^1 * 1.00000001000 x 2^-1 = 1.00000000111 x 2^1
+AC0A_7C00_3CFF_08_FC00_0 // f16_mul_rz.tv line 14500 AC0A_7C00_FC00_00 -1.00000001010 x 2^-4 * INF = -INF
+4400_6BFE_3CFF_08_73FE_0 // f16_mul_rz.tv line 15000 4400_6BFE_73FE_00 1.00000000000 x 2^2 * 1.01111111110 x 2^11 = 1.01111111110 x 2^13
+4401_D3F2_3CFF_08_DBF3_1 // f16_mul_rz.tv line 15500 4401_D3F2_DBF3_01 1.00000000001 x 2^2 * -1.01111110010 x 2^5 = -1.01111110011 x 2^7
+5BC2_43FF_3CFF_08_63C1_1 // f16_mul_rz.tv line 16000 5BC2_43FF_63C1_01 1.01111000010 x 2^7 * 1.01111111111 x 2^1 = 1.01111000001 x 2^9
+47FE_3C01_3CFF_08_47FF_1 // f16_mul_rz.tv line 16500 47FE_3C01_47FF_01 1.01111111110 x 2^2 * 1.00000000001 x 2^0 = 1.01111111111 x 2^2
+6800_13F1_3CFF_08_3FF1_0 // f16_mul_rz.tv line 17000 6800_13F1_3FF1_00 1.00000000000 x 2^11 * 1.01111110001 x 2^-11 = 1.01111110001 x 2^0
+78FB_3400_3CFF_08_70FB_0 // f16_mul_rz.tv line 17500 78FB_3400_70FB_00 1.00011111011 x 2^15 * 1.00000000000 x 2^-2 = 1.00011111011 x 2^13
+6BFF_07FE_3CFF_08_37FD_1 // f16_mul_rz.tv line 18000 6BFF_07FE_37FD_01 1.01111111111 x 2^11 * 1.01111111110 x 2^-14 = 1.01111111101 x 2^-2
+6BFE_13FE_3CFF_08_43FC_1 // f16_mul_rz.tv line 18500 6BFE_13FE_43FC_01 1.01111111110 x 2^11 * 1.01111111110 x 2^-11 = 1.01111111100 x 2^1
+382F_FFFF_3CFF_08_FFFF_0 // f16_mul_rz.tv line 19000 382F_FFFF_FFFF_00 1.00000101111 x 2^-1 * NaN = NaN
+7800_F801_3CFF_08_FBFF_5 // f16_mul_rz.tv line 19500 7800_F801_FBFF_05 1.00000000000 x 2^15 * -1.00000000001 x 2^15 = -1.01111111111 x 2^15
+7801_4877_3CFF_08_7BFF_5 // f16_mul_rz.tv line 20000 7801_4877_7BFF_05 1.00000000001 x 2^15 * 1.00001110111 x 2^3 = 1.01111111111 x 2^15
+// Skipped denorm f16_mul_rz.tv line 20500 0090_C400_8240_00 Denorm * -1.00000000000 x 2^2 = -Denorm
+7BFE_BFFE_3CFF_08_FBFF_5 // f16_mul_rz.tv line 21000 7BFE_BFFE_FBFF_05 1.01111111110 x 2^15 * -1.01111111110 x 2^0 = -1.01111111111 x 2^15
+7C00_4F08_3CFF_08_7C00_0 // f16_mul_rz.tv line 21500 7C00_4F08_7C00_00 INF * 1.01100001000 x 2^4 = INF
+BFFA_B7FF_3CFF_08_3BF9_1 // f16_mul_rz.tv line 22000 BFFA_B7FF_3BF9_01 -1.01111111010 x 2^0 * -1.01111111111 x 2^-2 = 1.01111111001 x 2^-1
+7FFF_9001_3CFF_08_7FFF_0 // f16_mul_rz.tv line 22500 7FFF_9001_7FFF_00 NaN * -1.00000000001 x 2^-11 = NaN
+7FFE_B82F_3CFF_08_7FFE_0 // f16_mul_rz.tv line 23000 7FFE_B82F_7FFE_00 NaN * -1.00000101111 x 2^-1 = NaN
+// Skipped denorm f16_mul_rz.tv line 23500 2F68_8000_8000_00 1.01101101000 x 2^-4 * -Denorm = -Denorm
+// Skipped denorm f16_mul_rz.tv line 24000 8001_7BFE_9BFE_00 -Denorm * 1.01111111110 x 2^15 = -1.01111111110 x 2^-9
+// Skipped denorm f16_mul_rz.tv line 24500 83FF_EB8E_338C_01 -Denorm * -1.01110001110 x 2^11 = 1.01110001100 x 2^-3
+75FF_47FF_3CFF_08_7BFF_5 // f16_mul_rz.tv line 25000 75FF_47FF_7BFF_05 1.00111111111 x 2^14 * 1.01111111111 x 2^2 = 1.01111111111 x 2^15
+8400_4001_3CFF_08_8801_0 // f16_mul_rz.tv line 25500 8400_4001_8801_00 -1.00000000000 x 2^-14 * 1.00000000001 x 2^1 = -1.00000000001 x 2^-13
+8401_C3E7_3CFF_08_0BE8_1 // f16_mul_rz.tv line 26000 8401_C3E7_0BE8_01 -1.00000000001 x 2^-14 * -1.01111100111 x 2^1 = 1.01111101000 x 2^-13
+CC00_3800_3CFF_08_C800_0 // f16_mul_rz.tv line 26500 CC00_3800_C800_00 -1.00000000000 x 2^4 * 1.00000000000 x 2^-1 = -1.00000000000 x 2^3
+87FE_13FE_3CFF_08_8001_3 // f16_mul_rz.tv line 27000 87FE_13FE_8001_03 -1.01111111110 x 2^-14 * 1.01111111110 x 2^-11 = -Denorm
+9000_7FF2_3CFF_08_7FF2_0 // f16_mul_rz.tv line 27500 9000_7FF2_7FF2_00 -1.00000000000 x 2^-11 * NaN = NaN
+// Skipped denorm f16_mul_rz.tv line 28000 C082_03FF_8880_01 -1.00010000010 x 2^1 * Denorm = -1.00010000000 x 2^-13
+9001_FC01_3CFF_08_FE01_0 // f16_mul_rz.tv line 28500 9001_FC01_FE01_10 -1.00000000001 x 2^-11 * NaN = NaN
+93FF_2DFF_3CFF_08_85FE_1 // f16_mul_rz.tv line 29000 93FF_2DFF_85FE_01 -1.01111111111 x 2^-11 * 1.00111111111 x 2^-4 = -1.00111111110 x 2^-14
+BE01_E800_3CFF_08_6A01_0 // f16_mul_rz.tv line 29500 BE01_E800_6A01_00 -1.01000000001 x 2^0 * -1.00000000000 x 2^11 = 1.01000000001 x 2^11
+B400_C3FE_3CFF_08_3BFE_0 // f16_mul_rz.tv line 30000 B400_C3FE_3BFE_00 -1.00000000000 x 2^-2 * -1.01111111110 x 2^1 = 1.01111111110 x 2^-1
+B401_2702_3CFF_08_9F03_1 // f16_mul_rz.tv line 30500 B401_2702_9F03_01 -1.00000000001 x 2^-2 * 1.01100000010 x 2^-6 = -1.01100000011 x 2^-8
+E09F_BBFF_3CFF_08_609E_1 // f16_mul_rz.tv line 31000 E09F_BBFF_609E_01 -1.00010011111 x 2^9 * -1.01111111111 x 2^-1 = 1.00010011110 x 2^9
+B7FE_B401_3CFF_08_2FFF_1 // f16_mul_rz.tv line 31500 B7FE_B401_2FFF_01 -1.01111111110 x 2^-2 * -1.00000000001 x 2^-2 = 1.01111111111 x 2^-4
+// Skipped denorm f16_mul_rz.tv line 32000 B800_80BF_005F_03 -1.00000000000 x 2^-1 * -Denorm = Denorm
+6BBC_8400_3CFF_08_B3BC_0 // f16_mul_rz.tv line 32500 6BBC_8400_B3BC_00 1.01110111100 x 2^11 * -1.00000000000 x 2^-14 = -1.01110111100 x 2^-3
+BBFF_7FFE_3CFF_08_7FFE_0 // f16_mul_rz.tv line 33000 BBFF_7FFE_7FFE_00 -1.01111111111 x 2^-1 * NaN = NaN
+BBFE_09DF_3CFF_08_89DD_1 // f16_mul_rz.tv line 33500 BBFE_09DF_89DD_01 -1.01111111110 x 2^-1 * 1.00111011111 x 2^-13 = -1.00111011101 x 2^-13
+124E_6BFF_3CFF_08_424D_1 // f16_mul_rz.tv line 34000 124E_6BFF_424D_01 1.01001001110 x 2^-11 * 1.01111111111 x 2^11 = 1.01001001101 x 2^1
+BC01_4401_3CFF_08_C402_1 // f16_mul_rz.tv line 34500 BC01_4401_C402_01 -1.00000000001 x 2^0 * 1.00000000001 x 2^2 = -1.00000000010 x 2^2
+BFFF_10BF_3CFF_08_94BE_1 // f16_mul_rz.tv line 35000 BFFF_10BF_94BE_01 -1.01111111111 x 2^0 * 1.00010111111 x 2^-11 = -1.00010111110 x 2^-10
+48EF_3C00_3CFF_08_48EF_0 // f16_mul_rz.tv line 35500 48EF_3C00_48EF_00 1.00011101111 x 2^3 * 1.00000000000 x 2^0 = 1.00011101111 x 2^3
+C000_37FE_3CFF_08_BBFE_0 // f16_mul_rz.tv line 36000 C000_37FE_BBFE_00 -1.00000000000 x 2^1 * 1.01111111110 x 2^-2 = -1.01111111110 x 2^-1
+// Skipped denorm f16_mul_rz.tv line 36500 C001_021F_843F_01 -1.00000000001 x 2^1 * Denorm = -1.00000111111 x 2^-14
+1180_07FF_3CFF_08_0001_3 // f16_mul_rz.tv line 37000 1180_07FF_0001_03 1.00110000000 x 2^-11 * 1.01111111111 x 2^-14 = Denorm
+// Skipped denorm f16_mul_rz.tv line 37500 C3FE_0001_8003_03 -1.01111111110 x 2^1 * Denorm = -Denorm
+// Skipped denorm f16_mul_rz.tv line 38000 C3FE_00FF_83FB_03 -1.01111111110 x 2^1 * Denorm = -Denorm
+1A7C_F800_3CFF_08_D67C_0 // f16_mul_rz.tv line 38500 1A7C_F800_D67C_00 1.01001111100 x 2^-9 * -1.00000000000 x 2^15 = -1.01001111100 x 2^6
+C401_C7FE_3CFF_08_4FFF_1 // f16_mul_rz.tv line 39000 C401_C7FE_4FFF_01 -1.00000000001 x 2^2 * -1.01111111110 x 2^2 = 1.01111111111 x 2^4
+C7FF_C73F_3CFF_08_533E_1 // f16_mul_rz.tv line 39500 C7FF_C73F_533E_01 -1.01111111111 x 2^2 * -1.01100111111 x 2^2 = 1.01100111110 x 2^5
+3F10_BFFF_3CFF_08_C30F_1 // f16_mul_rz.tv line 40000 3F10_BFFF_C30F_01 1.01100010000 x 2^0 * -1.01111111111 x 2^0 = -1.01100001111 x 2^1
+E800_B801_3CFF_08_6401_0 // f16_mul_rz.tv line 40500 E800_B801_6401_00 -1.00000000000 x 2^11 * -1.00000000001 x 2^-1 = 1.00000000001 x 2^10
+E801_B387_3CFF_08_5F88_1 // f16_mul_rz.tv line 41000 E801_B387_5F88_01 -1.00000000001 x 2^11 * -1.01110000111 x 2^-3 = 1.01110001000 x 2^8
+CBE1_9000_3CFF_08_1FE1_0 // f16_mul_rz.tv line 41500 CBE1_9000_1FE1_00 -1.01111100001 x 2^3 * -1.00000000000 x 2^-11 = 1.01111100001 x 2^-8
+// Skipped denorm f16_mul_rz.tv line 42000 EBFE_83FE_33FA_01 -1.01111111110 x 2^11 * -Denorm = 1.01111111010 x 2^-3
+F800_3F00_3CFF_08_FB00_0 // f16_mul_rz.tv line 42500 F800_3F00_FB00_00 -1.00000000000 x 2^15 * 1.01100000000 x 2^0 = -1.01100000000 x 2^15
+CFBF_7BFF_3CFF_08_FBFF_5 // f16_mul_rz.tv line 43000 CFBF_7BFF_FBFF_05 -1.01110111111 x 2^4 * 1.01111111111 x 2^15 = -1.01111111111 x 2^15
+FBFF_6801_3CFF_08_FBFF_5 // f16_mul_rz.tv line 43500 FBFF_6801_FBFF_05 -1.01111111111 x 2^15 * 1.00000000001 x 2^11 = -1.01111111111 x 2^15
+FBFE_11FF_3CFF_08_D1FD_1 // f16_mul_rz.tv line 44000 FBFE_11FF_D1FD_01 -1.01111111110 x 2^15 * 1.00111111111 x 2^-11 = -1.00111111101 x 2^5
+3CD8_4000_3CFF_08_40D8_0 // f16_mul_rz.tv line 44500 3CD8_4000_40D8_00 1.00011011000 x 2^0 * 1.00000000000 x 2^1 = 1.00011011000 x 2^1
+FC01_3BFE_3CFF_08_FE01_0 // f16_mul_rz.tv line 45000 FC01_3BFE_FE01_10 NaN * 1.01111111110 x 2^-1 = NaN
+FFFF_44F7_3CFF_08_FFFF_0 // f16_mul_rz.tv line 45500 FFFF_44F7_FFFF_00 NaN * 1.00011110111 x 2^2 = NaN
+CB78_13FF_3CFF_08_A377_1 // f16_mul_rz.tv line 46000 CB78_13FF_A377_01 -1.01101111000 x 2^3 * 1.01111111111 x 2^-11 = -1.01101110111 x 2^-7
+
+////////// Testcases from f16_mulAdd_rz.tv of type mulAdd rounding mode 0
+0000_0BE3_B9AB_0c_B9AB_0 // f16_mulAdd_rz.tv line 50000 0000_0BE3_B9AB_B9AB_00 0 * 1.01111100011 x 2^-13 + -1.00110101011 x 2^-1 = -1.00110101011 x 2^-1
+2FC7_E793_3FFE_0c_DB4D_1 // f16_mulAdd_rz.tv line 100000 2FC7_E793_3FFE_DB4D_01 1.01111000111 x 2^-4 * -1.01110010011 x 2^10 + 1.01111111110 x 2^0 = -1.01101001101 x 2^7
+4B04_3401_4EC1_0c_4FA1_1 // f16_mulAdd_rz.tv line 150000 4B04_3401_4EC1_4FA1_01 1.01100000100 x 2^3 * 1.00000000001 x 2^-2 + 1.01011000001 x 2^4 = 1.01110100001 x 2^4
+// Skipped denorm f16_mulAdd_rz.tv line 200000 03FF_E800_F732_F732_01 Denorm * -1.00000000000 x 2^11 + -1.01100110010 x 2^14 = -1.01100110010 x 2^14
+// Skipped denorm f16_mulAdd_rz.tv line 250000 03FE_D4FF_B401_B414_01 Denorm * -1.00011111111 x 2^6 + -1.00000000001 x 2^-2 = -1.00000010100 x 2^-2
+C411_63FF_D382_0c_EC1F_1 // f16_mulAdd_rz.tv line 300000 C411_63FF_D382_EC1F_01 -1.00000010001 x 2^2 * 1.01111111111 x 2^9 + -1.01110000010 x 2^5 = -1.00000011111 x 2^12
+B7E7_A09F_CC08_0c_CC07_1 // f16_mulAdd_rz.tv line 350000 B7E7_A09F_CC08_CC07_01 -1.01111100111 x 2^-2 * -1.00010011111 x 2^-7 + -1.00000001000 x 2^4 = -1.00000000111 x 2^4
+90BB_BC01_0400_0c_113C_1 // f16_mulAdd_rz.tv line 400000 90BB_BC01_0400_113C_01 -1.00010111011 x 2^-11 * -1.00000000001 x 2^0 + 1.00000000000 x 2^-14 = 1.00100111100 x 2^-11
+07FF_7C00_37FE_0c_7C00_0 // f16_mulAdd_rz.tv line 450000 07FF_7C00_37FE_7C00_00 1.01111111111 x 2^-14 * INF + 1.01111111110 x 2^-2 = INF
+07FE_C197_6C7F_0c_6C7E_1 // f16_mulAdd_rz.tv line 500000 07FE_C197_6C7F_6C7E_01 1.01111111110 x 2^-14 * -1.00110010111 x 2^1 + 1.00001111111 x 2^12 = 1.00001111110 x 2^12
+BC13_2BD7_7BFE_0c_7BFD_1 // f16_mulAdd_rz.tv line 550000 BC13_2BD7_7BFE_7BFD_01 -1.00000010011 x 2^0 * 1.01111010111 x 2^-5 + 1.01111111110 x 2^15 = 1.01111111101 x 2^15
+B5BB_9001_6846_0c_6846_1 // f16_mulAdd_rz.tv line 600000 B5BB_9001_6846_6846_01 -1.00110111011 x 2^-2 * -1.00000000001 x 2^-11 + 1.00001000110 x 2^11 = 1.00001000110 x 2^11
+1001_4400_C0DF_0c_C0DD_1 // f16_mulAdd_rz.tv line 650000 1001_4400_C0DF_C0DD_01 1.00000000001 x 2^-11 * 1.00000000000 x 2^2 + -1.00011011111 x 2^1 = -1.00011011101 x 2^1
+13FF_2C01_C401_0c_C400_1 // f16_mulAdd_rz.tv line 700000 13FF_2C01_C401_C400_01 1.01111111111 x 2^-11 * 1.00000000001 x 2^-4 + -1.00000000001 x 2^2 = -1.00000000000 x 2^2
+ABBF_BBA9_BB78_0c_BB01_1 // f16_mulAdd_rz.tv line 750000 ABBF_BBA9_BB78_BB01_01 -1.01110111111 x 2^-5 * -1.01110101001 x 2^-1 + -1.01101111000 x 2^-1 = -1.01100000001 x 2^-1
+8409_3401_AEBF_0c_AEBF_1 // f16_mulAdd_rz.tv line 800000 8409_3401_AEBF_AEBF_01 -1.00000001001 x 2^-14 * 1.00000000001 x 2^-2 + -1.01010111111 x 2^-4 = -1.01010111111 x 2^-4
+41FE_3801_3C00_0c_40FF_1 // f16_mulAdd_rz.tv line 850000 41FE_3801_3C00_40FF_01 1.00111111110 x 2^1 * 1.00000000001 x 2^-1 + 1.00000000000 x 2^0 = 1.00011111111 x 2^1
+3400_F800_47FE_0c_EFFE_1 // f16_mulAdd_rz.tv line 900000 3400_F800_47FE_EFFE_01 1.00000000000 x 2^-2 * -1.00000000000 x 2^15 + 1.01111111110 x 2^2 = -1.01111111110 x 2^12
+3401_BFCE_F963_0c_F963_1 // f16_mulAdd_rz.tv line 950000 3401_BFCE_F963_F963_01 1.00000000001 x 2^-2 * -1.01111001110 x 2^0 + -1.00101100011 x 2^15 = -1.00101100011 x 2^15
+C8C0_1018_93FE_0c_9DDC_1 // f16_mulAdd_rz.tv line 1000000 C8C0_1018_93FE_9DDC_01 -1.00011000000 x 2^3 * 1.00000011000 x 2^-11 + -1.01111111110 x 2^-11 = -1.00111011100 x 2^-8
+CA7E_0401_CEEE_0c_CEEE_1 // f16_mulAdd_rz.tv line 1050000 CA7E_0401_CEEE_CEEE_01 -1.01001111110 x 2^3 * 1.00000000001 x 2^-14 + -1.01011101110 x 2^4 = -1.01011101110 x 2^4
+37FE_C000_B301_0c_BCDF_1 // f16_mulAdd_rz.tv line 1100000 37FE_C000_B301_BCDF_01 1.01111111110 x 2^-2 * -1.00000000000 x 2^1 + -1.01100000001 x 2^-3 = -1.00011011111 x 2^0
+// Skipped denorm f16_mulAdd_rz.tv line 1150000 3800_5277_0001_4E77_01 1.00000000000 x 2^-1 * 1.01001110111 x 2^5 + Denorm = 1.01001110111 x 2^4
+747B_6881_F708_0c_7BFF_5 // f16_mulAdd_rz.tv line 1200000 747B_6881_F708_7BFF_05 1.00001111011 x 2^14 * 1.00010000001 x 2^11 + -1.01100001000 x 2^14 = 1.01111111111 x 2^15
+C80C_C67F_93FF_0c_5292_1 // f16_mulAdd_rz.tv line 1250000 C80C_C67F_93FF_5292_01 -1.00000001100 x 2^3 * -1.01001111111 x 2^2 + -1.01111111111 x 2^-11 = 1.01010010010 x 2^5
+46DF_B401_7800_0c_77FF_1 // f16_mulAdd_rz.tv line 1300000 46DF_B401_7800_77FF_01 1.01011011111 x 2^2 * -1.00000000001 x 2^-2 + 1.00000000000 x 2^15 = 1.01111111111 x 2^14
+// Skipped denorm f16_mulAdd_rz.tv line 1350000 3BFE_6800_83FE_67FD_01 1.01111111110 x 2^-1 * 1.00000000000 x 2^11 + -Denorm = 1.01111111101 x 2^10
+3C00_CFBE_AC04_0c_CFC2_1 // f16_mulAdd_rz.tv line 1400000 3C00_CFBE_AC04_CFC2_01 1.00000000000 x 2^0 * -1.01110111110 x 2^4 + -1.00000000100 x 2^-4 = -1.01111000010 x 2^4
+E877_C512_C3FE_0c_71A8_1 // f16_mulAdd_rz.tv line 1450000 E877_C512_C3FE_71A8_01 -1.00001110111 x 2^11 * -1.00100010010 x 2^2 + -1.01111111110 x 2^1 = 1.00110101000 x 2^13
+// Skipped denorm f16_mulAdd_rz.tv line 1500000 C011_8001_400B_400B_01 -1.00000010001 x 2^1 * -Denorm + 1.00000001011 x 2^1 = 1.00000001011 x 2^1
+3FFF_3C01_B43B_0c_3EF2_1 // f16_mulAdd_rz.tv line 1550000 3FFF_3C01_B43B_3EF2_01 1.01111111111 x 2^0 * 1.00000000001 x 2^0 + -1.00000111011 x 2^-2 = 1.01011110010 x 2^0
+3FFF_CD3F_3801_0c_D12E_1 // f16_mulAdd_rz.tv line 1600000 3FFF_CD3F_3801_D12E_01 1.01111111111 x 2^0 * -1.00100111111 x 2^4 + 1.00000000001 x 2^-1 = -1.00100101110 x 2^5
+325F_6B90_1607_0c_6205_1 // f16_mulAdd_rz.tv line 1650000 325F_6B90_1607_6205_01 1.01001011111 x 2^-3 * 1.01110010000 x 2^11 + 1.01000000111 x 2^-10 = 1.01000000101 x 2^9
+7B86_BFFA_1CFC_0c_FBFF_5 // f16_mulAdd_rz.tv line 1700000 7B86_BFFA_1CFC_FBFF_05 1.01110000110 x 2^15 * -1.01111111010 x 2^0 + 1.00011111100 x 2^-8 = -1.01111111111 x 2^15
+D61E_1001_9000_0c_AA2F_1 // f16_mulAdd_rz.tv line 1750000 D61E_1001_9000_AA2F_01 -1.01000011110 x 2^6 * 1.00000000001 x 2^-11 + -1.00000000000 x 2^-11 = -1.01000101111 x 2^-5
+4001_C400_BBFE_0c_C880_1 // f16_mulAdd_rz.tv line 1800000 4001_C400_BBFE_C880_01 1.00000000001 x 2^1 * -1.00000000000 x 2^2 + -1.01111111110 x 2^-1 = -1.00010000000 x 2^3
+43FF_4500_C91D_0c_48E1_1 // f16_mulAdd_rz.tv line 1850000 43FF_4500_C91D_48E1_01 1.01111111111 x 2^1 * 1.00100000000 x 2^2 + -1.00100011101 x 2^3 = 1.00011100001 x 2^3
+B710_BB18_FFFE_0c_FFFE_0 // f16_mulAdd_rz.tv line 1900000 B710_BB18_FFFE_FFFE_00 -1.01100010000 x 2^-2 * -1.01100011000 x 2^-1 + NaN = NaN
+6817_FFFF_B85F_0c_FFFF_0 // f16_mulAdd_rz.tv line 1950000 6817_FFFF_B85F_FFFF_00 1.00000010111 x 2^11 * NaN + -1.00001011111 x 2^-1 = NaN
+4400_B801_D510_0c_D530_1 // f16_mulAdd_rz.tv line 2000000 4400_B801_D510_D530_01 1.00000000000 x 2^2 * -1.00000000001 x 2^-1 + -1.00100010000 x 2^6 = -1.00100110000 x 2^6
+4401_43E6_6801_0c_6808_1 // f16_mulAdd_rz.tv line 2050000 4401_43E6_6801_6808_01 1.00000000001 x 2^2 * 1.01111100110 x 2^1 + 1.00000000001 x 2^11 = 1.00000001000 x 2^11
+// Skipped denorm f16_mulAdd_rz.tv line 2100000 FF2B_4784_0376_FF2B_00 NaN * 1.01110000100 x 2^2 + Denorm = NaN
+497E_BBDB_46E6_0c_C3C6_1 // f16_mulAdd_rz.tv line 2150000 497E_BBDB_46E6_C3C6_01 1.00101111110 x 2^3 * -1.01111011011 x 2^-1 + 1.01011100110 x 2^2 = -1.01111000110 x 2^1
+2FD8_8401_C000_0c_C000_1 // f16_mulAdd_rz.tv line 2200000 2FD8_8401_C000_C000_01 1.01111011000 x 2^-4 * -1.00000000001 x 2^-14 + -1.00000000000 x 2^1 = -1.00000000000 x 2^1
+6800_4000_EBFE_0c_4400_0 // f16_mulAdd_rz.tv line 2250000 6800_4000_EBFE_4400_00 1.00000000000 x 2^11 * 1.00000000000 x 2^1 + -1.01111111110 x 2^11 = 1.00000000000 x 2^2
+// Skipped denorm f16_mulAdd_rz.tv line 2300000 6801_800C_305F_3052_01 1.00000000001 x 2^11 * -Denorm + 1.00001011111 x 2^-3 = 1.00001010010 x 2^-3
+C0E9_B2FF_37FE_0c_3C25_1 // f16_mulAdd_rz.tv line 2350000 C0E9_B2FF_37FE_3C25_01 -1.00011101001 x 2^1 * -1.01011111111 x 2^-3 + 1.01111111110 x 2^-2 = 1.00000100101 x 2^0
+6A7F_7BFF_7405_0c_7BFF_5 // f16_mulAdd_rz.tv line 2400000 6A7F_7BFF_7405_7BFF_05 1.01001111111 x 2^11 * 1.01111111111 x 2^15 + 1.00000000101 x 2^14 = 1.01111111111 x 2^15
+6BFE_3401_B87A_0c_63FE_1 // f16_mulAdd_rz.tv line 2450000 6BFE_3401_B87A_63FE_01 1.01111111110 x 2^11 * 1.00000000001 x 2^-2 + -1.00001111010 x 2^-1 = 1.01111111110 x 2^9
+6BFE_343E_8401_0c_643C_1 // f16_mulAdd_rz.tv line 2500000 6BFE_343E_8401_643C_01 1.01111111110 x 2^11 * 1.00000111110 x 2^-2 + -1.00000000001 x 2^-14 = 1.00000111100 x 2^10
+// Skipped denorm f16_mulAdd_rz.tv line 2550000 3D03_02FB_AFFE_AFFD_01 1.00100000011 x 2^0 * Denorm + -1.01111111110 x 2^-4 = -1.01111111101 x 2^-4
+7A10_47D2_AC4E_0c_7BFF_5 // f16_mulAdd_rz.tv line 2600000 7A10_47D2_AC4E_7BFF_05 1.01000010000 x 2^15 * 1.01111010010 x 2^2 + -1.00001001110 x 2^-4 = 1.01111111111 x 2^15
+// Skipped denorm f16_mulAdd_rz.tv line 2650000 FBFE_0001_FC00_FC00_00 -1.01111111110 x 2^15 * Denorm + -INF = -INF
+7BFF_BC01_07FE_0c_FBFF_5 // f16_mulAdd_rz.tv line 2700000 7BFF_BC01_07FE_FBFF_05 1.01111111111 x 2^15 * -1.00000000001 x 2^0 + 1.01111111110 x 2^-14 = -1.01111111111 x 2^15
+7BFE_310F_5000_0c_7111_1 // f16_mulAdd_rz.tv line 2750000 7BFE_310F_5000_7111_01 1.01111111110 x 2^15 * 1.00100001111 x 2^-3 + 1.00000000000 x 2^5 = 1.00100010001 x 2^13
+7933_17DE_47FE_0c_559C_1 // f16_mulAdd_rz.tv line 2800000 7933_17DE_47FE_559C_01 1.00100110011 x 2^15 * 1.01111011110 x 2^-10 + 1.01111111110 x 2^2 = 1.00110011100 x 2^6
+// Skipped denorm f16_mulAdd_rz.tv line 2850000 0083_EBFF_B00F_B114_01 Denorm * -1.01111111111 x 2^11 + -1.00000001111 x 2^-3 = -1.00100010100 x 2^-3
+7C01_9001_406F_0c_7E01_0 // f16_mulAdd_rz.tv line 2900000 7C01_9001_406F_7E01_10 NaN * -1.00000000001 x 2^-11 + 1.00001101111 x 2^1 = NaN
+7FFF_E3C7_BC01_0c_7FFF_0 // f16_mulAdd_rz.tv line 2950000 7FFF_E3C7_BC01_7FFF_00 NaN * -1.01111000111 x 2^9 + -1.00000000001 x 2^0 = NaN
+C4FF_87CF_2FDC_0c_2FE5_1 // f16_mulAdd_rz.tv line 3000000 C4FF_87CF_2FDC_2FE5_01 -1.00011111111 x 2^2 * -1.01111001111 x 2^-14 + 1.01111011100 x 2^-4 = 1.01111100101 x 2^-4
+87F8_6016_4AB3_0c_4AAA_1 // f16_mulAdd_rz.tv line 3050000 87F8_6016_4AB3_4AAA_01 -1.01111111000 x 2^-14 * 1.00000010110 x 2^9 + 1.01010110011 x 2^3 = 1.01010101010 x 2^3
+785F_7FFF_3400_0c_7FFF_0 // f16_mulAdd_rz.tv line 3100000 785F_7FFF_3400_7FFF_00 1.00001011111 x 2^15 * NaN + 1.00000000000 x 2^-2 = NaN
+// Skipped denorm f16_mulAdd_rz.tv line 3150000 8001_3801_3FFE_3FFD_01 -Denorm * 1.00000000001 x 2^-1 + 1.01111111110 x 2^0 = 1.01111111101 x 2^0
+// Skipped denorm f16_mulAdd_rz.tv line 3200000 8001_9376_03E0_03E0_03 -Denorm * -1.01101110110 x 2^-11 + Denorm = Denorm
+// Skipped denorm f16_mulAdd_rz.tv line 3250000 BBF8_3103_83FE_B0FE_01 -1.01111111000 x 2^-1 * 1.00100000011 x 2^-3 + -Denorm = -1.00011111110 x 2^-3
+4702_47FF_5F80_0c_6030_1 // f16_mulAdd_rz.tv line 3300000 4702_47FF_5F80_6030_01 1.01100000010 x 2^2 * 1.01111111111 x 2^2 + 1.01110000000 x 2^8 = 1.00000110000 x 2^9
+8400_0401_4010_0c_400F_1 // f16_mulAdd_rz.tv line 3350000 8400_0401_4010_400F_01 -1.00000000000 x 2^-14 * 1.00000000001 x 2^-14 + 1.00000010000 x 2^1 = 1.00000001111 x 2^1
+8400_33B6_F801_0c_F801_1 // f16_mulAdd_rz.tv line 3400000 8400_33B6_F801_F801_01 -1.00000000000 x 2^-14 * 1.01110110110 x 2^-3 + -1.00000000001 x 2^15 = -1.00000000001 x 2^15
+DAAF_4B90_C7BD_0c_EA55_1 // f16_mulAdd_rz.tv line 3450000 DAAF_4B90_C7BD_EA55_01 -1.01010101111 x 2^7 * 1.01110010000 x 2^3 + -1.01110111101 x 2^2 = -1.01001010101 x 2^11
+9021_32AD_B399_0c_B399_1 // f16_mulAdd_rz.tv line 3500000 9021_32AD_B399_B399_01 -1.00000100001 x 2^-11 * 1.01010101101 x 2^-3 + -1.01110011001 x 2^-3 = -1.01110011001 x 2^-3
+AF8F_FBFF_4400_0c_6F8F_1 // f16_mulAdd_rz.tv line 3550000 AF8F_FBFF_4400_6F8F_01 -1.01110001111 x 2^-4 * -1.01111111111 x 2^15 + 1.00000000000 x 2^2 = 1.01110001111 x 2^12
+87FE_B401_7BFE_0c_7BFE_1 // f16_mulAdd_rz.tv line 3600000 87FE_B401_7BFE_7BFE_01 -1.01111111110 x 2^-14 * -1.00000000001 x 2^-2 + 1.01111111110 x 2^15 = 1.01111111110 x 2^15
+9000_8E7C_0BAF_0c_0BB0_1 // f16_mulAdd_rz.tv line 3650000 9000_8E7C_0BAF_0BB0_01 -1.00000000000 x 2^-11 * -1.01001111100 x 2^-12 + 1.01110101111 x 2^-13 = 1.01110110000 x 2^-13
+744C_95FA_BBFE_0c_CEAB_1 // f16_mulAdd_rz.tv line 3700000 744C_95FA_BBFE_CEAB_01 1.00001001100 x 2^14 * -1.00111111010 x 2^-10 + -1.01111111110 x 2^-1 = -1.01010101011 x 2^4
+42FE_C3FF_B81C_0c_CB3E_1 // f16_mulAdd_rz.tv line 3750000 42FE_C3FF_B81C_CB3E_01 1.01011111110 x 2^1 * -1.01111111111 x 2^1 + -1.00000011100 x 2^-1 = -1.01100111110 x 2^3
+// Skipped denorm f16_mulAdd_rz.tv line 3800000 93FF_8001_88FE_88FD_01 -1.01111111111 x 2^-11 * -Denorm + -1.00011111110 x 2^-13 = -1.00011111101 x 2^-13
+93FE_7401_1001_0c_CBFF_1 // f16_mulAdd_rz.tv line 3850000 93FE_7401_1001_CBFF_01 -1.01111111110 x 2^-11 * 1.00000000001 x 2^14 + 1.00000000001 x 2^-11 = -1.01111111111 x 2^3
+3C16_42F4_43E1_0c_477D_1 // f16_mulAdd_rz.tv line 3900000 3C16_42F4_43E1_477D_01 1.00000010110 x 2^0 * 1.01011110100 x 2^1 + 1.01111100001 x 2^1 = 1.01101111101 x 2^2
+7FBF_47FF_C18F_0c_7FBF_0 // f16_mulAdd_rz.tv line 3950000 7FBF_47FF_C18F_7FBF_00 NaN * 1.01111111111 x 2^2 + -1.00110001111 x 2^1 = NaN
+// Skipped denorm f16_mulAdd_rz.tv line 4000000 441E_6BFF_8000_741D_01 1.00000011110 x 2^2 * 1.01111111111 x 2^11 + -Denorm = 1.00000011101 x 2^14
+B7FF_1001_93FE_0c_94FF_1 // f16_mulAdd_rz.tv line 4050000 B7FF_1001_93FE_94FF_01 -1.01111111111 x 2^-2 * 1.00000000001 x 2^-11 + -1.01111111110 x 2^-11 = -1.00011111111 x 2^-10
+B7FF_C9C0_47DF_0c_4ACF_1 // f16_mulAdd_rz.tv line 4100000 B7FF_C9C0_47DF_4ACF_01 -1.01111111111 x 2^-2 * -1.00111000000 x 2^3 + 1.01111011111 x 2^2 = 1.01011001111 x 2^3
+C40F_AB7F_EBFE_0c_EBFD_1 // f16_mulAdd_rz.tv line 4150000 C40F_AB7F_EBFE_EBFD_01 -1.00000001111 x 2^2 * -1.01101111111 x 2^-5 + -1.01111111110 x 2^11 = -1.01111111101 x 2^11
+D404_3FFE_EAF9_0c_EB39_1 // f16_mulAdd_rz.tv line 4200000 D404_3FFE_EAF9_EB39_01 -1.00000000100 x 2^6 * 1.01111111110 x 2^0 + -1.01011111001 x 2^11 = -1.01100111001 x 2^11
+B800_FFFF_F201_0c_FFFF_0 // f16_mulAdd_rz.tv line 4250000 B800_FFFF_F201_FFFF_00 -1.00000000000 x 2^-1 * NaN + -1.01000000001 x 2^13 = NaN
+B801_3D3F_4001_0c_3D61_1 // f16_mulAdd_rz.tv line 4300000 B801_3D3F_4001_3D61_01 -1.00000000001 x 2^-1 * 1.00100111111 x 2^0 + 1.00000000001 x 2^1 = 1.00101100001 x 2^0
+4FFF_4D63_77FF_0c_7815_1 // f16_mulAdd_rz.tv line 4350000 4FFF_4D63_77FF_7815_01 1.01111111111 x 2^4 * 1.00101100011 x 2^4 + 1.01111111111 x 2^14 = 1.00000010101 x 2^15
+C41B_0FA0_C902_0c_C902_1 // f16_mulAdd_rz.tv line 4400000 C41B_0FA0_C902_C902_01 -1.00000011011 x 2^2 * 1.01110100000 x 2^-12 + -1.00100000010 x 2^3 = -1.00100000010 x 2^3
+B7C2_C7FF_B800_0c_42C1_1 // f16_mulAdd_rz.tv line 4450000 B7C2_C7FF_B800_42C1_01 -1.01111000010 x 2^-2 * -1.01111111111 x 2^2 + -1.00000000000 x 2^-1 = 1.01011000001 x 2^1
+BC00_8401_C3FE_0c_C3FD_1 // f16_mulAdd_rz.tv line 4500000 BC00_8401_C3FE_C3FD_01 -1.00000000000 x 2^0 * -1.00000000001 x 2^-14 + -1.01111111110 x 2^1 = -1.01111111101 x 2^1
+BC01_6800_D06F_0c_E812_1 // f16_mulAdd_rz.tv line 4550000 BC01_6800_D06F_E812_01 -1.00000000001 x 2^0 * 1.00000000000 x 2^11 + -1.00001101111 x 2^5 = -1.00000010010 x 2^11
+CFBC_931A_07FE_0c_26E5_1 // f16_mulAdd_rz.tv line 4600000 CFBC_931A_07FE_26E5_01 -1.01110111100 x 2^4 * -1.01100011010 x 2^-11 + 1.01111111110 x 2^-14 = 1.01011100101 x 2^-6
+7C70_BBFE_27F8_0c_7E70_0 // f16_mulAdd_rz.tv line 4650000 7C70_BBFE_27F8_7E70_10 NaN * -1.01111111110 x 2^-1 + 1.01111111000 x 2^-6 = NaN
+BFFE_7BFF_D3DF_0c_FBFF_5 // f16_mulAdd_rz.tv line 4700000 BFFE_7BFF_D3DF_FBFF_05 -1.01111111110 x 2^0 * 1.01111111111 x 2^15 + -1.01111011111 x 2^5 = -1.01111111111 x 2^15
+C000_2383_7C01_0c_7E01_0 // f16_mulAdd_rz.tv line 4750000 C000_2383_7C01_7E01_10 -1.00000000000 x 2^1 * 1.01110000011 x 2^-7 + NaN = NaN
+// Skipped denorm f16_mulAdd_rz.tv line 4800000 AFBC_8020_87F2_87EE_01 -1.01110111100 x 2^-4 * -Denorm + -1.01111110010 x 2^-14 = -1.01111101110 x 2^-14
+D00C_B8F6_B3CF_0c_4CF5_1 // f16_mulAdd_rz.tv line 4850000 D00C_B8F6_B3CF_4CF5_01 -1.00000001100 x 2^5 * -1.00011110110 x 2^-1 + -1.01111001111 x 2^-3 = 1.00011110101 x 2^4
+8BEB_43FF_E800_0c_E800_1 // f16_mulAdd_rz.tv line 4900000 8BEB_43FF_E800_E800_01 -1.01111101011 x 2^-13 * 1.01111111111 x 2^1 + -1.00000000000 x 2^11 = -1.00000000000 x 2^11
+// Skipped denorm f16_mulAdd_rz.tv line 4950000 C3FE_0001_FFFE_FFFE_00 -1.01111111110 x 2^1 * Denorm + NaN = NaN
+C3FE_B1FF_A600_0c_39CD_1 // f16_mulAdd_rz.tv line 5000000 C3FE_B1FF_A600_39CD_01 -1.01111111110 x 2^1 * -1.00111111111 x 2^-3 + -1.01000000000 x 2^-6 = 1.00111001101 x 2^-1
+B004_FC44_3FFE_0c_FE44_0 // f16_mulAdd_rz.tv line 5050000 B004_FC44_3FFE_FE44_10 -1.00000000100 x 2^-3 * NaN + 1.01111111110 x 2^0 = NaN
+85FF_37FE_31FE_0c_31FD_1 // f16_mulAdd_rz.tv line 5100000 85FF_37FE_31FE_31FD_01 -1.00111111111 x 2^-14 * 1.01111111110 x 2^-2 + 1.00111111110 x 2^-3 = 1.00111111101 x 2^-3
+C401_EBFF_92C2_0c_7400_1 // f16_mulAdd_rz.tv line 5150000 C401_EBFF_92C2_7400_01 -1.00000000001 x 2^2 * -1.01111111111 x 2^11 + -1.01011000010 x 2^-11 = 1.00000000000 x 2^14
+C7FF_B408_B401_0c_3F0E_1 // f16_mulAdd_rz.tv line 5200000 C7FF_B408_B401_3F0E_01 -1.01111111111 x 2^2 * -1.00000001000 x 2^-2 + -1.00000000001 x 2^-2 = 1.01100001110 x 2^0
+43E0_C6FB_2360_0c_CEDE_1 // f16_mulAdd_rz.tv line 5250000 43E0_C6FB_2360_CEDE_01 1.01111100000 x 2^1 * -1.01011111011 x 2^2 + 1.01101100000 x 2^-7 = -1.01011011110 x 2^4
+8B87_2C17_4F43_0c_4F42_1 // f16_mulAdd_rz.tv line 5300000 8B87_2C17_4F43_4F42_01 -1.01110000111 x 2^-13 * 1.00000010111 x 2^-4 + 1.01101000011 x 2^4 = 1.01101000010 x 2^4
+// Skipped denorm f16_mulAdd_rz.tv line 5350000 830F_BFFE_0400_090E_01 -Denorm * -1.01111111110 x 2^0 + 1.00000000000 x 2^-14 = 1.00100001110 x 2^-13
+E801_7FFF_37FE_0c_7FFF_0 // f16_mulAdd_rz.tv line 5400000 E801_7FFF_37FE_7FFF_00 -1.00000000001 x 2^11 * NaN + 1.01111111110 x 2^-2 = NaN
+EBFF_483F_C7C1_0c_F83E_1 // f16_mulAdd_rz.tv line 5450000 EBFF_483F_C7C1_F83E_01 -1.01111111111 x 2^11 * 1.00000111111 x 2^3 + -1.01111000001 x 2^2 = -1.00000111110 x 2^15
+49FE_3703_7BFE_0c_7BFE_1 // f16_mulAdd_rz.tv line 5500000 49FE_3703_7BFE_7BFE_01 1.00111111110 x 2^3 * 1.01100000011 x 2^-2 + 1.01111111110 x 2^15 = 1.01111111110 x 2^15
+84BE_93FE_33DE_0c_33DE_1 // f16_mulAdd_rz.tv line 5550000 84BE_93FE_33DE_33DE_01 -1.00010111110 x 2^-14 * -1.01111111110 x 2^-11 + 1.01111011110 x 2^-3 = 1.01111011110 x 2^-3
+F800_47FF_40FE_0c_FBFF_5 // f16_mulAdd_rz.tv line 5600000 F800_47FF_40FE_FBFF_05 -1.00000000000 x 2^15 * 1.01111111111 x 2^2 + 1.00011111110 x 2^1 = -1.01111111111 x 2^15
+F801_E3FE_C401_0c_7BFF_5 // f16_mulAdd_rz.tv line 5650000 F801_E3FE_C401_7BFF_05 -1.00000000001 x 2^15 * -1.01111111110 x 2^9 + -1.00000000001 x 2^2 = 1.01111111111 x 2^15
+0E80_0810_E912_0c_E911_1 // f16_mulAdd_rz.tv line 5700000 0E80_0810_E912_E911_01 1.01010000000 x 2^-12 * 1.00000010000 x 2^-13 + -1.00100010010 x 2^11 = -1.00100010001 x 2^11
+A67F_49FF_4D3E_0c_4D2A_1 // f16_mulAdd_rz.tv line 5750000 A67F_49FF_4D3E_4D2A_01 -1.01001111111 x 2^-6 * 1.00111111111 x 2^3 + 1.00100111110 x 2^4 = 1.00100101010 x 2^4
+22DC_3BFE_3C00_0c_3C0D_1 // f16_mulAdd_rz.tv line 5800000 22DC_3BFE_3C00_3C0D_01 1.01011011100 x 2^-7 * 1.01111111110 x 2^-1 + 1.00000000000 x 2^0 = 1.00000001101 x 2^0
+FBFE_FBFF_47FE_0c_7BFF_5 // f16_mulAdd_rz.tv line 5850000 FBFE_FBFF_47FE_7BFF_05 -1.01111111110 x 2^15 * -1.01111111111 x 2^15 + 1.01111111110 x 2^2 = 1.01111111111 x 2^15
+FC00_CE07_47C3_0c_7C00_0 // f16_mulAdd_rz.tv line 5900000 FC00_CE07_47C3_7C00_00 -INF * -1.01000000111 x 2^4 + 1.01111000011 x 2^2 = INF
+343D_C5C9_93FE_0c_BE22_1 // f16_mulAdd_rz.tv line 5950000 343D_C5C9_93FE_BE22_01 1.00000111101 x 2^-2 * -1.00111001001 x 2^2 + -1.01111111110 x 2^-11 = -1.01000100010 x 2^0
+EA10_07FE_C803_0c_C833_1 // f16_mulAdd_rz.tv line 6000000 EA10_07FE_C803_C833_01 -1.01000010000 x 2^11 * 1.01111111110 x 2^-14 + -1.00000000011 x 2^3 = -1.00000110011 x 2^3
+FFFF_C3FF_EA40_0c_FFFF_0 // f16_mulAdd_rz.tv line 6050000 FFFF_C3FF_EA40_FFFF_00 NaN * -1.01111111111 x 2^1 + -1.01001000000 x 2^11 = NaN
+// Skipped denorm f16_mulAdd_rz.tv line 6100000 FFFE_80F8_0001_FFFE_00 NaN * -Denorm + Denorm = NaN
diff --git a/pipelined/src/fpu/fcvtfp.sv b/pipelined/src/fpu/fcvtfp.sv
index e93822ee..fb8e1ad9 100644
--- a/pipelined/src/fpu/fcvtfp.sv
+++ b/pipelined/src/fpu/fcvtfp.sv
@@ -30,11 +30,17 @@ module cvtfp (
     logic [31:0] DSRes; // double to single precision result
 
 
+    // add support for all formats
+    // consider reordering code blocks so upconverting is in one region of the file
+    // and downconverting is in the other region.
 
     ///////////////////////////////////////////////////////////////////////////////
-    // LZC
+    // LZC: Leading Zero Counter
     ///////////////////////////////////////////////////////////////////////////////
 
+    // *** consider sharing this with fcvtint
+    // *** emphasize parallel structure between the two
+    // *** add a priorityencoder module to generic (similar to priorityonehot) and use it
 
     // LZC - find the first 1 in the input's mantissa
 	logic [8:0]	i,NormCnt;
diff --git a/pipelined/src/fpu/fcvtint.sv b/pipelined/src/fpu/fcvtint.sv
index d394d7c3..6a668699 100644
--- a/pipelined/src/fpu/fcvtint.sv
+++ b/pipelined/src/fpu/fcvtint.sv
@@ -61,6 +61,10 @@ module fcvt (
       //  fcvt.d.l  = 100
       //  fcvt.d.lu = 110
       //  {long, unsigned, to int}
+
+    // *** revisit this module, explain in more depth
+    // should the int to fp and fp to int paths be separated?
+    // add support for all formats
    
     // calculate signals based off the input and output's size
     assign Res64 = (FOpCtrlE[0]&FOpCtrlE[2]) | (FmtE&~FOpCtrlE[0]);
diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv
index 50100c3c..c5184c57 100644
--- a/pipelined/src/ieu/alu.sv
+++ b/pipelined/src/ieu/alu.sv
@@ -40,9 +40,9 @@ module alu #(parameter WIDTH=32) (
   logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
   logic        Carry, Neg;
   logic        LT, LTU;
-  logic        Overflow;
   logic        W64, SubArith, ALUOp;
   logic [2:0]  ALUFunct;
+  logic        Asign, Bsign;
 
   // Extract control signals
   // W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
@@ -57,12 +57,13 @@ module alu #(parameter WIDTH=32) (
   // Shifts
   shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
 
-  // condition code flags based on subtract output
+  // condition code flags based on subtract output Sum = A-B
   // Overflow occurs when the numbers being subtracted have the opposite sign 
   // and the result has the opposite sign of A
-  assign Overflow = (A[WIDTH-1] ^ B[WIDTH-1]) & (A[WIDTH-1] ^ Sum[WIDTH-1]);
   assign Neg  = Sum[WIDTH-1];
-  assign LT = Neg ^ Overflow;
+  assign Asign = A[WIDTH-1];
+  assign Bsign = B[WIDTH-1];
+  assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
   assign LTU = ~Carry;
  
   // SLT
diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv
index f1a66861..26ea6d86 100644
--- a/pipelined/src/ieu/comparator.sv
+++ b/pipelined/src/ieu/comparator.sv
@@ -36,9 +36,8 @@ module comparator #(parameter WIDTH=32) (
 
   logic [WIDTH-1:0] bbar, diff;
   logic             carry, eq, neg, overflow, lt, ltu;
-
-  // NOTE: This can be replaced by some faster logic optimized
-  // to just compute flags and not the difference.
+/*
+  // Subtractor implementation
 
   // subtraction
   assign bbar = ~b;
@@ -53,5 +52,35 @@ module comparator #(parameter WIDTH=32) (
   assign lt = neg ^ overflow;
   assign ltu = ~carry;
   assign flags = {eq, lt, ltu};
+*/
+
+  /* verilator lint_off UNOPTFLAT */
+  // prefix implementation
+  localparam levels=$clog2(WIDTH);
+  genvar i;
+  genvar level;
+  logic [WIDTH-1:0] e[levels:0];
+  logic [WIDTH-1:0] l[levels:0];
+  logic eq2, lt2, ltu2;
+
+  // Bitwise logic
+  assign e[0] = a ~^ b; // bitwise equality
+  assign l[0] = ~a & b; // bitwise less than unsigned: A=0 and B=1
+
+  // Recursion
+  for (level = 1; level<=levels; level++) begin
+    for (i=0; i<WIDTH/(2**level); i++) begin
+      assign e[level][i] = e[level-1][i*2+1] & e[level-1][i*2];  // group equal if both parts equal
+      assign l[level][i] = l[level-1][i*2+1] | e[level-1][i*2+1] & l[level-1][i*2]; // group less if upper is les or upper equal and lower less
+    end
+  end
+
+  // Output logic
+  assign eq2 = e[levels][0];  // A = B if all bits are equal
+  assign ltu2 = l[levels][0]; // A < B if group is less (unsigned)
+  // A < B signed if less than unsigned and msb is not < unsigned, or if A negative and B positive
+  assign lt2 = ltu2 & ~l[0][WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1]; 
+  assign flags = {eq2, lt2, ltu2};
+  /* verilator lint_on UNOPTFLAT */
 endmodule
 
diff --git a/pipelined/src/ifu/gsharePredictor.sv b/pipelined/src/ifu/gsharePredictor.sv
index 63c071bc..f175361d 100644
--- a/pipelined/src/ifu/gsharePredictor.sv
+++ b/pipelined/src/ifu/gsharePredictor.sv
@@ -31,10 +31,7 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "wally-config.vh"
-
 module gsharePredictor
-  #(parameter int k = 10
-    )
   (input logic             clk,
    input logic             reset,
    input logic             StallF, StallE,
@@ -52,8 +49,8 @@ module gsharePredictor
    input logic [1:0]       UpdateBPPredE
   
    );
-  logic [k+1:0]            GHR, GHRNext;
-  logic [k-1:0]            PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
+  logic [`BPRED_SIZE+1:0]  GHR, GHRNext;
+  logic [`BPRED_SIZE-1:0]  PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
   logic                    PHTUpdateEN;
   logic                    BPClassWrongNonCFI;
   logic                    BPClassWrongCFI;
@@ -63,7 +60,7 @@ module gsharePredictor
 
   logic [6:0]              GHRMuxSel;
   logic                    GHRUpdateEN;
-  logic [k-1:0]            GHRLookup;
+  logic [`BPRED_SIZE-1:0]            GHRLookup;
 
   assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
   assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
@@ -85,18 +82,18 @@ module gsharePredictor
   // hoping this created a AND-OR mux.
   always_comb begin
     case (GHRMuxSel) 
-      7'b000_0001: GHRNext = GHR[k-1+2:0];  // no change
-      7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update
-      7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1
-      7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction
-      7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2
-      7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1
-      7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update
-      default: GHRNext = GHR[k-1+2:0];
+      7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0];  // no change
+      7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
+      7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
+      7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
+      7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
+      7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
+      7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], BPPredF[1]}; // speculative update
+      default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
     endcase
   end
 
-  flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
+  flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
            .reset(reset),
            .en((GHRUpdateEN)),
            .d(GHRNext),
@@ -105,21 +102,21 @@ module gsharePredictor
   // if actively updating the GHR at the time of prediction we want to us
   // GHRNext as the lookup rather than GHR.
 
-  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0];
-  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1];  
+  assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
+  assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];  
   assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
   assign PHTUpdateEN = InstrClassE[0] & ~StallE;
 
-  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0];
+  assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
   
   // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT 
-  SRAM2P1R1W #(k, 2) PHT(.clk(clk),
+  SRAM2P1R1W #(`BPRED_SIZE, 2) PHT(.clk(clk),
     .reset(reset),
-    //.RA1(GHR[k-1:0]),
-    .RA1(GHRLookup ^ PCNextF[k:1]),
+    //.RA1(GHR[`BPRED_SIZE-1:0]),
+    .RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
     .RD1(BPPredF),
     .REN1(~StallF),
-    .WA1(PHTUpdateAdr ^ PCE[k:1]),
+    .WA1(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
     .WD1(UpdateBPPredE),
     .WEN1(PHTUpdateEN),
     .BitWEN1(2'b11));
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index d5e2e88b..5b42b411 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -140,7 +140,7 @@ module ifu (
   // WFI
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  assign wfiD = (InstrD[6:0] == 7'b111011 && InstrD[31:20] == 12'b000100000101); // WFI in decode stage
+  assign wfiD = (InstrD[6:0] == 7'b1110011 && InstrD[31:20] == 12'b000100000101); // WFI in decode stage
   assign InstrNextF = wfiD ? InstrD : PostSpillInstrRawF; // on WFI, keep replaying WFI
 
   ////////////////////////////////////////////////////////////////////////////////////////////////
diff --git a/pipelined/src/lsu/atomic.sv b/pipelined/src/lsu/atomic.sv
index d2054a78..a5dd06ac 100644
--- a/pipelined/src/lsu/atomic.sv
+++ b/pipelined/src/lsu/atomic.sv
@@ -41,7 +41,7 @@ module atomic (
   input logic [1:0]          LSUAtomicM,
   input logic [1:0]          PreLSURWM,
   input logic                IgnoreRequest,
-  output logic [`XLEN-1:0]   FinalAMOWriteDataM,
+  output logic [`XLEN-1:0]   AMOWriteDataM,
   output logic               SquashSCW,
   output logic [1:0]         LSURWM);
 
@@ -50,7 +50,7 @@ module atomic (
 
   amoalu amoalu(.srca(ReadDataM), .srcb(LSUWriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]), 
                 .result(AMOResult));
-  mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
+  mux2 #(`XLEN) wdmux(LSUWriteDataM, AMOResult, LSUAtomicM[1], AMOWriteDataM);
   assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
   lrsc lrsc(.clk, .reset, .FlushW, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
     .SquashSCW, .LSURWM);
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 1e732516..81e5fcbc 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -145,6 +145,7 @@ module lsu (
   assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
 
   // MMU and Misalignment fault logic required if privileged unit exists
+  // *** DH: This is too strong a requirement.  Separate MMU in `VIRTMEM_SUPPORTED from simpler faults in `ZICSR_SUPPORTED
   if(`ZICSR_SUPPORTED == 1) begin : dmmu
     logic DisableTranslation;
     assign DisableTranslation = SelHPTW | FlushDCacheM;
@@ -181,7 +182,7 @@ module lsu (
   //  Memory System
   //  Either Data Cache or Data Tightly Integrated Memory or just bus interface
   /////////////////////////////////////////////////////////////////////////////////////////////
-  logic [`XLEN-1:0]    FinalAMOWriteDataM, FinalWriteDataM;
+  logic [`XLEN-1:0]    AMOWriteDataM, FinalWriteDataM;
   logic [`XLEN-1:0]    ReadDataWordM;
   logic [`XLEN-1:0]    ReadDataWordMuxM;
   logic                IgnoreRequest;
@@ -255,13 +256,13 @@ module lsu (
   if (`A_SUPPORTED) begin:atomic
     atomic atomic(.clk, .reset, .FlushW, .StallW, .ReadDataM, .LSUWriteDataM, .LSUPAdrM, 
       .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, 
-      .FinalAMOWriteDataM, .SquashSCW, .LSURWM);
+      .AMOWriteDataM, .SquashSCW, .LSURWM);
   end else begin:lrsc
-    assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign FinalAMOWriteDataM = LSUWriteDataM;
+    assign SquashSCW = 0; assign LSURWM = PreLSURWM; assign AMOWriteDataM = LSUWriteDataM;
   end
 
   subwordwrite subwordwrite(.LSUPAdrM(LSUPAdrM[2:0]),
-    .LSUFunct3M, .FinalAMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
+    .LSUFunct3M, .AMOWriteDataM, .FinalWriteDataM, .ByteMaskM);
 
   
 endmodule
diff --git a/pipelined/src/lsu/subwordwrite.sv b/pipelined/src/lsu/subwordwrite.sv
index ce850ab7..7f2a6b8d 100644
--- a/pipelined/src/lsu/subwordwrite.sv
+++ b/pipelined/src/lsu/subwordwrite.sv
@@ -33,55 +33,30 @@
 module subwordwrite (
   input logic [2:0]          LSUPAdrM,
   input logic [2:0]          LSUFunct3M,
-  input logic [`XLEN-1:0]    FinalAMOWriteDataM,
+  input logic [`XLEN-1:0]    AMOWriteDataM,
   output logic [`XLEN-1:0]   FinalWriteDataM,
   output logic [`XLEN/8-1:0] ByteMaskM
-                     );
-                  
-  logic [`XLEN-1:0]          WriteDataSubwordDuplicated;
+);
 
-  swbytemask swbytemask(.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HADDRD(LSUPAdrM),
-    .ByteMask(ByteMaskM));
+  // Compute byte masks
+  swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
   
+  // Replicate data for subword writes
   if (`XLEN == 64) begin:sww
-    // Handle subword writes
     always_comb 
       case(LSUFunct3M[1:0])
-        2'b00:  WriteDataSubwordDuplicated = {8{FinalAMOWriteDataM[7:0]}};  // sb
-        2'b01:  WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[15:0]}}; // sh
-        2'b10:  WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[31:0]}}; // sw
-        2'b11:  WriteDataSubwordDuplicated = FinalAMOWriteDataM;            // sw
+        2'b00:  FinalWriteDataM = {8{AMOWriteDataM[7:0]}};  // sb
+        2'b01:  FinalWriteDataM = {4{AMOWriteDataM[15:0]}}; // sh
+        2'b10:  FinalWriteDataM = {2{AMOWriteDataM[31:0]}}; // sw
+        2'b11:  FinalWriteDataM = AMOWriteDataM;            // sw
       endcase
-
-    always_comb begin
-      FinalWriteDataM='0;
-      if (ByteMaskM[0]) FinalWriteDataM[7:0]   = WriteDataSubwordDuplicated[7:0];
-      if (ByteMaskM[1]) FinalWriteDataM[15:8]  = WriteDataSubwordDuplicated[15:8];
-      if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16];
-      if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24];
-      if (ByteMaskM[4]) FinalWriteDataM[39:32] = WriteDataSubwordDuplicated[39:32];
-      if (ByteMaskM[5]) FinalWriteDataM[47:40] = WriteDataSubwordDuplicated[47:40];
-      if (ByteMaskM[6]) FinalWriteDataM[55:48] = WriteDataSubwordDuplicated[55:48];
-      if (ByteMaskM[7]) FinalWriteDataM[63:56] = WriteDataSubwordDuplicated[63:56];
-    end 
-
   end else begin:sww // 32-bit
-    // Handle subword writes
     always_comb 
       case(LSUFunct3M[1:0])
-        2'b00:  WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[7:0]}};  // sb
-        2'b01:  WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[15:0]}}; // sh
-        2'b10:  WriteDataSubwordDuplicated = FinalAMOWriteDataM;            // sw
-        default: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // shouldn't happen
+        2'b00:  FinalWriteDataM = {4{AMOWriteDataM[7:0]}};  // sb
+        2'b01:  FinalWriteDataM = {2{AMOWriteDataM[15:0]}}; // sh
+        2'b10:  FinalWriteDataM = AMOWriteDataM;            // sw
+        default: FinalWriteDataM = AMOWriteDataM; // shouldn't happen
       endcase
-
-    always_comb begin
-      FinalWriteDataM='0;
-      if (ByteMaskM[0]) FinalWriteDataM[7:0]   = WriteDataSubwordDuplicated[7:0];
-      if (ByteMaskM[1]) FinalWriteDataM[15:8]  = WriteDataSubwordDuplicated[15:8];
-      if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16];
-      if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24];
-    end 
-
   end
 endmodule
diff --git a/pipelined/src/lsu/swbytemask.sv b/pipelined/src/lsu/swbytemask.sv
index d3ff2d57..7f89e628 100644
--- a/pipelined/src/lsu/swbytemask.sv
+++ b/pipelined/src/lsu/swbytemask.sv
@@ -31,32 +31,32 @@
 `include "wally-config.vh"
 
 module swbytemask (
-  input logic [3:0]          HSIZED,
-  input logic [2:0]         HADDRD,
+  input logic [1:0]         Size,
+  input logic [2:0]         Adr,
   output logic [`XLEN/8-1:0] ByteMask);
   
 
   if(`XLEN == 64) begin
     always_comb begin
-      case(HSIZED[1:0])
-        2'b00: begin ByteMask = 8'b00000000; ByteMask[HADDRD[2:0]] = 1; end // sb
-        2'b01: case (HADDRD[2:1])
+      case(Size[1:0])
+        2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
+        2'b01: case (Adr[2:1])
                   2'b00: ByteMask = 8'b0000_0011;
                   2'b01: ByteMask = 8'b0000_1100;
                   2'b10: ByteMask = 8'b0011_0000;
                   2'b11: ByteMask = 8'b1100_0000;
                 endcase
-        2'b10: if (HADDRD[2]) ByteMask = 8'b11110000;
-               else           ByteMask = 8'b00001111;
+        2'b10: if (Adr[2]) ByteMask = 8'b11110000;
+               else        ByteMask = 8'b00001111;
         2'b11: ByteMask = 8'b1111_1111;
       endcase
     end
   end else begin
     always_comb begin
-      case(HSIZED[1:0])
-        2'b00: begin ByteMask = 4'b0000; ByteMask[HADDRD[1:0]] = 1; end // sb
-        2'b01: if (HADDRD[1]) ByteMask = 4'b1100;
-               else           ByteMask = 4'b0011;
+      case(Size[1:0])
+        2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
+        2'b01: if (Adr[1]) ByteMask = 4'b1100;
+               else        ByteMask = 4'b0011;
         2'b10: ByteMask = 4'b1111;
         default: ByteMask =  4'b1111;
       endcase
diff --git a/pipelined/src/privileged/csrc.sv b/pipelined/src/privileged/csrc.sv
index c48e3d2e..9d141798 100644
--- a/pipelined/src/privileged/csrc.sv
+++ b/pipelined/src/privileged/csrc.sv
@@ -64,12 +64,8 @@ module csrc #(parameter
   );
 
   if (`ZICOUNTERS_SUPPORTED) begin:counters
-    (* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
-    logic [63:0] CYCLEPlusM, INSTRETPlusM;
-    logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
-    logic        WriteCYCLEM, WriteINSTRETM;
     logic [4:0]  CounterNumM;
-    logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
+    (* mark_debug = "true" *)     logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
     logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
     logic 			       InstrValidNotFlushedM;
     logic LoadStallE, LoadStallM;
diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv
index 25e929a2..1f7ae6b1 100644
--- a/pipelined/src/privileged/privdec.sv
+++ b/pipelined/src/privileged/privdec.sv
@@ -33,7 +33,8 @@
 
 module privdec (
   input  logic [31:20] InstrM,
-  input  logic         PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, TrappedSRETM,
+  input  logic         PrivilegedM, IllegalIEUInstrFaultM, IllegalCSRAccessM, IllegalFPUInstrM, 
+  input  logic         TrappedSRETM, WFITimeoutM,
   input  logic [1:0]   PrivilegeModeW, 
   input  logic         STATUS_TSR,
   output logic         IllegalInstrFaultM,
@@ -51,7 +52,6 @@ module privdec (
   assign wfiM =       PrivilegedM & (InstrM[31:20] == 12'b000100000101);
   assign sfencevmaM = PrivilegedM & (InstrM[31:25] ==  7'b0001001); // *** & (PrivilegedModeW == `M_MODE | ~STATUS_TVM); // *** does this work in U mode?
   assign IllegalPrivilegedInstrM = PrivilegedM & ~(sretM|mretM|ecallM|ebreakM|wfiM|sfencevmaM);
-  assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | TrappedSRETM; // *** generalize this for other instructions
-
-  // *** initially, wfi is nop
+  assign IllegalInstrFaultM = (IllegalIEUInstrFaultM & IllegalFPUInstrM) | IllegalPrivilegedInstrM | IllegalCSRAccessM | 
+                               TrappedSRETM | WFITimeoutM; // *** generalize this for other instructions
 endmodule
diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv
index 003a84b7..b429a14c 100644
--- a/pipelined/src/privileged/privileged.sv
+++ b/pipelined/src/privileged/privileged.sv
@@ -104,6 +104,7 @@ module privileged (
   logic [11:0] MIP_REGW, MIE_REGW, SIP_REGW, SIE_REGW;
   logic md;
   logic       StallMQ;
+  logic WFITimeoutM; 
 
 
   ///////////////////////////////////////////
@@ -114,24 +115,6 @@ module privileged (
   assign md = CauseM[`XLEN-1] ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM[`LOG_XLEN-1:0]];
   
   // PrivilegeMode FSM
-/* -----\/----- EXCLUDED -----\/-----
-  always_comb begin
-    TrappedSRETM = 0;
-    if (mretM)      NextPrivilegeModeM = STATUS_MPP;
-    else if (sretM) 
-      if (STATUS_TSR & PrivilegeModeW == `S_MODE) begin
-        TrappedSRETM = 1;
-                    NextPrivilegeModeM = PrivilegeModeW;
-      end else      NextPrivilegeModeM = {1'b0, STATUS_SPP};
-    else if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
-      if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
-                    NextPrivilegeModeM = `S_MODE;
-      else          NextPrivilegeModeM = `M_MODE;
-    end else        NextPrivilegeModeM = PrivilegeModeW;
-  end
-
- -----/\----- EXCLUDED -----/\----- */
-  
   always_comb begin
     if (TrapM) begin // Change privilege based on DELEG registers (see 3.1.8)
       if (`S_SUPPORTED & md & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE))
@@ -149,14 +132,22 @@ module privileged (
 
   flopenl #(2) privmodereg(clk, reset, ~StallW, NextPrivilegeModeM, `M_MODE, PrivilegeModeW);
 
-  // *** WFI could be implemented here and depends on TW
+  ///////////////////////////////////////////
+  // WFI timeout Privileged Spec 3.1.6.5
+  ///////////////////////////////////////////
+  if (`U_SUPPORTED) begin
+    logic [`WFI_TIMEOUT_BIT:0] WFICount, WFICountPlus1;
+    assign WFICountPlus1 = WFICount + 1;
+    floprc #(`WFI_TIMEOUT_BIT+1) wficountreg(clk, reset, ~wfiM, WFICountPlus1, WFICount);  // count while in WFI
+    assign WFITimeoutM = STATUS_TW & PrivilegeModeW != `M_MODE & WFICount[`WFI_TIMEOUT_BIT]; 
+  end else assign WFITimeoutM = 0;
 
   ///////////////////////////////////////////
   // decode privileged instructions
   ///////////////////////////////////////////
 
    privdec pmd(.InstrM(InstrM[31:20]), 
-              .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM,
+              .PrivilegedM, .IllegalIEUInstrFaultM, .IllegalCSRAccessM, .IllegalFPUInstrM, .TrappedSRETM, .WFITimeoutM,
               .PrivilegeModeW, .STATUS_TSR, .IllegalInstrFaultM, 
               .sretM, .mretM, .ecallM, .ebreakM, .wfiM, .sfencevmaM);
 
@@ -233,7 +224,7 @@ module privileged (
             .PCM,
             .InstrMisalignedAdrM, .IEUAdrM, 
             .InstrM,
-            .InstrValidM, .CommittedM, .DivE,
+            .InstrValidM, .CommittedM, .DivE, 
             .TrapM, .MTrapM, .STrapM, .UTrapM, .RetM,
             .InterruptM,
             .ExceptionM,
diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv
index a2cc6ef3..1cc21579 100644
--- a/pipelined/src/privileged/trap.sv
+++ b/pipelined/src/privileged/trap.sv
@@ -46,7 +46,7 @@ module trap (
   input logic [`XLEN-1:0]  PCM,
   input logic [`XLEN-1:0]  InstrMisalignedAdrM, IEUAdrM, 
   input logic [31:0] 	   InstrM,
-  input logic 		   InstrValidM, CommittedM, DivE,
+  input logic 		   InstrValidM, CommittedM, DivE, 
   output logic 		   TrapM, MTrapM, STrapM, UTrapM, RetM,
   output logic 		   InterruptM,
   output logic 		   ExceptionM,
diff --git a/pipelined/src/uncore/clint.sv b/pipelined/src/uncore/clint.sv
index c2d9f0f5..b0b275a3 100644
--- a/pipelined/src/uncore/clint.sv
+++ b/pipelined/src/uncore/clint.sv
@@ -66,8 +66,7 @@ module clint (
   if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000};
   else           assign #2 entry = {HADDR[15:2], 2'b00}; 
   
-  swbytemask swbytemask(.HSIZED, .HADDRD(entryd[2:0]), .ByteMask(ByteMaskM));
-
+  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(entryd[2:0]), .ByteMask(ByteMaskM));
 
   // DH 2/20/21: Eventually allow MTIME to run off a separate clock
   // This will require synchronizing MTIME to the system clock
diff --git a/pipelined/src/uncore/gpio.sv b/pipelined/src/uncore/gpio.sv
index acd17247..ad82e62a 100644
--- a/pipelined/src/uncore/gpio.sv
+++ b/pipelined/src/uncore/gpio.sv
@@ -146,7 +146,7 @@ module gpio (
 
   // chip i/o
   // connect OUT to IN for loopback testing
-  if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & input_en & output_en;
+  if (`GPIO_LOOPBACK_TEST) assign input0d = GPIOPinsOut & output_en | (GPIOPinsIn  & input_en);
   else                     assign input0d = GPIOPinsIn  & input_en;
   flop #(32) sync1(HCLK,input0d,input1d);
   flop #(32) sync2(HCLK,input1d,input2d);
diff --git a/pipelined/src/uncore/ram.sv b/pipelined/src/uncore/ram.sv
index 82d56a96..442bfc50 100644
--- a/pipelined/src/uncore/ram.sv
+++ b/pipelined/src/uncore/ram.sv
@@ -56,7 +56,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
   logic				  memwrite;
   logic [3:0] 		  busycount;
   
-  swbytemask swbytemask(.HSIZED, .HADDRD(HWADDR[2:0]), .ByteMask(ByteMaskM));
+  swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HWADDR[2:0]), .ByteMask(ByteMaskM));
 
   assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
 
diff --git a/pipelined/src/uncore/uartPC16550D.sv b/pipelined/src/uncore/uartPC16550D.sv
index a6e2dd71..af656405 100644
--- a/pipelined/src/uncore/uartPC16550D.sv
+++ b/pipelined/src/uncore/uartPC16550D.sv
@@ -54,14 +54,22 @@ module uartPC16550D(
 	output logic 	   SOUT, RTSb, DTRb, OUT1b, OUT2b
 	);
 
+  // signal to watch
+  // rxparityerr, RXBR[upper 3 bits]
+  // LSR bits 1 to 4 are based on parity, overrun, and framing errors
+  // txstate, rxstate
+  // loop, fifoenabled
+  // IER, RCR, MCR, LSR, MSR, DLL, DLM, RBR
+  
+
   // transmit and receive states // *** neeed to work on synth warning -- it wants to make enums 32 bits by default
   typedef enum logic [1:0] {UART_IDLE, UART_ACTIVE, UART_DONE, UART_BREAK} statetype;
 
   // Registers
-  logic [10:0] RBR;
-  logic [7:0]  FCR, LCR, LSR, SCR, DLL, DLM;
-  logic [3:0]  IER, MSR;
-  logic [4:0]  MCR;
+   (* mark_debug = "true" *)  logic [10:0] RBR;
+   (* mark_debug = "true" *)  logic [7:0]  FCR, LCR, LSR, SCR, DLL, DLM;
+   (* mark_debug = "true" *)  logic [3:0]  IER, MSR;
+   (* mark_debug = "true" *)  logic [4:0]  MCR;
 
   // Syncrhonized and delayed UART signals
   logic 	   SINd, DSRbd, DCDbd, CTSbd, RIbd;
@@ -78,7 +86,7 @@ module uartPC16550D(
   logic [16+`UART_PRESCALE-1:0] baudcount;
   logic [3:0] 					rxoversampledcnt, txoversampledcnt; // count oversampled-by-16
   logic [3:0] 					rxbitsreceived, txbitssent;
-  statetype rxstate, txstate;
+   (* mark_debug = "true" *)  statetype rxstate, txstate;
 
   // shift registrs and FIFOs
   logic [9:0] 					rxshiftreg;
@@ -90,11 +98,11 @@ module uartPC16550D(
   logic [3:0] 					rxbitsexpected, txbitsexpected;
 
   // receive data
-  logic [10:0] 					RXBR;
+   (* mark_debug = "true" *)  logic [10:0] 					RXBR;
   logic [6:0] 					rxtimeoutcnt;
   logic 						rxcentered;
   logic 						rxparity, rxparitybit, rxstopbit;
-  logic 						rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
+   (* mark_debug = "true" *)  logic 						rxparityerr, rxoverrunerr, rxframingerr, rxbreak, rxfifohaserr;
   logic 						rxdataready;
   logic 						rxfifoempty, rxfifotriggered, rxfifotimeout;
   logic 						rxfifodmaready;
@@ -145,7 +153,8 @@ module uartPC16550D(
       if (`FPGA) begin
 		//DLL <= #1 8'd38; // 35Mhz
 		//DLL <= #1 8'd11; // 10 Mhz
-		DLL <= #1 8'd33; // 30 Mhz
+		//DLL <= #1 8'd33; // 30 Mhz
+		DLL <= #1 8'd8; // 30 Mhz 230400
 		DLM <= #1 8'b0;
       end else begin
 		DLL <= #1 8'd1; // this cannot be zero with DLM also zer0.
@@ -162,10 +171,13 @@ module uartPC16550D(
            3'b001: if (DLAB) DLM <= #1 Din; else IER <= #1 Din[3:0];
 		   -----/\----- EXCLUDED -----/\----- */
 		  // *** BUG FIX ME for now for the divider to be 38.  Our clock is 35 Mhz.  35Mhz /(38 * 16) ~= 57600 baud, which is close enough to 57600 baud
+		  // dll = freq / (baud * 16)
+		  // 30Mhz / (57600 * 16) = 32.5
+		  // 30Mhz / (230400 * 16) = 8.13
 		  // freq /baud / 16 = div
           //3'b000: if (DLAB) DLL <= #1 8'd38; //else TXHR <= #1 Din; // TX handled in TX register/FIFO section
 		  //3'b000: if (DLAB) DLL <= #1 8'd11; //else TXHR <= #1 Din; // TX handled in
-		  3'b000: if (DLAB) DLL <= #1 8'd33; //else TXHR <= #1 Din; // TX handled in 		  
+		  3'b000: if (DLAB) DLL <= #1 8'd8; //else TXHR <= #1 Din; // TX handled in 		  
           3'b001: if (DLAB) DLM <= #1 8'b0; else IER <= #1 Din[3:0];
 
           3'b010: FCR <= #1 {Din[7:6], 2'b0, Din[3], 2'b0, Din[0]}; // Write only FIFO Control Register; 4:5 reserved and 2:1 self-clearing
diff --git a/pipelined/testbench/testbench-linux.sv b/pipelined/testbench/testbench-linux.sv
index 6f0cdf37..82455512 100644
--- a/pipelined/testbench/testbench-linux.sv
+++ b/pipelined/testbench/testbench-linux.sv
@@ -662,7 +662,7 @@ module testbench;
         `checkEQ("PCW",PCW,ExpectedPCW)
         //`checkEQ("InstrW",InstrW,ExpectedInstrW) <-- not viable because of
         // compressed to uncompressed conversion
-        `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.INSTRET_REGW,InstrCountW)
+        `checkEQ("Instr Count",dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2],InstrCountW)
         #2; // delay 2 ns.
         if(`DEBUG_TRACE >= 5) begin
           $display("%tns, %d instrs: Reg Write Address %02d ? expected value: %02d", $time, AttemptedInstructionCount, dut.core.ieu.dp.regf.a3, ExpectedRegAdrW);
diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv
index 2b8e6df8..bf4903e5 100644
--- a/pipelined/testbench/testbench.sv
+++ b/pipelined/testbench/testbench.sv
@@ -361,8 +361,8 @@ module riscvassertions;
 //    assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM");
     assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
     assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
-    assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
-    assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");    
+    //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS.");
+    //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS.");    
   end
 endmodule
 
diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh
index 90d41f55..277c4d6c 100644
--- a/pipelined/testbench/tests.vh
+++ b/pipelined/testbench/tests.vh
@@ -1467,11 +1467,17 @@ string imperas32f[] = '{
     "rv64i_m/privilege/WALLY-MTVEC", "002090",
     "rv64i_m/privilege/WALLY-MVENDORID", "004090", */
     "rv64i_m/privilege/WALLY-PMA", "0050a0",
-    "rv64i_m/privilege/WALLY-PMP", "0050a0"
+    "rv64i_m/privilege/WALLY-PMP", "0050a0",
 //    "rv64i_m/privilege/WALLY-SCAUSE", "002090",
 //    "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
 //    "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
-//    "rv64i_m/privilege/WALLY-trap-01", "0050a0"
+    "rv64i_m/privilege/WALLY-trap-01", "0050a0",
+    "rv64i_m/privilege/WALLY-MIE-01", "0050a0",
+    "rv64i_m/privilege/WALLY-mtvec-01", "0050a0",
+    "rv64i_m/privilege/WALLY-stvec-01", "0050a0",
+    "rv64i_m/privilege/WALLY-PIE-stack-01", "0050a0",
+    "rv64i_m/privilege/WALLY-PIE-stack-s-01", "0050a0",
+    "rv64i_m/privilege/WALLY-trap-sret-01", "0050a0"
 //    "rv64i_m/privilege/WALLY-STVEC", "002090",
 //    "rv64i_m/privilege/WALLY-UCAUSE", "002090",
 
diff --git a/synthDC/Makefile b/synthDC/Makefile
index b1452f0e..4aff4482 100755
--- a/synthDC/Makefile
+++ b/synthDC/Makefile
@@ -24,9 +24,11 @@ export SAIFPOWER ?= 0
 CONFIGDIR ?= ${WALLY}/pipelined/config
 CONFIGFILES	?= $(shell find $(CONFIGDIR) -name rv*_*)
 CONFIGFILESTRIM = $(notdir $(CONFIGFILES))
+FREQS = 25 50 100 150 200 250 300 350 400
+k = 3 6 
 print:
+	echo $(k)
 	echo $(CONFIGFILESTRIM)
-	echo $(DIRS)
 
 default:
 	@echo "Basic synthesis procedure for Wally:"
@@ -39,24 +41,25 @@ rv%.log: rv%
 	echo $<
 
 
-DIRS = rv32e #rv32gc rv64ic rv64gc rv32ic
+DIRS = rv32e rv32gc rv64ic rv32ic rv64gc
 # DELDIRS = rv32e rv32gc rv64ic rv64gc rv32ic
 # CONFIGSUBDIRS = _FPUoff _noMulDiv _noVirtMem _PMP0 _PMP16 _orig
-
+bpred:
+	@$(foreach kval, $(k), rm -rf $(CONFIGDIR)/rv64gc_bpred_$(kval);)
+	@$(foreach kval, $(k), cp -r $(CONFIGDIR)/rv64gc $(CONFIGDIR)/rv64gc_bpred_$(kval);)
+	@$(foreach kval, $(k), sed -i 's/BPRED_SIZE.*/BPRED_SIZE $(kval)/g' $(CONFIGDIR)/rv64gc_bpred_$(kval)/wally-config.vh;)
+	@$(foreach kval, $(k), make synth DESIGN=wallypipelinedcore CONFIG=rv64gc_bpred_$(kval) TECH=sky90 FREQ=500 MAXCORES=4 --jobs;)
 copy: 
 	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
 	@$(foreach dir, $(DIRS), cp -r $(CONFIGDIR)/$(dir) $(CONFIGDIR)/$(dir)_orig;)
 	@$(foreach dir, $(DIRS), sed -i 's/WAYSIZEINBYTES.*/WAYSIZEINBYTES 512/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
 	@$(foreach dir, $(DIRS), sed -i 's/NUMWAYS.*/NUMWAYS 1/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
 	@$(foreach dir, $(DIRS), sed -i "s/RAM_RANGE.*/RAM_RANGE	 34\'h01FF/g" $(CONFIGDIR)/$(dir)_orig/wally-config.vh ;)
+	@$(foreach dir, $(DIRS), sed -i 's/BPRED_SIZE.*/BPRED_SIZE 5/g' $(CONFIGDIR)/$(dir)_orig/wally-config.vh;)
+
 
 del:
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_orig;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_FPUoff;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP16;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_PMP0;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noVirtMem;)
-	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_noMulDiv;)
+	@$(foreach dir, $(DIRS), rm -rf $(CONFIGDIR)/$(dir)_*;)
 
 configs: $(DIRS)
 $(DIRS): 
@@ -76,23 +79,25 @@ $(DIRS):
 	cp -r $(CONFIGDIR)/$@_FPUoff $(CONFIGDIR)/$@_PMP0
 	sed -i 's/PMP_ENTRIES \(64\|16\|0\)/PMP_ENTRIES 0/' $(CONFIGDIR)/$@_PMP0/wally-config.vh
 	
-	# No Virtual Memory 
-	rm -rf $(CONFIGDIR)/$@_noVirtMem
-	cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noVirtMem
-	sed -i 's/VIRTMEM_SUPPORTED 1/VIRTMEM_SUPPORTED 0/' $(CONFIGDIR)/$@_noVirtMem/wally-config.vh
-
 	#no muldiv
 	rm -rf $(CONFIGDIR)/$@_noMulDiv
-	cp -r $(CONFIGDIR)/$@_noVirtMem $(CONFIGDIR)/$@_noMulDiv
+	cp -r $(CONFIGDIR)/$@_PMP0 $(CONFIGDIR)/$@_noMulDiv
 	sed -i 's/1 *<< *12/0 << 12/' $(CONFIGDIR)/$@_noMulDiv/wally-config.vh
 
+	#no priv
+	rm -rf $(CONFIGDIR)/$@_noPriv
+	cp -r $(CONFIGDIR)/$@_noMulDiv $(CONFIGDIR)/$@_noPriv
+	sed -i 's/ZICSR_SUPPORTED *1/ZICSR_SUPPORTED 0/' $(CONFIGDIR)/$@_noPriv/wally-config.vh
+
+freqs: 
+	@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e TECH=sky130 FREQ=$(freq) MAXCORES=1;)
 
 allsynth: $(CONFIGFILESTRIM)
 
 $(CONFIGFILESTRIM):
-	make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky90 FREQ=500 MAXCORES=1
+	make synth DESIGN=wallypipelinedcore CONFIG=$@ TECH=sky130 FREQ=1000 MAXCORES=1
+
 
-	
 synth:
 	@echo "DC Synthesis"
 	@mkdir -p hdl/
diff --git a/synthDC/hdl/wally-shared.vh b/synthDC/hdl/wally-shared.vh
deleted file mode 100644
index 198a4ab2..00000000
--- a/synthDC/hdl/wally-shared.vh
+++ /dev/null
@@ -1,99 +0,0 @@
-//////////////////////////////////////////
-// wally-shared.vh
-//
-// Written: david_harris@hmc.edu 7 June 2021
-//
-// Purpose: Shared and default configuration values common to all designs
-//
-// A component of the Wally configurable RISC-V project.
-//
-// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
-//
-// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
-// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
-// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
-// is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
-// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
-// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
-// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-///////////////////////////////////////////
-
-// include shared constants
-`include "wally-constants.vh"
-
-// macros to define supported modes
-// NOTE: No hardware support fo Q yet
-
-`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
-`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
-`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
-`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
-`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
-`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
-`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
-`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
-`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
-`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
-
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
-//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
-`define N_SUPPORTED 0
-
-
-// logarithm of XLEN, used for number of index bits to select
-`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
-
-// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
-`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
-
-
-// Floating-point half-precision
-`define ZFH_SUPPORTED 0
-
-// Floating point constants for Quad, Double, Single, and Half precisions
-`define Q_LEN 128
-`define Q_NE 15
-`define Q_NF 112
-`define Q_BIAS 16383
-`define D_LEN 64
-`define D_NE 11
-`define D_NF 52
-`define D_BIAS 1023
-`define S_LEN 32
-`define S_NE 8
-`define S_NF 23
-`define S_BIAS 127
-`define H_LEN 16
-`define H_NE 5
-`define H_NF 10
-`define H_BIAS 15
-
-// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
-`define FLEN (`Q_SUPPORTED ? `Q_LEN  : `D_SUPPORTED ? `D_LEN  : `F_SUPPORTED ? `S_LEN  : `H_LEN)
-`define NE   (`Q_SUPPORTED ? `Q_NE   : `D_SUPPORTED ? `D_NE   : `F_SUPPORTED ? `S_NE   : `H_NE)
-`define NF   (`Q_SUPPORTED ? `Q_NF   : `D_SUPPORTED ? `D_NF   : `F_SUPPORTED ? `S_NF   : `H_NF)
-`define FMT  (`Q_SUPPORTED ? 3       : `D_SUPPORTED ? 1       : `F_SUPPORTED ? 0       : 2)
-`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)
-
-// Floating point constants needed for FPU paramerterization
-`define FPSIZES (`Q_SUPPORTED+`D_SUPPORTED+`F_SUPPORTED+`ZFH_SUPPORTED)
-`define LEN1  ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN   : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN  : `H_LEN)
-`define NE1   ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE   : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE  : `H_NE)
-`define NF1   ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF  : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
-`define FMT1  ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 1        : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 0       : 2)
-`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS  : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
-`define LEN2  ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN   : `H_LEN)
-`define NE2   ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE   : `H_NE)
-`define NF2   ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF  : `H_NF)
-`define FMT2  ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 0        : 2)
-`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS  : `H_BIAS)
-
-// Disable spurious Verilator warnings
-
-/* verilator lint_off STMTDLY */
-/* verilator lint_off ASSIGNDLY */
-/* verilator lint_off PINCONNECTEMPTY */
diff --git a/synthDC/runSynth.sh b/synthDC/runSynth.sh
new file mode 100644
index 00000000..8c4451b0
--- /dev/null
+++ b/synthDC/runSynth.sh
@@ -0,0 +1,4 @@
+rm -r runs/*
+make clean
+make freqs TECH=sky130
+python3 scripts/extractSummary.py
\ No newline at end of file
diff --git a/synthDC/scripts/extractSummary.py b/synthDC/scripts/extractSummary.py
new file mode 100755
index 00000000..b7a2cc76
--- /dev/null
+++ b/synthDC/scripts/extractSummary.py
@@ -0,0 +1,50 @@
+#!/usr/bin/python3
+# Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022
+import glob 
+import re
+import csv
+import linecache
+import os 
+
+
+def main():
+    data = []
+    curr_dir = os.path.dirname(os.path.abspath(__file__))
+    output_file = os.path.join(curr_dir,"..","Summary.csv")
+    runs_dir = os.path.join(curr_dir,"..","runs/*/reports/wallypipelinedcore_qor.rep")
+    search_strings = [
+        "Critical Path Length:", "Cell Area:", "Overall Compile Time:",
+        "Critical Path Clk Period:", "Critical Path Slack:"
+    ]
+
+    for name in glob.glob(runs_dir):   
+        f = open(name, 'r')
+        trimName = re.search("wallypipelinedcore_(.*?)_2022",name).group(1)
+
+        output = {'Name':trimName}
+        num_lines = len(f.readlines())
+        curr_line_index = 0
+
+        while curr_line_index < num_lines:
+            line = linecache.getline(name, curr_line_index)
+            for search_string in search_strings:
+                if search_string in line:
+                    val = getVal(name,search_string,line,curr_line_index)
+                    output[search_string] = val
+            curr_line_index +=1 
+        data += [output]
+
+    with open(output_file, 'w') as csvfile:
+        writer = csv.DictWriter(csvfile, fieldnames=['Name'] + search_strings)
+        writer.writeheader()
+        writer.writerows(data)
+        
+def getVal(filename, search_string, line, line_index):
+    data = re.search(f"{search_string} *(.*?)\\n", line).group(1)
+    if data == '': #sometimes data is stored in two line
+        data = linecache.getline(filename, line_index+1).strip()
+    return data
+
+if __name__=="__main__":
+    main()
+                
\ No newline at end of file
diff --git a/tests/fp/run_all.sh b/tests/fp/run_all.sh
index 8d4b03dc..f1ba3625 100755
--- a/tests/fp/run_all.sh
+++ b/tests/fp/run_all.sh
@@ -3,4 +3,3 @@
 mkdir -p vectors
 ./create_vectors.sh
 ./remove_spaces.sh
-./append_ctrlSig.sh
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
index a7006338..7e6fdc8f 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
@@ -35,9 +35,10 @@ rv64i_sc_tests = \
     WALLY-CSR-permission-s-01 \
     WALLY-CSR-permission-u-01 \
     WALLY-misa-01 \
-    WALLY-sscratch-s-01 \
     WALLY-AMO \
     WALLY-LRSC \
+#    WALLY-scratch-01 \
+#    WALLY-sscratch-s-01 \
 
 #    WALLY-scratch-01 \
 
@@ -58,6 +59,12 @@ target_tests_nosim = \
     WALLY-MVENDORID \
     WALLY-CSR-PERMISSIONS-M \
     WALLY-CSR-PERMISSIONS-S \
+    WALLY-mtvec-01 \
+    WALLY-stvec-01 \
+    WALLY-MIE-01 \
+    WALLY-PIE-stack-01 \
+    WALLY-PIE-stack-s-01 \
+    WALLY-trap-sret-01 \
     WALLY-trap-01 \
     # Have all 0's in references!
     #WALLY-MEPC \
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIE-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIE-01.reference_output
new file mode 100644
index 00000000..a50302e5
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-MIE-01.reference_output
@@ -0,0 +1,1024 @@
+00000000 # test 5.3.1.6: Readback value from zeroing out MIE.
+00000000 # note that none of the attempted interrupts should fire since MIE is zeroed. 
+0000000b # mcause for ecall from terminating tests in M mode
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-01.reference_output
new file mode 100644
index 00000000..9a433054
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-01.reference_output
@@ -0,0 +1,1024 @@
+00000aaa # test 5.3.1.6: enabling all of MIE
+00000000
+0007ec03 # value to indicate successful vectoring on m soft interrupt 
+00000000
+00000003 # mcause value from m time interrupt
+80000000
+00000000 # mtval for mtime interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
+0000000b # mcause for ecall from terminating tests in M mode
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output
new file mode 100644
index 00000000..748d8b72
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-PIE-stack-s-01.reference_output
@@ -0,0 +1,1024 @@
+00000aaa # test 5.3.1.6: enabling all of MIE
+00000000
+00000222 # writeaback for delegating all interrupts to S mode
+00000000
+0000000b # mcause for ecall from going to S mode from M mode
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000000
+0007ec01 # value to indicate successful vectoring on s soft interrupt 
+00000000
+00000001 # scause value from s soft interrupt
+80000000
+00000000 # stval for ssoft interrupt (0x0)
+00000000
+00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
+00000000 # Note here that we atempt to cause an interrupt after zeroing status.mie, but it shouldn't fire.
+00000009 # mcause for ecall from terminating tests in S mode
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
index bc760ed6..5503d02b 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-mtvec-01.reference_output
@@ -1,3 +1,17 @@
+00000aaa # Test 5.3.1.5: readback value of SIE after enabling all interrupts.
+00000000
+00000007 # mcause from m time interrupt
+80000000
+00000000 # mtval for mtime interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0000000b # mcause from M mode ecall from test termination
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
 deadbeef
 deadbeef
 deadbeef
@@ -1007,18 +1021,4 @@ deadbeef
 deadbeef
 deadbeef
 deadbeef
-deadbeef
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-deadbeef
-deadbeef
-deadbeef
-deadbeef
+deadbeef
\ No newline at end of file
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output
index bc760ed6..769df382 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-stvec-01.reference_output
@@ -1,43 +1,43 @@
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
-deadbeef
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-deadbeef
-deadbeef
-deadbeef
-deadbeef
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-deadbeef
-deadbeef
+00000aaa # Test 5.3.1.5: readback value of MIE after enabling all interrupts.
+00000000
+00000222 # readback value of mideleg after attempting to delegate all interrupts.
+00000000
+0000000b # mcause from ecall for going from M mode to S mode
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000000
+00000001 # mcause from s soft interrupt
+80000000
+00000000 # mtval for ssoft interrupt (0x0)
+00000000
+00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
+00000000
+00000009 # mcause from ecall for going from S mode to M mode
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000000
+0000000b # mcause from ecall for going from M mode to U mode
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000000
+00000001 # mcause from s soft interrupt from user mode this time
+80000000
+00000000 # mtval for mtime interrupt (0x0)
+00000000
+00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
+00000000
+00000008 # mcause from U mode ecall from test termination
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00000000 # masked out mstatus.MPP = 00, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000000
 deadbeef
 deadbeef
 deadbeef
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
index eef583de..8165e85c 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
@@ -1,5 +1,11 @@
 00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
 00000000
+00000000 # mcause from instruction addr misaligned fault
+00000000
+800003d2 # mtval of faulting instruction adress (0x800003d3)
+00000000 
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
 00000001 # mcause from an instruction access fault
 00000000
 00000000 # mtval of faulting instruction address (0x0)
@@ -14,13 +20,13 @@
 00000000
 00000003 # mcause from Breakpoint
 00000000
-800003ec # mtval of breakpoint instruction adress (0x800003ec)
+80000404 # mtval of breakpoint instruction adress (0x80000404)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-800003f5 # mtval of misaligned address (0x800003f5)
+8000040d # mtval of misaligned address (0x8000040d)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -32,7 +38,7 @@
 00000000
 00000006 # mcause from store misaligned
 00000000
-80000411 # mtval of address with misaligned store instr (0x80000410)
+80000429 # mtval of address with misaligned store instr (0x80000429)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -60,7 +66,31 @@
 00000000
 00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec01 # value to indicate successful vectoring on s soft interrupt 
+00000000
+00000001 # mcause value from s soft interrupt
+80000000
+00000000 # mtval for ssoft interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0007ec03 # value to indicate successful vectoring on m soft interrupt 
+00000000
+00000003 # mcause value from m soft interrupt
+80000000
+00000000 # mtval for msoft interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0007ec05 # value to indicate successful vectoring on s time interrupt 
+00000000
+00000005 # mcause value from s time interrupt
+80000000
+00000000 # mtval for stime interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0007ec07 # value to indicate successful vectoring on m time interrupt 
 00000000
 00000007 # mcause value from m time interrupt
 80000000
@@ -68,15 +98,15 @@
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec09 # value to indicate successful vectoring on s ext interrupt 
 00000000
-00000001 # mcause value from m soft interrupt
+00000009 # mcause value from s ext interrupt
 80000000
-00000000 # mtval for msoft interrupt (0x0)
+00000000 # mtval for sext interrupt (0x0)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec0b # value to indicate successful vectoring on m ext interrupt 
 00000000
 0000000b # mcause value from m ext interrupt
 80000000
@@ -84,11 +114,17 @@
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
-00000000
+fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
+ffffffff
 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
 00000000
-00000001 # Test 5.3.1.4: mcause from an instruction access fault
+00000000 # mcause from instruction addr misaligned fault
+00000000
+800003d2 # mtval of faulting instruction adress (0x800003d3)
+00000000 
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+00000001 # mcause from an instruction access fault
 00000000
 00000000 # mtval of faulting instruction address (0x0)
 00000000
@@ -102,13 +138,13 @@
 00000000
 00000003 # mcause from Breakpoint
 00000000
-800003ec # mtval of breakpoint instruction adress (0x800003ec)
+80000404 # mtval of breakpoint instruction adress (0x80000404)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
 00000004 # mcause from load address misaligned
 00000000
-800003f5 # mtval of misaligned address (0x800003f5)
+8000040d # mtval of misaligned address (0x8000040d)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -120,7 +156,7 @@
 00000000
 00000006 # mcause from store misaligned
 00000000
-80000411 # mtval of address with misaligned store instr (0x80000410)
+80000429 # mtval of address with misaligned store instr (0x80000429)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
@@ -136,23 +172,23 @@
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec03 # value to indicate successful vectoring on m soft interrupt 
 00000000
-00000007 # mcause value from  time interrupt
-80000000
-00000000 # mtval for mtime interrupt (0x0)
-00000000
-00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
-00000000
-000007ec # value to indicate a vectored interrupts
-00000000
-00000001 # mcause value from m soft interrupt
+00000003 # mcause value from m soft interrupt
 80000000
 00000000 # mtval for msoft interrupt (0x0)
 00000000
 00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
 00000000
-000007ec # value to indicate a vectored interrupts
+0007ec07 # value to indicate successful vectoring on m time interrupt 
+00000000
+00000007 # mcause value from m time interrupt
+80000000
+00000000 # mtval for mtime interrupt (0x0)
+00000000
+00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
+00000000
+0007ec0b # value to indicate successful vectoring on m ext interrupt 
 00000000
 0000000b # mcause value from m ext interrupt
 80000000
@@ -978,97 +1014,3 @@ deadbeef
 deadbeef
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output
new file mode 100644
index 00000000..18201197
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-sret-01.reference_output
@@ -0,0 +1,1024 @@
+0000000b # test 5.3.1.6: mcause for ecall from going to S mode from M mode
+00000000
+00000000 # mtval of ecall (*** defined to be zero for now)
+00000000
+00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000000
+00000002 # mcause for illegal sret instruction due to status.tsr bit being set.
+00000000
+10200073 # mtval of illegal instruction (illegal instruction's machine code)
+00000000
+00000800 # masked out mstatus.MPP = 01, mstatus.MPIE = 0, and mstatus.MIE = 0
+00000000
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diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S
new file mode 100644
index 00000000..bc691507
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-MIE-01.S
@@ -0,0 +1,44 @@
+///////////////////////////////////////////
+//
+// WALLY-MIE
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-04-10
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
+
+TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
+
+li x28, 0x8
+csrs mstatus, x28 // set mstatus.MIE bit to 1.
+WRITE_READ_CSR mie, 0x0 // force zeroing out mie CSR.
+
+// test 5.3.1.6 Interrupt enabling and priority tests 
+// note that none of these interrupts should be caught or handled.
+
+jal cause_m_soft_interrupt
+
+END_TESTS
+
+TEST_STACK_AND_DATA
+
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S
new file mode 100644
index 00000000..cdfd3334
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S
@@ -0,0 +1,49 @@
+///////////////////////////////////////////
+//
+// WALLY-privilege-interrupt-enable-stack
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-04-10
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
+
+TRAP_HANDLER m, DEBUG=1
+
+li x28, 0x8
+csrs mstatus, x28 // set mstatus.MIE bit to 1 
+WRITE_READ_CSR mie, 0xFFF
+
+// test 5.3.1.6 Interrupt enabling and priority tests 
+
+// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling 
+jal cause_m_soft_interrupt
+
+li x28, 0x8
+csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen
+
+// attempt to cause interrupt, it should not go through
+jal cause_m_soft_interrupt
+
+END_TESTS
+
+TEST_STACK_AND_DATA
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S
new file mode 100644
index 00000000..8a139e19
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S
@@ -0,0 +1,53 @@
+///////////////////////////////////////////
+//
+// WALLY-privilege-interrupt-enable-stack
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-04-10
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
+
+TRAP_HANDLER m, DEBUG=1 // necessary so we can go to S mode
+TRAP_HANDLER s, DEBUG=1 // neccessary to handle s mode interrupts. 
+
+li x28, 0x2
+csrs sstatus, x28 // set sstatus.SIE bit to 1
+WRITE_READ_CSR mie, 0xFFF // enable all interrupts, including supervisor ones
+WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
+
+// test 5.3.1.6 Interrupt enabling and priority tests 
+
+GOTO_S_MODE
+
+// Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling 
+jal cause_s_soft_interrupt
+
+li x28, 0x2
+csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen
+
+// attempt to cause interrupt, it should not go through
+jal cause_s_soft_interrupt
+
+END_TESTS
+
+TEST_STACK_AND_DATA
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
index 4f96071e..c9ae5cf0 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h
@@ -84,7 +84,7 @@ cause_instr_access:
     ret
 
 cause_illegal_instr:
-    .word 0x00000000 // a 32 bit zros is an illegal instruction
+    .word 0x00000000 // 32 bit zero is an illegal instruction
     ret
 
 cause_breakpnt:
@@ -118,7 +118,7 @@ cause_ecall:
     ecall
     ret
 
-cause_time_interrupt:
+cause_m_time_interrupt:
     // The following code works for both RV32 and RV64.  
     // RV64 alone would be easier using double-word adds and stores
     li x28, 0x30          // Desired offset from the present time
@@ -132,23 +132,99 @@ cause_time_interrupt:
     sw x31,4(x29)          // store into most significant word of MTIMECMP
 nowrap:
     sw x28, 0(x29)         // store into least significant word of MTIMECMP
-loop:
-    wfi 
-    j loop         // wait until interrupt occurs
+time_loop:
+    wfi
+    j time_loop             // wait until interrupt occurs
     ret
 
-cause_soft_interrupt:
+cause_s_time_interrupt:
+    li x28, 0x20
+    csrs mip, x28 // set supervisor time interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
+    nop // added extra nops in so the csrs can get through the pipeline before returning.
+    ret
+
+cause_m_soft_interrupt:
     la x28, 0x02000000      // MSIP register in CLINT
     li x29, 1               // 1 in the lsb
     sw x29, 0(x28)          // Write MSIP bit
     ret
 
-cause_ext_interrupt:
+cause_s_soft_interrupt:
+    li x28, 0x2
+    csrs sip, x28 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP.
+    ret
+
+cause_m_ext_interrupt:
+    # ========== Configure PLIC ==========
+    # m priority threshold = 0
+    li x28, 0xC200000
+    li x29, 0
+    sw x29, 0(x28)
+    # source 3 (GPIO) priority = 1
+    li x28, 0xC000000
+    li x29, 1
+    sw x29, 0x0C(x28)
+    # enable source 3 in M Mode
+    li x28, 0x0C002000
+    li x29, 0b1000 
+    sw x29, 0(x28)
+
     li x28, 0x10060000 // load base GPIO memory location
     li x29, 0x1
-    sw x29, 8(x28) // enable the first pin as an output
-    sw x29, 28(x28) // set first pin to high interrupt enable
-    sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
+    sw x29, 0x08(x28)  // enable the first pin as an output
+
+    sw x0, 0x1C(x28) // clear rise_ip
+    sw x0, 0x24(x28) // clear fall_ip
+    sw x0, 0x2C(x28) // clear high_ip
+    sw x0, 0x34(x28) // clear low_ip
+
+    sw x29, 0x28(x28)  // set first pin to interrupt on a rising value
+    sw x29, 0x0C(x28)  // write a 1 to the first output pin (cause interrupt)
+m_ext_loop:
+    wfi
+    lw x29, 0x8(x28)
+    bnez x28, m_ext_loop // go through this loop until the trap handler has disabled the GPIO output pins.
+    ret
+
+cause_s_ext_interrupt_GPIO:
+    # ========== Configure PLIC ==========
+    # s priority threshold = 0
+    li x28, 0xC201000
+    li x29, 0
+    sw x29, 0(x28)
+    # m priority threshold = 7
+    li x28, 0xC200000
+    li x29, 7
+    sw x29, 0(x28)
+    # source 3 (GPIO) priority = 1
+    li x28, 0xC000000
+    li x29, 1
+    sw x29, 0x0C(x28)
+    # enable source 3 in S mode
+    li x28, 0x0C002080
+    li x29, 0b1000 
+    sw x29, 0(x28)
+
+    li x28, 0x10060000 // load base GPIO memory location
+    li x29, 0x1
+    sw x29, 0x08(x28)  // enable the first pin as an output
+
+    sw x0, 0x1C(x28) // clear rise_ip
+    sw x0, 0x24(x28) // clear fall_ip
+    sw x0, 0x2C(x28) // clear high_ip
+    sw x0, 0x34(x28) // clear low_ip
+
+    sw x29, 0x28(x28)  // set first pin to interrupt on a rising value
+    sw x29, 0x0C(x28)  // write a 1 to the first output pin (cause interrupt)
+s_ext_loop:
+    wfi
+    lw x29, 0x8(x28)
+    bnez x28, s_ext_loop // go through this loop until the trap handler has disabled the GPIO output pins.
+    ret
+
+cause_s_ext_interrupt_IP:
+    li x28, 0x200
+    csrs mip, x28 // set supervisor external interrupt pending.
     ret
 
 end_trap_triggers:
@@ -216,7 +292,7 @@ end_trap_triggers:
     //     
     // --------------------------------------------------------------------------------------------
 
-.align 2
+.align 3
 trap_handler_\MODE\():
     j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
     // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
@@ -273,18 +349,19 @@ trap_stack_saved_\MODE\(): // jump here after handling vectored interupt since w
     // Respond to trap based on cause
     // All interrupts should return after being logged
     csrr x1, \MODE\()cause
-    slli x1, x1, 3          // multiply cause by 8 to get offset in vector Table
     li x5, 0x8000000000000000   // if msb is set, it is an interrupt
     and x5, x5, x1
     bnez x5, interrupt_handler_\MODE\()  // return from interrupt
     // Other trap handling is specified in the vector Table
     la x5, exception_vector_table_\MODE\()
+    slli x1, x1, 3          // multiply cause by 8 to get offset in vector Table
     add x5, x5, x1      // compute address of vector in Table
     ld x5, 0(x5)        // fectch address of handler from vector Table
     jr x5               // and jump to the handler
 
 interrupt_handler_\MODE\():
     la x5, interrupt_vector_table_\MODE\() // NOTE THIS IS NOT THE SAME AS VECTORED INTERRUPTS!!!
+    slli x1, x1, 3          // multiply cause by 8 to get offset in vector Table
     add x5, x5, x1      // compute address of vector in Table
     ld x5, 0(x5)        // fectch address of handler from vector Table
     jr x5               // and jump to the handler
@@ -343,6 +420,7 @@ trapreturn_finished_\MODE\():
     ld x7, -24(sp)     // restore registers from stack before returning
     ld x5, -16(sp)
     ld x1, -8(sp)
+    csrrw sp, \MODE\()scratch, sp // switch sp and scratch stack back to restore the non-trap stack pointer
     \MODE\()ret  // return from trap
 
 ecallhandler_\MODE\():
@@ -364,7 +442,7 @@ ecallhandler_changetomachinemode_\MODE\():
 
 ecallhandler_changetosupervisormode_\MODE\():
     // Force status.MPP (bits 12:11) to 01 to enter supervisor mode after mret
-    li x1, 0b1100000000000  
+    li x1, 0b1000000000000  
     csrc \MODE\()status, x1
     li x1, 0b0100000000000
     csrs \MODE\()status, x1
@@ -440,23 +518,52 @@ vectored_int_end_\MODE\():
     j trap_stack_saved_\MODE\()
 
 soft_interrupt_\MODE\():
-    la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
-    sw x0, 0(x28)
-    j trapreturn_\MODE\()
+    la x5, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
+    sw x0, 0(x5)
+
+    csrci \MODE\()ip, 0x2 // clear supervisor software interrupt pending bit 
+    ld x1, -8(sp) // load return address from stack into ra (the address to return to after causing this interrupt)
+    // Note: we do this because the mepc loads in the address of the instruction after the sw that causes the interrupt
+    //  This means that this trap handler will return to the next address after that one, which might be unpredictable behavior.
+    j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
 
 time_interrupt_\MODE\():
-    la x29, 0x02004000    // MTIMECMP register in CLINT
-    li x30, 0xFFFFFFFF
-    sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
+    la x5, 0x02004000    // MTIMECMP register in CLINT
+    li x7, 0xFFFFFFFF
+    sd x7, 0(x5) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
     
-    ld x1, -8(sp) // load return address from stack into ra (the address AFTER the jal to the faulting address)
+    li x5, 0x20
+    csrc \MODE\()ip, x5
+    ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
     j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
 
 ext_interrupt_\MODE\():
     li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
     sw x0, 8(x28) // disable the first pin as an output
     sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
-    j trapreturn_\MODE\()
+
+    # reset PLIC to turn off external interrupts
+    # priority threshold = 7
+    li x28, 0xC200000
+    li x5, 0x7
+    sw x5, 0(x28)
+    # source 3 (GPIO) priority = 0
+    li x28, 0xC000000
+    li x5, 0
+    sw x5, 0x0C(x28)
+    # disable source 3
+    li x28, 0x0C002000
+    li x5, 0b0000
+    sw x5, 0(x28)
+
+    li x5, 0x200
+    csrc \MODE\()ip, x5
+
+    ld x1, -8(sp) // load return address from stack into ra (the address to return to after the loop is complete)
+    j trapreturn_finished_\MODE\() // return to the code at ra value from before trap
+
+
+
 
     // Table of trap behavior
     // lists what to do on each exception (not interrupts)
@@ -485,17 +592,17 @@ exception_vector_table_\MODE\():
     .align 3 // aligns this data table to an 8 byte boundary
 interrupt_vector_table_\MODE\():
     .8byte segfault_\MODE\()            // 0: reserved
-    .8byte s_soft_vector_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
+    .8byte soft_interrupt_\MODE\()    // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
     .8byte segfault_\MODE\()            // 2: reserved
-    .8byte m_soft_vector_\MODE\()    // 3: breakpoint
+    .8byte soft_interrupt_\MODE\()    // 3: breakpoint
     .8byte segfault_\MODE\()            // 4: reserved
-    .8byte s_time_vector_\MODE\()    // 5: load access fault
+    .8byte time_interrupt_\MODE\()    // 5: load access fault
     .8byte segfault_\MODE\()            // 6: reserved
-    .8byte m_time_vector_\MODE\()    // 7: store access fault
+    .8byte time_interrupt_\MODE\()    // 7: store access fault
     .8byte segfault_\MODE\()            // 8: reserved
-    .8byte s_ext_vector_\MODE\()     // 9: ecall from S-mode
+    .8byte ext_interrupt_\MODE\()     // 9: ecall from S-mode
     .8byte segfault_\MODE\()            // 10: reserved
-    .8byte m_ext_vector_\MODE\()     // 11: ecall from M-mode
+    .8byte ext_interrupt_\MODE\()     // 11: ecall from M-mode
 
 .align 3
 trap_return_pagetype_table_\MODE\():
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
index b90291bc..635ed1c6 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S
@@ -25,20 +25,19 @@
 
 INIT_TESTS
 
+CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
+
 // test 5.3.1.5 Unvectored interrupt tests 
 
 TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
 li x28, 0x8
-csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
-// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+WRITE_READ_CSR mie, 0xFFF
 
 // cause traps, ensuring that we DONT go through the vectored part of the trap handler
-// *** this assumes that interrupt code 0 remains reserved
 
-// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
-// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
-// CAUSE_EXT_INTERRUPT
+jal cause_m_time_interrupt
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
index 688c7891..949984ea 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S
@@ -25,30 +25,29 @@
 
 INIT_TESTS
 
+CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
+
 // test 5.3.1.5 Unvectored interrupt tests 
 
+TRAP_HANDLER m, VECTORED=0, DEBUG=1 // necessary to handle changing modes
 TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
-// li x28, 0x8
-// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
-// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
-
+li x28, 0x2
+csrs sstatus, x28 // set sstatus.SIE bit to 1
+WRITE_READ_CSR mie, 0xFFFF
 WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
 
+// cause traps, ensuring that we DONT go through the vectored part of the trap handler
+
 GOTO_S_MODE
 
-// cause traps, ensuring that we DONT go through the vectored part of the trap handler
-// *** this assumes that interrupt code 0 remains reserved
+jal cause_s_soft_interrupt
 
-// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
-// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
-// CAUSE_EXT_INTERRUPT
+GOTO_M_MODE 
 
-GOTO_U_MODE 
+jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode
 
-// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
-// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
-// CAUSE_EXT_INTERRUPT
+GOTO_U_MODE // Should cause software interrupt to fire off. 
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
index 45d34c34..17100fbb 100644
--- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
@@ -35,7 +35,7 @@ WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented
 
 // test 5.3.1.4 Basic trap tests 
 
-// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_addr_misaligned
 jal cause_instr_access
 jal cause_illegal_instr
 jal cause_breakpnt
@@ -47,16 +47,23 @@ GOTO_U_MODE // Causes M mode ecall
 GOTO_S_MODE // Causes U mode ecall
 GOTO_M_MODE // Causes S mode ecall
 
-jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
-jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
-jal cause_ext_interrupt
+
+jal cause_s_soft_interrupt 
+jal cause_m_soft_interrupt
+jal cause_s_time_interrupt
+jal cause_m_time_interrupt
+//jal cause_s_ext_interrupt_GPIO
+jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
+jal cause_m_ext_interrupt
+
+
 
 // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
 
 WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
 WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
 
-// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
+jal cause_instr_addr_misaligned
 jal cause_instr_access
 jal cause_illegal_instr
 jal cause_breakpnt
@@ -66,9 +73,14 @@ jal cause_store_addr_misaligned
 jal cause_store_acc
 jal cause_ecall // M mode ecall
 
-jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen. 
-jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
-jal cause_ext_interrupt
+jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode.
+jal cause_m_soft_interrupt
+jal cause_s_time_interrupt
+jal cause_m_time_interrupt
+//jal cause_s_ext_interrupt_GPIO
+jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
+jal cause_m_ext_interrupt
+
 
 END_TESTS
 
diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S
new file mode 100644
index 00000000..42690c79
--- /dev/null
+++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-sret-01.S
@@ -0,0 +1,42 @@
+///////////////////////////////////////////
+//
+// WALLY-trap-sret
+//
+// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
+//
+// Created 2022-04-10
+//
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
+// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
+// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
+// is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+///////////////////////////////////////////
+
+#include "WALLY-TEST-LIB-64.h"
+
+INIT_TESTS
+
+TRAP_HANDLER m, DEBUG=1
+
+// test 5.3.1.6 Interrupt enabling and priority tests 
+
+li x28, 0x400000
+csrs mstatus, x28 // Set mstatus.tsr to 1.
+
+GOTO_S_MODE
+
+sret // attempt to run sret instruction. 
+// should cause illegal instruction exception despite being in s mode
+
+END_TESTS
+
+TEST_STACK_AND_DATA