From 2157970adf05ef652f5217560f075d7b1f6b64a8 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 16:00:27 -0600 Subject: [PATCH 1/7] Moved branch predictor files into separate sub-directory. --- pipelined/src/ifu/{ => brpred}/BTBPredictor.sv | 0 pipelined/src/ifu/{ => brpred}/RAsPredictor.sv | 0 pipelined/src/ifu/{ => brpred}/bpred.sv | 0 pipelined/src/ifu/{ => brpred}/foldedgshare.sv | 0 pipelined/src/ifu/{ => brpred}/globalHistoryPredictor.sv | 0 pipelined/src/ifu/{ => brpred}/globalhistory.sv | 0 pipelined/src/ifu/{ => brpred}/gshare.sv | 0 pipelined/src/ifu/{ => brpred}/localHistoryPredictor.sv | 0 pipelined/src/ifu/{ => brpred}/oldgsharepredictor.sv | 0 pipelined/src/ifu/{ => brpred}/oldgsharepredictor2.sv | 0 pipelined/src/ifu/{ => brpred}/optgshare.sv | 0 pipelined/src/ifu/{ => brpred}/satCounter2.sv | 0 pipelined/src/ifu/{ => brpred}/speculativeglobalhistory.sv | 0 pipelined/src/ifu/{ => brpred}/speculativegshare.sv | 0 pipelined/src/ifu/{ => brpred}/twoBitPredictor.sv | 0 15 files changed, 0 insertions(+), 0 deletions(-) rename pipelined/src/ifu/{ => brpred}/BTBPredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/RAsPredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/bpred.sv (100%) rename pipelined/src/ifu/{ => brpred}/foldedgshare.sv (100%) rename pipelined/src/ifu/{ => brpred}/globalHistoryPredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/globalhistory.sv (100%) rename pipelined/src/ifu/{ => brpred}/gshare.sv (100%) rename pipelined/src/ifu/{ => brpred}/localHistoryPredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/oldgsharepredictor.sv (100%) rename pipelined/src/ifu/{ => brpred}/oldgsharepredictor2.sv (100%) rename pipelined/src/ifu/{ => brpred}/optgshare.sv (100%) rename pipelined/src/ifu/{ => brpred}/satCounter2.sv (100%) rename pipelined/src/ifu/{ => brpred}/speculativeglobalhistory.sv (100%) rename pipelined/src/ifu/{ => brpred}/speculativegshare.sv (100%) rename pipelined/src/ifu/{ => brpred}/twoBitPredictor.sv (100%) diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/brpred/BTBPredictor.sv similarity index 100% rename from pipelined/src/ifu/BTBPredictor.sv rename to pipelined/src/ifu/brpred/BTBPredictor.sv diff --git a/pipelined/src/ifu/RAsPredictor.sv b/pipelined/src/ifu/brpred/RAsPredictor.sv similarity index 100% rename from pipelined/src/ifu/RAsPredictor.sv rename to pipelined/src/ifu/brpred/RAsPredictor.sv diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv similarity index 100% rename from pipelined/src/ifu/bpred.sv rename to pipelined/src/ifu/brpred/bpred.sv diff --git a/pipelined/src/ifu/foldedgshare.sv b/pipelined/src/ifu/brpred/foldedgshare.sv similarity index 100% rename from pipelined/src/ifu/foldedgshare.sv rename to pipelined/src/ifu/brpred/foldedgshare.sv diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/brpred/globalHistoryPredictor.sv similarity index 100% rename from pipelined/src/ifu/globalHistoryPredictor.sv rename to pipelined/src/ifu/brpred/globalHistoryPredictor.sv diff --git a/pipelined/src/ifu/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv similarity index 100% rename from pipelined/src/ifu/globalhistory.sv rename to pipelined/src/ifu/brpred/globalhistory.sv diff --git a/pipelined/src/ifu/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv similarity index 100% rename from pipelined/src/ifu/gshare.sv rename to pipelined/src/ifu/brpred/gshare.sv diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/brpred/localHistoryPredictor.sv similarity index 100% rename from pipelined/src/ifu/localHistoryPredictor.sv rename to pipelined/src/ifu/brpred/localHistoryPredictor.sv diff --git a/pipelined/src/ifu/oldgsharepredictor.sv b/pipelined/src/ifu/brpred/oldgsharepredictor.sv similarity index 100% rename from pipelined/src/ifu/oldgsharepredictor.sv rename to pipelined/src/ifu/brpred/oldgsharepredictor.sv diff --git a/pipelined/src/ifu/oldgsharepredictor2.sv b/pipelined/src/ifu/brpred/oldgsharepredictor2.sv similarity index 100% rename from pipelined/src/ifu/oldgsharepredictor2.sv rename to pipelined/src/ifu/brpred/oldgsharepredictor2.sv diff --git a/pipelined/src/ifu/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv similarity index 100% rename from pipelined/src/ifu/optgshare.sv rename to pipelined/src/ifu/brpred/optgshare.sv diff --git a/pipelined/src/ifu/satCounter2.sv b/pipelined/src/ifu/brpred/satCounter2.sv similarity index 100% rename from pipelined/src/ifu/satCounter2.sv rename to pipelined/src/ifu/brpred/satCounter2.sv diff --git a/pipelined/src/ifu/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv similarity index 100% rename from pipelined/src/ifu/speculativeglobalhistory.sv rename to pipelined/src/ifu/brpred/speculativeglobalhistory.sv diff --git a/pipelined/src/ifu/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv similarity index 100% rename from pipelined/src/ifu/speculativegshare.sv rename to pipelined/src/ifu/brpred/speculativegshare.sv diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/brpred/twoBitPredictor.sv similarity index 100% rename from pipelined/src/ifu/twoBitPredictor.sv rename to pipelined/src/ifu/brpred/twoBitPredictor.sv From 7d1109fc24289058e307692e297f40a6840f2c3d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 16:12:35 -0600 Subject: [PATCH 2/7] Partial BTB cleanup. --- pipelined/src/ifu/brpred/BTBPredictor.sv | 114 ----------------------- pipelined/src/ifu/brpred/bpred.sv | 13 ++- 2 files changed, 6 insertions(+), 121 deletions(-) delete mode 100644 pipelined/src/ifu/brpred/BTBPredictor.sv diff --git a/pipelined/src/ifu/brpred/BTBPredictor.sv b/pipelined/src/ifu/brpred/BTBPredictor.sv deleted file mode 100644 index ba5fe374..00000000 --- a/pipelined/src/ifu/brpred/BTBPredictor.sv +++ /dev/null @@ -1,114 +0,0 @@ -/////////////////////////////////////////// -// ram2p1r1wb -// -// Written: Ross Thomposn -// Email: ross1728@gmail.com -// Created: February 15, 2021 -// Modified: -// -// Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want -// to encode to reduce storage), valid, target PC. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module BTBPredictor - #(parameter int Depth = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallE, - input logic [`XLEN-1:0] LookUpPC, - output logic [`XLEN-1:0] TargetPC, - output logic [3:0] InstrClass, - output logic Valid, - // update - input logic UpdateEN, - input logic [`XLEN-1:0] UpdatePC, - input logic [`XLEN-1:0] UpdateTarget, - input logic [3:0] UpdateInstrClass, - input logic UpdateInvalid - ); - - localparam TotalDepth = 2 ** Depth; - logic [TotalDepth-1:0] ValidBits; - logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ; - logic UpdateENQ; - - - // hashing function for indexing the PC - // We have Depth bits to index, but XLEN bits as the input. - // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if - // using compressed instructions. XOR bit 1 with the MSB of index. - assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]}; - assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]}; - - - flopenr #(Depth) UpdatePCIndexReg(.clk(clk), - .reset(reset), - .en(~StallE), - .d(UpdatePCIndex), - .q(UpdatePCIndexQ)); - - // The valid bit must be resetable. - always_ff @ (posedge clk) begin - if (reset) begin - ValidBits <= #1 {TotalDepth{1'b0}}; - end else - if (UpdateENQ) begin - ValidBits[UpdatePCIndexQ] <= #1 ~ UpdateInvalid; - end - end - assign Valid = ValidBits[LookUpPCIndexQ]; - - - flopenr #(1) UpdateENReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(UpdateEN), - .q(UpdateENQ)); - - - flopenr #(Depth) LookupPCIndexReg(.clk(clk), - .reset(reset), - .en(~StallF), - .d(LookUpPCIndex), - .q(LookUpPCIndexQ)); - - - - // the BTB contains the target address. - // Another optimization may be using a PC relative address. - // *** need to add forwarding. - - // *** optimize for byte write enables - // *** switch to ram2p1r1wbefix - ram2p1r1wb #(Depth, `XLEN+4) memory(.clk(clk), - .reset(reset), - .ra1(LookUpPCIndex), - .rd1({{InstrClass, TargetPC}}), - .ren1(~StallF), - .wa2(UpdatePCIndex), - .wd2({UpdateInstrClass, UpdateTarget}), - .wen2(UpdateEN), - .bwe2({4'hF, {`XLEN{1'b1}}})); // *** definitely not right. - - -endmodule diff --git a/pipelined/src/ifu/brpred/bpred.sv b/pipelined/src/ifu/brpred/bpred.sv index ab47d678..9c5efe30 100644 --- a/pipelined/src/ifu/brpred/bpred.sv +++ b/pipelined/src/ifu/brpred/bpred.sv @@ -135,20 +135,19 @@ module bpred ( // Part 2 Branch target address prediction // *** For now the BTB will house the direct and indirect targets - // *** getting to many false positivies from the BTB, we need a partial TAG to reduce this. - BTBPredictor TargetPredictor(.clk(clk), + btb TargetPredictor(.clk(clk), .reset(reset), .*, // Stalls and flushes - .LookUpPC(PCNextF), - .TargetPC(BTBPredPCF), + .PCNextF, + .BTBPredPCF, .InstrClass(PredInstrClassF), .Valid(BTBValidF), // update .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE), - .UpdatePC(PCE), - .UpdateTarget(IEUAdrE), + .PCE, + .IEUAdrE, .UpdateInvalid(PredictionInstrClassWrongE), - .UpdateInstrClass(InstrClassE)); + .InstrClassE); // Part 3 RAS // *** need to add the logic to restore RAS on flushes. We will use incr for this. From 1170dc7250a04c497226f3053f36a0cec06e0d93 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 17:19:51 -0600 Subject: [PATCH 3/7] Moved and ranamed btb to btb.sv Fixed btb to use the fixed port 2 sram. --- pipelined/src/generic/mem/ram2p1r1wb.sv | 8 +- pipelined/src/generic/mem/ram2p1rwbefix.sv | 4 +- pipelined/src/ifu/brpred/btb.sv | 110 +++++++++++++++++++++ 3 files changed, 117 insertions(+), 5 deletions(-) create mode 100644 pipelined/src/ifu/brpred/btb.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv index 5e79d5e2..7ac29e1d 100644 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -74,12 +74,14 @@ module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) ( flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q); // read port - assign rd1 = mem[ra1q]; + //assign rd1 = mem[ra1q]; + always_ff @(posedge clk) + if(ren1) rd1 <= mem[ra1]; // write port - assign bwe = {WIDTH{wen2q}} & bwe2; + assign bwe = {WIDTH{wen2}} & bwe2; always_ff @(posedge clk) - mem[wa2q] <= wd2q & bwe | mem[wa2q] & ~bwe; + mem[wa2] <= wd2 & bwe | mem[wa2] & ~bwe; endmodule diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv index 9b9beaf9..ac30343b 100644 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv @@ -59,13 +59,13 @@ module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) ( // Write divided into part for bytes and part for extra msbs if(WIDTH >= 8) - always_ff @(posedge clk) + always @(posedge clk) if (ce2 & we2) for(i = 0; i < WIDTH/8; i++) if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always_ff @(posedge clk) + always @(posedge clk) if (ce2 & we2 & bwe2[WIDTH/8]) mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv new file mode 100644 index 00000000..6666c35f --- /dev/null +++ b/pipelined/src/ifu/brpred/btb.sv @@ -0,0 +1,110 @@ +/////////////////////////////////////////// +// btb.sv +// +// Written: Ross Thomposn ross1728@gmail.com +// Created: February 15, 2021 +// Modified: 24 January 2023 +// +// Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions. +// It also guesses the type of instrution; jalr(r), return, jump (jr), or branch. +// +// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module btb + #(parameter int Depth = 10 + ) + (input logic clk, + input logic reset, + input logic StallF, StallE, + input logic [`XLEN-1:0] PCNextF, + output logic [`XLEN-1:0] BTBPredPCF, + output logic [3:0] InstrClass, + output logic Valid, + // update + input logic UpdateEN, + input logic [`XLEN-1:0] PCE, + input logic [`XLEN-1:0] IEUAdrE, + input logic [3:0] InstrClassE, + input logic UpdateInvalid + ); + + localparam TotalDepth = 2 ** Depth; + logic [TotalDepth-1:0] ValidBits; + logic [Depth-1:0] PCNextFIndex, PCEIndex, PCNextFIndexQ, PCEIndexQ; + logic UpdateENQ; + logic [`XLEN-1:0] ResetPC; + + + // hashing function for indexing the PC + // We have Depth bits to index, but XLEN bits as the input. + // bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if + // using compressed instructions. XOR bit 1 with the MSB of index. + assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]}; + assign ResetPC = `RESET_VECTOR; + assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; + //assign PCNextFIndex = {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; + + flopenr #(Depth) PCEIndexReg(.clk(clk), + .reset(reset), + .en(~StallE), + .d(PCEIndex), + .q(PCEIndexQ)); + + // The valid bit must be resetable. + always_ff @ (posedge clk) begin + if (reset) begin + ValidBits <= #1 {TotalDepth{1'b0}}; + end else + if (UpdateENQ) begin + ValidBits[PCEIndexQ] <= #1 ~ UpdateInvalid; + end + end + assign Valid = ValidBits[PCNextFIndexQ]; + + + flopenr #(1) UpdateENReg(.clk(clk), + .reset(reset), + .en(~StallF), + .d(UpdateEN), + .q(UpdateENQ)); + + + flopenr #(Depth) LookupPCIndexReg(.clk(clk), + .reset(reset), + .en(~StallF), + .d(PCNextFIndex), + .q(PCNextFIndexQ)); + + + + // the BTB contains the target address. + // Another optimization may be using a PC relative address. + // *** need to add forwarding. + + // *** optimize for byte write enables + + ram2p1r1wbefix #(2**Depth, `XLEN+4) memory( + .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), + .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); + +endmodule From 1acbdaeca6d381397b16a5afda7b8a78dc760cd7 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 17:22:00 -0600 Subject: [PATCH 4/7] Removed the old two port ram and replaced it with the fixed version. The fixed version is renamed to ram2p1r1wb.sv --- pipelined/src/generic/mem/ram2p1r1wb.sv | 88 ------------------- pipelined/src/generic/mem/ram2p1rwbefix.sv | 6 +- pipelined/src/ifu/brpred/btb.sv | 2 +- pipelined/src/ifu/brpred/foldedgshare.sv | 2 +- pipelined/src/ifu/brpred/globalhistory.sv | 2 +- pipelined/src/ifu/brpred/gshare.sv | 2 +- pipelined/src/ifu/brpred/optgshare.sv | 2 +- .../ifu/brpred/speculativeglobalhistory.sv | 2 +- pipelined/src/ifu/brpred/speculativegshare.sv | 2 +- pipelined/src/ifu/brpred/twoBitPredictor.sv | 2 +- 10 files changed, 11 insertions(+), 99 deletions(-) delete mode 100644 pipelined/src/generic/mem/ram2p1r1wb.sv diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv deleted file mode 100644 index 7ac29e1d..00000000 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ /dev/null @@ -1,88 +0,0 @@ -/////////////////////////////////////////// -// ram2p1r1wb -// -// Written: Ross Thomposn -// Email: ross1728@gmail.com -// Created: February 14, 2021 -// Modified: -// -// Purpose: Behavioral model of two port SRAM. While this is synthesizable it will produce a flip flop based memory which -// behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm. -// -// -// to preload this memory we can use the following command -// in modelsim's do file. -// mem load -infile -format -// example -// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) ( - input logic clk, - input logic reset, - - // port 1 is read only - input logic [DEPTH-1:0] ra1, - output logic [WIDTH-1:0] rd1, - input logic ren1, - - // port 2 is write only - input logic [DEPTH-1:0] wa2, - input logic [WIDTH-1:0] wd2, - input logic wen2, - input logic [WIDTH-1:0] bwe2 -); - - - logic [DEPTH-1:0] ra1q, wa2q; - logic wen2q; - logic [WIDTH-1:0] wd2q; - - logic [WIDTH-1:0] mem[2**DEPTH-1:0]; - logic [WIDTH-1:0] bwe; - - - // SRAMs address busses are always registered first - // *** likely issued DH and RT 12/20/22 - // wrong enable for write port registers - // prefer to code read like ram1p1rw - // prefer not to have two-cycle write latency - // will require branch predictor changes - - flopenr #(DEPTH) ra1Reg(clk, reset, ren1, ra1, ra1q); - flopenr #(DEPTH) wa2Reg(clk, reset, ren1, wa2, wa2q); - flopr #(1) wen2Reg(clk, reset, wen2, wen2q); - flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q); - - // read port - //assign rd1 = mem[ra1q]; - always_ff @(posedge clk) - if(ren1) rd1 <= mem[ra1]; - - // write port - assign bwe = {WIDTH{wen2}} & bwe2; - always_ff @(posedge clk) - mem[wa2] <= wd2 & bwe | mem[wa2] & ~bwe; - -endmodule - - diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv index ac30343b..49354075 100644 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ b/pipelined/src/generic/mem/ram2p1rwbefix.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// -// 1 port sram. +// 2 port sram. // // Written: ross1728@gmail.com May 3, 2021 -// Basic sram with 1 read write port. +// Two port SRAM 1 read port and 1 write port. // When clk rises Addr and LineWriteData are sampled. // Following the clk edge read data is output from the sampled Addr. // Write @@ -31,7 +31,7 @@ `include "wally-config.vh" -module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) ( +module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( input logic clk, input logic ce1, ce2, input logic [$clog2(DEPTH)-1:0] ra1, diff --git a/pipelined/src/ifu/brpred/btb.sv b/pipelined/src/ifu/brpred/btb.sv index 6666c35f..5f725b83 100644 --- a/pipelined/src/ifu/brpred/btb.sv +++ b/pipelined/src/ifu/brpred/btb.sv @@ -103,7 +103,7 @@ module btb // *** optimize for byte write enables - ram2p1r1wbefix #(2**Depth, `XLEN+4) memory( + ram2p1r1wbe #(2**Depth, `XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1({InstrClass, BTBPredPCF}), .ce2(~StallE), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEN), .bwe2('1)); diff --git a/pipelined/src/ifu/brpred/foldedgshare.sv b/pipelined/src/ifu/brpred/foldedgshare.sv index 38e0fe61..2dfa4824 100644 --- a/pipelined/src/ifu/brpred/foldedgshare.sv +++ b/pipelined/src/ifu/brpred/foldedgshare.sv @@ -77,7 +77,7 @@ module foldedgshare assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]}; assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]}; - ram2p1r1wbefix #(2**depth, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(FinalIndexNextF), .rd1(TableDirPredictionF), diff --git a/pipelined/src/ifu/brpred/globalhistory.sv b/pipelined/src/ifu/brpred/globalhistory.sv index 86c48f6b..7aa86dbb 100644 --- a/pipelined/src/ifu/brpred/globalhistory.sv +++ b/pipelined/src/ifu/brpred/globalhistory.sv @@ -51,7 +51,7 @@ module globalhistory logic PCSrcM; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(GHR), .rd1(DirPredictionF), diff --git a/pipelined/src/ifu/brpred/gshare.sv b/pipelined/src/ifu/brpred/gshare.sv index ca801a27..ce189d26 100644 --- a/pipelined/src/ifu/brpred/gshare.sv +++ b/pipelined/src/ifu/brpred/gshare.sv @@ -54,7 +54,7 @@ module gshare assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), diff --git a/pipelined/src/ifu/brpred/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv index d911ec03..fae59c67 100644 --- a/pipelined/src/ifu/brpred/optgshare.sv +++ b/pipelined/src/ifu/brpred/optgshare.sv @@ -153,7 +153,7 @@ module optgshare assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]}; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableDirPredictionF), diff --git a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv index 6a4e3da0..094adca9 100644 --- a/pipelined/src/ifu/brpred/speculativeglobalhistory.sv +++ b/pipelined/src/ifu/brpred/speculativeglobalhistory.sv @@ -60,7 +60,7 @@ module speculativeglobalhistory logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(GHRNextF), .rd1(TableDirPredictionF), diff --git a/pipelined/src/ifu/brpred/speculativegshare.sv b/pipelined/src/ifu/brpred/speculativegshare.sv index 3dd66366..05753c76 100644 --- a/pipelined/src/ifu/brpred/speculativegshare.sv +++ b/pipelined/src/ifu/brpred/speculativegshare.sv @@ -70,7 +70,7 @@ module speculativegshare assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF | reset), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableDirPredictionF), diff --git a/pipelined/src/ifu/brpred/twoBitPredictor.sv b/pipelined/src/ifu/brpred/twoBitPredictor.sv index 3e41dfc4..5a04a5fc 100644 --- a/pipelined/src/ifu/brpred/twoBitPredictor.sv +++ b/pipelined/src/ifu/brpred/twoBitPredictor.sv @@ -56,7 +56,7 @@ module twoBitPredictor assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk), + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), .rd1(DirPredictionF), From 56369f76412f94b528ced51bc2b5c4ea020baecc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 24 Jan 2023 17:26:54 -0600 Subject: [PATCH 5/7] Removed old versions of gshare. --- .../src/ifu/brpred/globalHistoryPredictor.sv | 123 ----------------- .../src/ifu/brpred/oldgsharepredictor.sv | 130 ------------------ .../src/ifu/brpred/oldgsharepredictor2.sv | 130 ------------------ 3 files changed, 383 deletions(-) delete mode 100644 pipelined/src/ifu/brpred/globalHistoryPredictor.sv delete mode 100644 pipelined/src/ifu/brpred/oldgsharepredictor.sv delete mode 100644 pipelined/src/ifu/brpred/oldgsharepredictor2.sv diff --git a/pipelined/src/ifu/brpred/globalHistoryPredictor.sv b/pipelined/src/ifu/brpred/globalHistoryPredictor.sv deleted file mode 100644 index 92a3f9a1..00000000 --- a/pipelined/src/ifu/brpred/globalHistoryPredictor.sv +++ /dev/null @@ -1,123 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Global History Branch predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module globalHistoryPredictor - #(parameter int k = 10 - ) - (input logic clk, - input logic reset, - input logic StallF, StallE, - input logic [`XLEN-1:0] PCNextF, - output logic [1:0] BPPredF, - // update - input logic [4:0] InstrClassE, - input logic [4:0] BPInstrClassE, - input logic [4:0] BPInstrClassD, - input logic [4:0] BPInstrClassF, - input logic BPPredDirWrongE, - - input logic [`XLEN-1:0] PCE, - input logic PCSrcE, - input logic [1:0] UpdateBPPredE - - ); - logic [k+1:0] GHR, GHRNext; - logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; - logic PHTUpdateEN; - logic BPClassWrongNonCFI; - logic BPClassWrongCFI; - logic BPClassRightNonCFI; - logic BPClassRightBPWrong; - logic BPClassRightBPRight; - - logic [6:0] GHRMuxSel; - logic GHRUpdateEN; - logic [k-1:0] GHRLookup; - - assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; - assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & BPPredDirWrongE; - assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~BPPredDirWrongE; - - - // GHR update selection, 1 hot encoded. - assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight); - assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]); - assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0]; - assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0]; - assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight)); - assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF; - - // hoping this created a AND-OR mux. - always_comb begin - case (GHRMuxSel) - 7'b000_0001: GHRNext = GHR[k-1+2:0]; // no change - 7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update - 7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1 - 7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction - 7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2 - 7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1 - 7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update - default: GHRNext = GHR[k-1+2:0]; - endcase - end - - flopenr #(k+2) GlobalHistoryRegister(.clk(clk), - .reset(reset), - .en((GHRUpdateEN)), - .d(GHRNext), - .q(GHR)); - - // if actively updating the GHR at the time of prediction we want to us - // GHRNext as the lookup rather than GHR. - - assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0]; - assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1]; - assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0; - assign PHTUpdateEN = InstrClassE[0] & ~StallE; - - assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0]; - - // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - ram2p1r1wb #(k, 2) PHT(.clk(clk), - .reset(reset), - //.RA1(GHR[k-1:0]), - .ra1(GHRLookup), - .rd1(BPPredF), - .ren1(~StallF), - .wa2(PHTUpdateAdr), - .wd2(UpdateBPPredE), - .wen2(PHTUpdateEN), - .bwe2(2'b11)); - -endmodule diff --git a/pipelined/src/ifu/brpred/oldgsharepredictor.sv b/pipelined/src/ifu/brpred/oldgsharepredictor.sv deleted file mode 100644 index 29a62251..00000000 --- a/pipelined/src/ifu/brpred/oldgsharepredictor.sv +++ /dev/null @@ -1,130 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Gshare predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" -module oldgsharepredictor - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - output logic [1:0] DirPredictionF, - // update - input logic [4:0] InstrClassE, - input logic [4:0] BPInstrClassE, - input logic [4:0] BPInstrClassD, - input logic [4:0] BPInstrClassF, - output logic DirPredictionWrongE, - - input logic PCSrcE - - ); - logic [`BPRED_SIZE+1:0] GHR, GHRNext; - logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; - logic PHTUpdateEN; - logic BPClassWrongNonCFI; - logic BPClassWrongCFI; - logic BPClassRightNonCFI; - logic BPClassRightBPWrong; - logic BPClassRightBPRight; - logic [1:0] DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE; - - logic [6:0] GHRMuxSel; - logic GHRUpdateEN; - logic [`BPRED_SIZE-1:0] GHRLookup; - - assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; - assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE; - assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE; - - - // GHR update selection, 1 hot encoded. - assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight); - assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]); - assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0]; - assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0]; - assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight)); - assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF; - - // hoping this created a AND-OR mux. - always_comb begin - case (GHRMuxSel) - 7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change - 7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update - 7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1 - 7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction - 7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2 - 7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1 - 7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update - default: GHRNext = GHR[`BPRED_SIZE-1+2:0]; - endcase - end - - flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk), - .reset(reset), - .en((GHRUpdateEN)), - .d(GHRNext), - .q(GHR)); - - // if actively updating the GHR at the time of prediction we want to us - // GHRNext as the lookup rather than GHR. - - assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0]; - assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1]; - assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0; - assign PHTUpdateEN = InstrClassE[0] & ~StallE; - - assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; - - // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk), - .reset(reset), - //.RA1(GHR[`BPRED_SIZE-1:0]), - .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), - .rd1(DirPredictionF), - .ren1(~StallF), - .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]), - .wd2(NewDirPredictionE), - .wen2(PHTUpdateEN), - .bwe2(2'b11)); - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - // New prediction pipeline - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; - -endmodule // gsharePredictor diff --git a/pipelined/src/ifu/brpred/oldgsharepredictor2.sv b/pipelined/src/ifu/brpred/oldgsharepredictor2.sv deleted file mode 100644 index 679358e3..00000000 --- a/pipelined/src/ifu/brpred/oldgsharepredictor2.sv +++ /dev/null @@ -1,130 +0,0 @@ -/////////////////////////////////////////// -// globalHistoryPredictor.sv -// -// Written: Shreya Sanghai -// Email: ssanghai@hmc.edu -// Created: March 16, 2021 -// Modified: -// -// Purpose: Gshare predictor with parameterized global history register -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" -module oldgsharepredictor2 - (input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, - input logic FlushD, FlushE, FlushM, FlushW, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - output logic [1:0] DirPredictionF, - // update - input logic [4:0] InstrClassE, - input logic [4:0] BPInstrClassE, - input logic [4:0] BPInstrClassD, - input logic [4:0] BPInstrClassF, - output logic DirPredictionWrongE, - - input logic PCSrcE - - ); - logic [`BPRED_SIZE+1:0] GHR, GHRNext; - logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1; - logic PHTUpdateEN; - logic BPClassWrongNonCFI; - logic BPClassWrongCFI; - logic BPClassRightNonCFI; - logic BPClassRightBPWrong; - logic BPClassRightBPRight; - logic [1:0] DirPredictionD, DirPredictionE; - logic [1:0] NewDirPredictionE; - - logic [6:0] GHRMuxSel; - logic GHRUpdateEN; - logic [`BPRED_SIZE-1:0] GHRLookup; - - assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0]; - assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0]; - assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE; - assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE; - - - // GHR update selection, 1 hot encoded. - assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight); - assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0]; - assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]); - assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0]; - assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0]; - assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight)); - assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF; - - // hoping this created a AND-OR mux. - always_comb begin - case (GHRMuxSel) - 7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change - 7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update - 7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1 - 7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction - 7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2 - 7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1 - 7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update - default: GHRNext = GHR[`BPRED_SIZE-1+2:0]; - endcase - end - - flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk), - .reset(reset), - .en((GHRUpdateEN)), - .d(GHRNext), - .q(GHR)); - - // if actively updating the GHR at the time of prediction we want to us - // GHRNext as the lookup rather than GHR. - - assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0]; - assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1]; - assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0; - assign PHTUpdateEN = InstrClassE[0] & ~StallE; - - assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; - - // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk), - .reset(reset), - //.RA1(GHR[`BPRED_SIZE-1:0]), - .ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), - .rd1(DirPredictionF), - .ren1(~StallF), - .wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]), - .wd2(NewDirPredictionE), - .wen2(PHTUpdateEN), - .bwe2(2'b11)); - - // DirPrediction pipeline - flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD); - flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE); - - // New prediction pipeline - satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE)); - - assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0]; - -endmodule // gsharePredictor From ad6f7041b41fb6a05646854e585a417210f532c4 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 10:14:30 -0600 Subject: [PATCH 6/7] Fixed wrong header on optgshare.sv. Somehow it still had the old MIT license. Renamed ram2p1rwbefix.sv to ram2p1rwbe.sv --- pipelined/src/generic/mem/ram2p1rwbefix.sv | 72 ---------------------- pipelined/src/ifu/brpred/optgshare.sv | 24 +++----- 2 files changed, 10 insertions(+), 86 deletions(-) delete mode 100644 pipelined/src/generic/mem/ram2p1rwbefix.sv diff --git a/pipelined/src/generic/mem/ram2p1rwbefix.sv b/pipelined/src/generic/mem/ram2p1rwbefix.sv deleted file mode 100644 index 49354075..00000000 --- a/pipelined/src/generic/mem/ram2p1rwbefix.sv +++ /dev/null @@ -1,72 +0,0 @@ -/////////////////////////////////////////// -// 2 port sram. -// -// Written: ross1728@gmail.com May 3, 2021 -// Two port SRAM 1 read port and 1 write port. -// When clk rises Addr and LineWriteData are sampled. -// Following the clk edge read data is output from the sampled Addr. -// Write -// -// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words - -`include "wally-config.vh" - -module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( - input logic clk, - input logic ce1, ce2, - input logic [$clog2(DEPTH)-1:0] ra1, - input logic [WIDTH-1:0] wd2, - input logic [$clog2(DEPTH)-1:0] wa2, - input logic we2, - input logic [(WIDTH-1)/8:0] bwe2, - output logic [WIDTH-1:0] rd1 -); - - logic [WIDTH-1:0] mem[DEPTH-1:0]; - - // *************************************************************************** - // TRUE Smem macro - // *************************************************************************** - - // *************************************************************************** - // READ first SRAM model - // *************************************************************************** - integer i; - - // Read - always_ff @(posedge clk) - if(ce1) rd1 <= #1 mem[ra1]; - - // Write divided into part for bytes and part for extra msbs - if(WIDTH >= 8) - always @(posedge clk) - if (ce2 & we2) - for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; - - if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always @(posedge clk) - if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; - -endmodule diff --git a/pipelined/src/ifu/brpred/optgshare.sv b/pipelined/src/ifu/brpred/optgshare.sv index fae59c67..1f99cfd2 100644 --- a/pipelined/src/ifu/brpred/optgshare.sv +++ b/pipelined/src/ifu/brpred/optgshare.sv @@ -12,22 +12,18 @@ // // Copyright (C) 2021 Harvey Mudd College & Oklahoma State University // -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 // -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at // -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" From b931110f2d923161b252aae9b60bb8c5893aeb6a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 25 Jan 2023 10:17:43 -0600 Subject: [PATCH 7/7] Renamed file missed from last commit. --- pipelined/src/generic/mem/ram2p1rwbe.sv | 72 +++++++++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 pipelined/src/generic/mem/ram2p1rwbe.sv diff --git a/pipelined/src/generic/mem/ram2p1rwbe.sv b/pipelined/src/generic/mem/ram2p1rwbe.sv new file mode 100644 index 00000000..49354075 --- /dev/null +++ b/pipelined/src/generic/mem/ram2p1rwbe.sv @@ -0,0 +1,72 @@ +/////////////////////////////////////////// +// 2 port sram. +// +// Written: ross1728@gmail.com May 3, 2021 +// Two port SRAM 1 read port and 1 write port. +// When clk rises Addr and LineWriteData are sampled. +// Following the clk edge read data is output from the sampled Addr. +// Write +// +// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement. +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words + +`include "wally-config.vh" + +module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) ( + input logic clk, + input logic ce1, ce2, + input logic [$clog2(DEPTH)-1:0] ra1, + input logic [WIDTH-1:0] wd2, + input logic [$clog2(DEPTH)-1:0] wa2, + input logic we2, + input logic [(WIDTH-1)/8:0] bwe2, + output logic [WIDTH-1:0] rd1 +); + + logic [WIDTH-1:0] mem[DEPTH-1:0]; + + // *************************************************************************** + // TRUE Smem macro + // *************************************************************************** + + // *************************************************************************** + // READ first SRAM model + // *************************************************************************** + integer i; + + // Read + always_ff @(posedge clk) + if(ce1) rd1 <= #1 mem[ra1]; + + // Write divided into part for bytes and part for extra msbs + if(WIDTH >= 8) + always @(posedge clk) + if (ce2 & we2) + for(i = 0; i < WIDTH/8; i++) + if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; + + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 + always @(posedge clk) + if (ce2 & we2 & bwe2[WIDTH/8]) + mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; + +endmodule