From 1af7b8051e875533c93268bf07551f0ba19fbcc1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 22 Feb 2023 12:54:46 -0600 Subject: [PATCH 1/8] Fixed bug in basic gshare. --- src/ifu/bpred/gsharebasic.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index ccad0e3c..cb0bbe9e 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -42,7 +42,7 @@ module gsharebasic #(parameter k = 10, input logic BranchInstrE, BranchInstrM, PCSrcE ); - logic [k-1:0] IndexNextF, IndexE; + logic [k-1:0] IndexNextF, IndexM; logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; @@ -52,19 +52,19 @@ module gsharebasic #(parameter k = 10, if(TYPE == 1) begin assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; + assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; end else if(TYPE == 0) begin assign IndexNextF = GHRNext; - assign IndexE = GHRE; + assign IndexM = GHRM; end ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), - .ce1(~StallF), .ce2(~StallM & ~FlushM), + .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(DirPredictionF), - .wa2(IndexE), + .wa2(IndexM), .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallW & ~FlushW), + .we2(BranchInstrM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); From 4a9dbe4680010e659589c21e90ba251f7e57705b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 22 Feb 2023 16:11:52 -0600 Subject: [PATCH 2/8] Updated branch predictor results processing script. --- bin/parseHPMC.py | 44 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 35 insertions(+), 9 deletions(-) diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index 0cc75e10..ddf0ccb7 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -124,8 +124,9 @@ def ProcessFile(fileName): benchmarks.append((testName, opt, HPMClist)) return benchmarks -def ComputeAverage(benchmarks): +def ComputeArithmeticAverage(benchmarks): average = {} + index = 0 for (testName, opt, HPMClist) in benchmarks: for field in HPMClist: value = HPMClist[field] @@ -133,17 +134,40 @@ def ComputeAverage(benchmarks): average[field] = value else: average[field] += value + index += 1 benchmarks.append(('All', '', average)) def FormatToPlot(currBenchmark): names = [] values = [] for config in currBenchmark: - print ('config' , config) + #print ('config' , config) names.append(config[0]) values.append(config[1]) return (names, values) +def GeometricAverage(benchmarks, field): + Product = 1 + index = 0 + for (testName, opt, HPMCList) in benchmarks: + #print(HPMCList) + Product *= HPMCList[field] + index += 1 + return Product ** (1.0/index) + +def ComputeGeometricAverage(benchmarks): + fields = ['BDMR', 'BTMR', 'RASMPR', 'ClassMPR', 'ICacheMR', 'DCacheMR'] + AllAve = {} + for field in fields: + Product = 1 + index = 0 + for (testName, opt, HPMCList) in benchmarks: + #print(HPMCList) + Product *= HPMCList[field] + index += 1 + AllAve[field] = Product ** (1.0/index) + benchmarks.append(('All', '', AllAve)) + if(sys.argv[1] == '-b'): configList = [] summery = 0 @@ -152,22 +176,24 @@ if(sys.argv[1] == '-b'): sys.argv = sys.argv[1::] for config in sys.argv[2::]: benchmarks = ProcessFile(config) - ComputeAverage(benchmarks) + #ComputeArithmeticAverage(benchmarks) ComputeAll(benchmarks) + ComputeGeometricAverage(benchmarks) + print('CONFIG: %s GEO MEAN: %f' % (config, GeometricAverage(benchmarks, 'BDMR'))) configList.append((config.split('.')[0], benchmarks)) # Merge all configruations into a single list benchmarkAll = [] for (config, benchmarks) in configList: - print(config) + #print(config) for benchmark in benchmarks: (nameString, opt, dataDict) = benchmark - print("BENCHMARK") - print(nameString) - print(opt) - print(dataDict) + #print("BENCHMARK") + #print(nameString) + #print(opt) + #print(dataDict) benchmarkAll.append((nameString, opt, config, dataDict)) - print('ALL!!!!!!!!!!') + #print('ALL!!!!!!!!!!') #for bench in benchmarkAll: # print('BENCHMARK') # print(bench) From f0d32a745a9c75a57323fa7a0808302ffba76183 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 22 Feb 2023 22:08:00 -0600 Subject: [PATCH 3/8] updates to bp result parsing script. --- bin/parseHPMC.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/parseHPMC.py b/bin/parseHPMC.py index ddf0ccb7..0156dc9f 100755 --- a/bin/parseHPMC.py +++ b/bin/parseHPMC.py @@ -179,7 +179,7 @@ if(sys.argv[1] == '-b'): #ComputeArithmeticAverage(benchmarks) ComputeAll(benchmarks) ComputeGeometricAverage(benchmarks) - print('CONFIG: %s GEO MEAN: %f' % (config, GeometricAverage(benchmarks, 'BDMR'))) + #print('CONFIG: %s GEO MEAN: %f' % (config, GeometricAverage(benchmarks, 'BDMR'))) configList.append((config.split('.')[0], benchmarks)) # Merge all configruations into a single list @@ -212,7 +212,7 @@ if(sys.argv[1] == '-b'): size = len(benchmarkDict) index = 1 if(summery == 0): - print('Number of plots', size) + #print('Number of plots', size) for benchmarkName in benchmarkDict: currBenchmark = benchmarkDict[benchmarkName] (names, values) = FormatToPlot(currBenchmark) @@ -249,7 +249,7 @@ if(sys.argv[1] == '-b'): print(dct) for cat in dct: (x, y) = dct[cat] - plt.scatter(x, y, label=cat) + plt.scatter(x, y, label='k') plt.plot(x, y) plt.ylabel('Prediction Accuracy') plt.xlabel('Size (b or k)') From ed91fc5ce359343a2dd8c65606bc7149afd5987b Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 23 Feb 2023 14:33:32 -0600 Subject: [PATCH 4/8] Renamed PCPredX to BTAX. --- src/ifu/bpred/bpred.sv | 15 +++++++-------- src/ifu/bpred/btb.sv | 32 ++++++++++++++++---------------- 2 files changed, 23 insertions(+), 24 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 71077596..e29ef3ef 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -73,7 +73,7 @@ module bpred ( logic [1:0] DirPredictionF; logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD; - logic [`XLEN-1:0] PredPCF, RASPCF; + logic [`XLEN-1:0] BTAF, RASPCF; logic PredictionPCWrongE; logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; logic [3:0] InstrClassD; @@ -90,7 +90,7 @@ module bpred ( logic RASTargetWrongE; logic JumpOrTakenBranchE; - logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; + logic [`XLEN-1:0] BTAD, BTAE, RASPCD, RASPCE; // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. @@ -142,7 +142,7 @@ module bpred ( btb #(`BTB_SIZE) TargetPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, - .PredPCF, + .BTAF, .BTAD, .BTBPredInstrClassF, .PredictionInstrClassWrongM, .IEUAdrE, .IEUAdrM, @@ -189,7 +189,7 @@ module bpred ( .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .RASPCF, .PCLinkE); - assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; + assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTAF; assign InstrClassD[0] = BranchD; assign InstrClassD[1] = JumpD ; @@ -249,19 +249,18 @@ module bpred ( // 3. target ras (ras target wrong / class[2]) // 4. direction (br dir wrong / class[0]) - // Unforuantely we can't relay on PCD to infer the correctness of the BTB or RAS because the class prediction + // Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE; + assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1]; flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); - flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); - flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE); + flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE); flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 8e2d0e25..2bb00671 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -31,19 +31,20 @@ `include "wally-config.vh" module btb #(parameter Depth = 10 ) ( - input logic clk, - input logic reset, - input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages - output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC + input logic clk, + input logic reset, + input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages + output logic [`XLEN-1:0] BTAF, // BTB's guess at PC + output logic [`XLEN-1:0] BTAD, output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class // update - input logic PredictionInstrClassWrongM, // BTB's instruction class guess was wrong - input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb - input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb - input logic [3:0] InstrClassD, // Instruction class to insert into btb - input logic [3:0] InstrClassE, // Instruction class to insert into btb - input logic [3:0] InstrClassM // Instruction class to insert into btb + input logic PredictionInstrClassWrongM, // BTB's instruction class guess was wrong + input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassD, // Instruction class to insert into btb + input logic [3:0] InstrClassE, // Instruction class to insert into btb + input logic [3:0] InstrClassM // Instruction class to insert into btb ); logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex, PCMIndex; @@ -51,7 +52,6 @@ module btb #(parameter Depth = 10 ) ( logic MatchF, MatchD, MatchE, MatchM, MatchNextX, MatchXF; logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; - logic [`XLEN-1:0] PredPCD; logic UpdateEn; // hashing function for indexing the PC @@ -78,14 +78,14 @@ module btb #(parameter Depth = 10 ) ( flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} : - MatchD ? {InstrClassD, PredPCD} : + assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, BTAF} : + MatchD ? {InstrClassD, BTAD} : MatchE ? {InstrClassE, IEUAdrE} : {InstrClassM, IEUAdrM} ; flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF); - assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF}; + assign {BTBPredInstrClassF, BTAF} = MatchXF ? ForwardBTBPredictionF : {TableBTBPredictionF}; assign UpdateEn = |InstrClassM | PredictionInstrClassWrongM; @@ -95,6 +95,6 @@ module btb #(parameter Depth = 10 ) ( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF), .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(UpdateEn), .bwe2('1)); - flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, PredPCF, PredPCD); + flopenrc #(`XLEN) BTBD(clk, reset, FlushD, ~StallD, BTAF, BTAD); endmodule From 195343c84fe607cdd5ff530afbe79ef995c7f121 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 23 Feb 2023 14:39:31 -0600 Subject: [PATCH 5/8] Added if generate around bp logic only used with performance counters. --- src/ifu/bpred/bpred.sv | 44 ++++++++++++++++++++++++------------------ 1 file changed, 25 insertions(+), 19 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index e29ef3ef..06840309 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -88,9 +88,8 @@ module bpred ( logic BTBTargetWrongE; logic RASTargetWrongE; - logic JumpOrTakenBranchE; - logic [`XLEN-1:0] BTAD, BTAE, RASPCD, RASPCE; + logic [`XLEN-1:0] BTAD; // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. @@ -243,26 +242,33 @@ module bpred ( if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); else assign NextValidPCE = PCE; - // performance counters - // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now - // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) - // 3. target ras (ras target wrong / class[2]) - // 4. direction (br dir wrong / class[0]) - // Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction - // could be wrong or the fall through address selected for branch predict not taken. - // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of - // both without the above inaccuracies. - assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE; - assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; + if(`ZICOUNTERS_SUPPORTED) begin + logic JumpOrTakenBranchE; + logic [`XLEN-1:0] BTAE, RASPCD, RASPCE; + // performance counters + // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now + // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) + // 3. target ras (ras target wrong / class[2]) + // 4. direction (br dir wrong / class[0]) - assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1]; - - flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); + // Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction + // could be wrong or the fall through address selected for branch predict not taken. + // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of + // both without the above inaccuracies. + assign BTBPredPCWrongE = (BTAE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE; + assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; - flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE); + assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1]; + + flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); - flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); - flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); + flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, BTAD, BTAE); + + flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); + flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); + end else begin + assign {BTBPredPCWrongE, RASPredPCWrongE, JumpOrTakenBranchM} = '0; + end endmodule From 2fff070b1dbd21dd6470c5452d2a15ca3549edf9 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 23 Feb 2023 14:44:15 -0600 Subject: [PATCH 6/8] Moved more branch predictor logic into the performance counter block. --- src/ifu/bpred/bpred.sv | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 06840309..8aca9f43 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -78,7 +78,7 @@ module bpred ( logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; logic [3:0] InstrClassD; logic [3:0] InstrClassE; - logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; + logic DirPredictionWrongE; logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; @@ -200,9 +200,7 @@ module bpred ( flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); // branch predictor - flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, AnyWrongPredInstrClassE}, - {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM}); + flopenrc #(1) BPClassWrongRegM(clk, reset, FlushM, ~StallM, AnyWrongPredInstrClassE, PredictionInstrClassWrongM); // pipeline the class flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); @@ -242,10 +240,10 @@ module bpred ( if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); else assign NextValidPCE = PCE; - if(`ZICOUNTERS_SUPPORTED) begin logic JumpOrTakenBranchE; logic [`XLEN-1:0] BTAE, RASPCD, RASPCE; + logic BTBPredPCWrongE, RASPredPCWrongE; // performance counters // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) @@ -267,8 +265,12 @@ module bpred ( flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); + flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, + {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE}, + {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM}); + end else begin - assign {BTBPredPCWrongE, RASPredPCWrongE, JumpOrTakenBranchM} = '0; + assign {BTBPredPCWrongM, RASPredPCWrongM, JumpOrTakenBranchM} = '0; end endmodule From 70f7f593321f3a0dbec7b1942477d03b3da47f2d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 23 Feb 2023 14:44:15 -0600 Subject: [PATCH 7/8] Moved more branch predictor logic into the performance counter block. --- src/ifu/bpred/bpred.sv | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 06840309..8aca9f43 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -78,7 +78,7 @@ module bpred ( logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; logic [3:0] InstrClassD; logic [3:0] InstrClassE; - logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; + logic DirPredictionWrongE; logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; @@ -200,9 +200,7 @@ module bpred ( flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); // branch predictor - flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM, - {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, AnyWrongPredInstrClassE}, - {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM}); + flopenrc #(1) BPClassWrongRegM(clk, reset, FlushM, ~StallM, AnyWrongPredInstrClassE, PredictionInstrClassWrongM); // pipeline the class flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD); @@ -242,10 +240,10 @@ module bpred ( if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE); else assign NextValidPCE = PCE; - if(`ZICOUNTERS_SUPPORTED) begin logic JumpOrTakenBranchE; logic [`XLEN-1:0] BTAE, RASPCD, RASPCE; + logic BTBPredPCWrongE, RASPredPCWrongE; // performance counters // 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now // 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal) @@ -267,8 +265,12 @@ module bpred ( flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD); flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE); + flopenrc #(3) BPPredWrongRegM(clk, reset, FlushM, ~StallM, + {DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE}, + {DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM}); + end else begin - assign {BTBPredPCWrongE, RASPredPCWrongE, JumpOrTakenBranchM} = '0; + assign {BTBPredPCWrongM, RASPredPCWrongM, JumpOrTakenBranchM} = '0; end endmodule From 500764f97b960feff52f54f8c4f4b978a8e1cdea Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 23 Feb 2023 15:15:14 -0600 Subject: [PATCH 8/8] Branch predictor cleanup. --- src/ifu/bpred/bpred.sv | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 8aca9f43..ec974d14 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -149,25 +149,28 @@ module bpred ( // the branch predictor needs a compact decoding of the instruction class. if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode - logic [4:0] CompressedOpcF; logic [3:0] InstrClassF; logic cjal, cj, cjr, cjalr, CJumpF, CBranchF; logic JumpF, BranchF; - - assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; - assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; - assign cj = CompressedOpcF == 5'h0d; - assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; - assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; - assign CJumpF = cjal | cj | cjr | cjalr; - assign CBranchF = CompressedOpcF[4:1] == 4'h7; + if(`C_SUPPORTED) begin + logic [4:0] CompressedOpcF; + assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; + assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32; + assign cj = CompressedOpcF == 5'h0d; + assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign CJumpF = cjal | cj | cjr | cjalr; + assign CBranchF = CompressedOpcF[4:1] == 4'h7; + end else begin + assign {cjal, cj, cjr, cjalr, CJumpF, CBranchF} = '0; + end assign JumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F; assign BranchF = PostSpillInstrRawF[6:0] == 7'h63; assign InstrClassF[0] = BranchF | (`C_SUPPORTED & CBranchF); - assign InstrClassF[1] = JumpF | (`C_SUPPORTED & (cjal | cj | cj | cjalr)); + assign InstrClassF[1] = JumpF | (`C_SUPPORTED & (CJumpF)); assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5 (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));