From b7b082482f2d0422578f4fbcf5922097e1e70c17 Mon Sep 17 00:00:00 2001
From: David Harris <david_harris@hmc.edu>
Date: Mon, 19 Sep 2022 00:30:30 -0700
Subject: [PATCH] Division working again for radix 2 with unified OTFC

---
 pipelined/src/fpu/fdivsqrtiter.sv   | 2 +-
 pipelined/src/fpu/fdivsqrtstage4.sv | 3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrtiter.sv b/pipelined/src/fpu/fdivsqrtiter.sv
index 25bbdbb5..e2346b3e 100644
--- a/pipelined/src/fpu/fdivsqrtiter.sv
+++ b/pipelined/src/fpu/fdivsqrtiter.sv
@@ -104,7 +104,7 @@ module fdivsqrtiter(
   logic [1:0] initCSqrt, initCDiv2, initCDiv4, initCUpper;
   assign initCSqrt = 2'b11;
   assign initCDiv2 = 2'b10;
-  assign initCDiv4 = 2'b00;
+  assign initCDiv4 = 2'b10; // *** not sure why this works; seems like it should be 00 for initializing to -4
   assign initCUpper = SqrtE ? initCSqrt : (`RADIX == 4) ? initCDiv4 : initCDiv2;
   assign initC = {initCUpper, {`DIVb{1'b0}}};
 
diff --git a/pipelined/src/fpu/fdivsqrtstage4.sv b/pipelined/src/fpu/fdivsqrtstage4.sv
index 548a4af6..298854f4 100644
--- a/pipelined/src/fpu/fdivsqrtstage4.sv
+++ b/pipelined/src/fpu/fdivsqrtstage4.sv
@@ -53,7 +53,6 @@ module fdivsqrtstage4 (
   logic [`DIVb+3:0] AddIn;
   logic [4:0] Smsbs;
   logic CarryIn;
-
   assign CNext = {2'b11, C[`DIVb+1:2]};
 
   // Qmient Selection logic
@@ -86,6 +85,8 @@ module fdivsqrtstage4 (
  
   otfc4 otfc4(.q, .Q, .QM, .QNext, .QMNext);
   sotfc4 sotfc4(.s(q), .Sqrt(SqrtM), .C(CNext[`DIVb:0]), .S, .SM, .SNext, .SMNext);
+
+  assign qn = 0; // unused for radix 4
 endmodule