From b79021a73ef9499a8b58e1cc4e77c9961ee7037c Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Tue, 12 Oct 2021 09:45:02 -0700 Subject: [PATCH] lint warnings fixed --- wally-pipelined/src/fpu/divconv.sv | 2 +- wally-pipelined/src/fpu/fctrl.sv | 4 ++-- wally-pipelined/src/fpu/fcvt.sv | 20 ++++++++++---------- wally-pipelined/src/fpu/fhazard.sv | 6 +++--- wally-pipelined/src/fpu/fma.sv | 20 ++++++++++---------- wally-pipelined/src/fpu/fpdiv.sv | 4 ++-- wally-pipelined/src/fpu/rounder_div.sv | 2 +- wally-pipelined/src/fpu/unpacking.sv | 2 +- 8 files changed, 30 insertions(+), 30 deletions(-) diff --git a/wally-pipelined/src/fpu/divconv.sv b/wally-pipelined/src/fpu/divconv.sv index 271cd69a..7fbafeb1 100755 --- a/wally-pipelined/src/fpu/divconv.sv +++ b/wally-pipelined/src/fpu/divconv.sv @@ -68,7 +68,7 @@ module divconv ( mux2 #(64) mxA ({64'hFFFF_FFFF_FFFF_F9FF}, {64'hFFFF_FF3F_FFFF_FFFF}, P, qm_const); // CPA (from CSA)/Remainder addition/subtraction - assign {cout1, mul_out} = (mcand*mplier) + constant + muxr_out; + assign {cout1, mul_out} = (mcand*mplier) + constant + {127'b0, muxr_out}; // Assuming [1,2) - q1 assign {cout2, q_out1} = regb_out + q_const; diff --git a/wally-pipelined/src/fpu/fctrl.sv b/wally-pipelined/src/fpu/fctrl.sv index f5c15e9d..6fd29a2b 100755 --- a/wally-pipelined/src/fpu/fctrl.sv +++ b/wally-pipelined/src/fpu/fctrl.sv @@ -69,7 +69,7 @@ module fctrl ( 2'b01: ControlsD = `FCTRLW'b1_0_11_010_011_00_0_0; // fcvt.s.wu 2'b10: ControlsD = `FCTRLW'b1_0_11_100_011_00_0_0; // fcvt.s.l 2'b11: ControlsD = `FCTRLW'b1_0_11_110_011_00_0_0; // fcvt.s.lu - default: ControlsD = `FCTRLW'b0_0_00_0000_000_00_0_1; // non-implemented instruction + default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction endcase 7'b1100000: case(Rs2D[1:0]) 2'b00: ControlsD = `FCTRLW'b0_1_11_001_011_11_0_0; // fcvt.w.s @@ -98,7 +98,7 @@ module fctrl ( //7'b0100001: ControlsD = `FCTRLW'b1_0_11_000_100_00_0_0; // fcvt.d.s default: ControlsD = `FCTRLW'b0_0_00_000_100_00_0_1; // non-implemented instruction endcase - default: ControlsD = `FCTRLW'b0_0_000_000_000_00_0_1; // non-implemented instruction + default: ControlsD = `FCTRLW'b0_0_00_000_000_00_0_1; // non-implemented instruction endcase // unswizzle control bits diff --git a/wally-pipelined/src/fpu/fcvt.sv b/wally-pipelined/src/fpu/fcvt.sv index 17da8030..479da90c 100644 --- a/wally-pipelined/src/fpu/fcvt.sv +++ b/wally-pipelined/src/fpu/fcvt.sv @@ -68,7 +68,7 @@ module fcvt ( assign Bits = Res64 ? 8'd64 : 8'd32; // calulate the unbiased exponent - assign ExpVal = XExpE - BiasE + XDenormE; + assign ExpVal = {1'b0,XExpE} - {1'b0,BiasE} + {12'b0, XDenormE}; //////////////////////////////////////////////////////// @@ -84,11 +84,11 @@ module fcvt ( always_comb begin i = 0; while (~PosInt[64-1-i] && i < `XLEN) i = i+1; // search for leading one - LZResP = i+1; // compute shift count + LZResP = i[5:0]+1; // compute shift count end // if no one was found set to zero otherwise calculate the exponent - assign TmpExp = i==`XLEN ? 0 : FmtE ? 1023 + SubBits - LZResP : 127 + SubBits - LZResP; + assign TmpExp = i==`XLEN ? 0 : FmtE ? 11'd1023 + {3'b0, SubBits} - {5'b0, LZResP} : 11'd127 + {3'b0, SubBits} - {5'b0, LZResP}; @@ -97,13 +97,13 @@ module fcvt ( // select the shift value and amount based on operation (to fp or int) - assign ShiftCnt = FOpCtrlE[0] ? ExpVal : LZResP; - assign ShiftVal = FOpCtrlE[0] ? {{64-2{1'b0}}, XManE} : {PosInt, 52'b0}; + assign ShiftCnt = FOpCtrlE[0] ? ExpVal : {7'b0, LZResP}; + assign ShiftVal = FOpCtrlE[0] ? {{64-1{1'b0}}, XManE} : {PosInt, 52'b0}; // if shift = -1 then shift one bit right for gaurd bit (right shifting twice never rounds) // if the shift is negitive add a bit for sticky bit calculation // otherwise shift left - assign ShiftedManTmp = &ShiftCnt ? {{64-1{1'b0}}, XManE[52:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt; + assign ShiftedManTmp = &ShiftCnt ? {{64{1'b0}}, XManE[52:1]} : ShiftCnt[12] ? {{64+51{1'b0}}, ~XZeroE} : ShiftVal << ShiftCnt; // truncate the shifted mantissa assign ShiftedMan = ShiftedManTmp[64+51:50]; @@ -135,8 +135,8 @@ module fcvt ( assign Plus1 = CalcPlus1 & (Guard|Round|Sticky)&~(XZeroE&FOpCtrlE[0]); // round the shifted mantissa - assign RoundedTmp = ShiftedMan[64+1:2] + Plus1; - assign {ResExp, ResFrac} = FmtE ? {TmpExp, ShiftedMan[64+1:14]} + Plus1 : {{TmpExp, ShiftedMan[64+1:43]} + Plus1, 29'b0} ; + assign RoundedTmp = ShiftedMan[64+1:2] + {64'b0, Plus1}; + assign {ResExp, ResFrac} = FmtE ? {TmpExp, ShiftedMan[64+1:14]} + {62'b0, Plus1} : {{TmpExp, ShiftedMan[64+1:43]} + {33'b0,Plus1}, 29'b0} ; // fit the rounded result into the appropriate size and take the 2's complement if needed assign Rounded = Res64 ? XSgnE&FOpCtrlE[0] ? -RoundedTmp[63:0] : RoundedTmp[63:0] : @@ -148,10 +148,10 @@ module fcvt ( // check if the result overflows - assign Of = (~XSgnE&($signed(ShiftCnt) >= $signed(Bits))) | (~XSgnE&RoundSgn&~FOpCtrlE[1]) | (RoundMSB&(ShiftCnt==(Bits-1))) | (~XSgnE&XInfE) | XNaNE; + assign Of = (~XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (~XSgnE&RoundSgn&~FOpCtrlE[1]) | (RoundMSB&(ShiftCnt==({{5{Bits[7]}}, Bits}-1))) | (~XSgnE&XInfE) | XNaNE; // check if the result underflows (this calculation changes if the result is signed or unsigned) - assign Uf = FOpCtrlE[1] ? XSgnE&~XZeroE | (XSgnE&XInfE) | (XSgnE&~XZeroE&(~ShiftCnt[12]|CalcPlus1)) | (ShiftCnt[12]&Plus1) : (XSgnE&XInfE) | (XSgnE&($signed(ShiftCnt) >= $signed(Bits))) | (XSgnE&~RoundSgn&~ShiftCnt[12]); // assign CvtIntRes = (XSgnE | ShiftCnt[12]) ? {64{1'b0}} : (ShiftCnt >= 64) ? {64{1'b1}} : Rounded; + assign Uf = FOpCtrlE[1] ? XSgnE&~XZeroE | (XSgnE&XInfE) | (XSgnE&~XZeroE&(~ShiftCnt[12]|CalcPlus1)) | (ShiftCnt[12]&Plus1) : (XSgnE&XInfE) | (XSgnE&($signed(ShiftCnt) >= $signed({{5{Bits[7]}}, Bits}))) | (XSgnE&~RoundSgn&~ShiftCnt[12]); // assign CvtIntRes = (XSgnE | ShiftCnt[12]) ? {64{1'b0}} : (ShiftCnt >= 64) ? {64{1'b1}} : Rounded; // calculate the result's sign assign SgnRes = ~FOpCtrlE[2] & FOpCtrlE[0]; diff --git a/wally-pipelined/src/fpu/fhazard.sv b/wally-pipelined/src/fpu/fhazard.sv index e5331737..d515b24d 100644 --- a/wally-pipelined/src/fpu/fhazard.sv +++ b/wally-pipelined/src/fpu/fhazard.sv @@ -45,7 +45,7 @@ module fhazard( // if the needed value is in the memory stage - input 1 if ((Adr1E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 3'b11) FForwardXE = 2'b10; // choose FResM + if(FResultSelM == 2'b11) FForwardXE = 2'b10; // choose FResM else FStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr1E == RdW) & FRegWriteW) FForwardXE = 2'b01; // choose FPUResult64W @@ -54,7 +54,7 @@ module fhazard( // if the needed value is in the memory stage - input 2 if ((Adr2E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 3'b11) FForwardYE = 2'b10; // choose FResM + if(FResultSelM == 2'b11) FForwardYE = 2'b10; // choose FResM else FStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr2E == RdW) & FRegWriteW) FForwardYE = 2'b01; // choose FPUResult64W @@ -63,7 +63,7 @@ module fhazard( // if the needed value is in the memory stage - input 3 if ((Adr3E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) - if(FResultSelM == 3'b11) FForwardZE = 2'b10; // choose FResM + if(FResultSelM == 2'b11) FForwardZE = 2'b10; // choose FResM else FStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr3E == RdW) & FRegWriteW) FForwardZE = 2'b01; // choose FPUResult64W diff --git a/wally-pipelined/src/fpu/fma.sv b/wally-pipelined/src/fpu/fma.sv index 52b7d741..5dcfe883 100644 --- a/wally-pipelined/src/fpu/fma.sv +++ b/wally-pipelined/src/fpu/fma.sv @@ -179,7 +179,7 @@ module expadd( assign XExpVal = XDenormE ? Denorm : XExpE; assign YExpVal = YDenormE ? Denorm : YExpE; // kill the exponent if the product is zero - either X or Y is 0 - assign ProdExpE = (XExpVal + YExpVal - `NE'h3ff)&{`NE+2{~(XZeroE|YZeroE)}}; + assign ProdExpE = ({2'b0, XExpVal} + {2'b0, YExpVal} - {2'b0, `NE'h3ff})&{`NE+2{~(XZeroE|YZeroE)}}; endmodule @@ -251,7 +251,7 @@ module align( // - positive means the product is larger, so shift Z right // - Denormal numbers have a diffrent exponent value depending on the precision assign ZExpVal = ZDenormE ? Denorm : ZExpE; - assign AlignCnt = ProdExpE - ZExpVal + (`NF+3); + assign AlignCnt = ProdExpE - {2'b0, ZExpVal} + (`NF+3); // Defualt Addition without shifting // | 54'b0 | 106'b(product) | 2'b0 | @@ -266,7 +266,7 @@ module align( // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | - if ($signed(AlignCnt) < $signed(0)) begin + if ($signed(AlignCnt) < $signed(13'b0)) begin KillProdE = 1; ZManShifted = ZManPreShifted; AddendStickyE = ~(XZeroE|YZeroE); @@ -274,7 +274,7 @@ module align( // If the Addend is shifted right // | 54'b0 | 106'b(product) | 2'b0 | // | addnend | - end else if ($signed(AlignCnt)<=$signed(3*`NF+4)) begin + end else if ($signed(AlignCnt)<=$signed(13'd3*13'd`NF+13'd4)) begin KillProdE = 0; ZManShifted = ZManPreShifted >> AlignCnt; AddendStickyE = |(ZManShifted[`NF-1:0]); @@ -337,7 +337,7 @@ module add( // Do the addition // - calculate a positive and negitive sum in parallel - assign PreSum = AlignedAddendInv + {ProdManKilled, 2'b0}; + assign PreSum = AlignedAddendInv + {55'b0, ProdManKilled, 2'b0}; assign NegPreSum = AlignedAddendE + NegProdManKilled; // Is the sum negitive @@ -387,7 +387,7 @@ module posloa( logic [8:0] i; always_comb begin i = 0; - while (~pf[3*`NF+6-i] && $unsigned(i) <= $unsigned(3*`NF+6)) i = i+1; // search for leading one + while (~pf[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one PCnt = i; end @@ -413,7 +413,7 @@ module negloa( logic [8:0] i; always_comb begin i = 0; - while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(3*`NF+6)) i = i+1; // search for leading one + while (~f[3*`NF+6-i] && $unsigned(i) <= $unsigned(9'd3*9'd`NF+9'd6)) i = i+1; // search for leading one NCnt = i; end @@ -594,8 +594,8 @@ module resultselect( ((FrmM[1:0]==2'b01) | (FrmM[1:0]==2'b10&~ResultSgn) | (FrmM[1:0]==2'b11&ResultSgn)) ? {{32{1'b1}}, ResultSgn, 8'hfe, {23{1'b1}}} : {{32{1'b1}}, ResultSgn, 8'hff, 23'b0}; assign InvalidResult = FmtM ? {ResultSgn, {`NE{1'b1}}, 1'b1, {`NF-1{1'b0}}} : {{32{1'b1}}, ResultSgn, 8'hff, 1'b1, 22'b0}; - assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - (Minus1&AddendStickyM) + (Plus1&AddendStickyM)} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}}; - assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + (CalcPlus1&(AddendStickyM|FrmM[1])) : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}}; + assign KillProdResult = FmtM ? {ResultSgn, {ZExpM, ZManM[`NF-1:0]} - {62'b0, (Minus1&AddendStickyM) + (Plus1&AddendStickyM)}} : {{32{1'b1}}, ResultSgn, {ZExpM[`NE-1],ZExpM[6:0], ZManM[51:29]} - {30'b0, (Minus1&AddendStickyM)} + {30'b0, (Plus1&AddendStickyM)}}; + assign UnderflowResult = FmtM ? {ResultSgn, {`FLEN-1{1'b0}}} + {63'b0,(CalcPlus1&(AddendStickyM|FrmM[1]))} : {{32{1'b1}}, {ResultSgn, 31'b0} + {31'b0, (CalcPlus1&(AddendStickyM|FrmM[1]))}}; assign FMAResM = XNaNM ? XNaNResult : YNaNM ? YNaNResult : ZNaNM ? ZNaNResult : @@ -666,7 +666,7 @@ module normalize( assign UfSticky = AddendStickyM | NormSumSticky; // Determine sum's exponent - assign SumExp = (SumExpTmp+LZAPlus1+(~|SumExpTmp&SumShifted[3*`NF+6])) & {`NE+2{~(SumZero|ResultDenorm)}}; + assign SumExp = (SumExpTmp+{12'b0, LZAPlus1}+{12'b0, ~|SumExpTmp&SumShifted[3*`NF+6]}) & {`NE+2{~(SumZero|ResultDenorm)}}; // recalculate if the result is denormalized assign ResultDenorm = PreResultDenorm&~SumShifted[3*`NF+6]&~SumShifted[3*`NF+7]; diff --git a/wally-pipelined/src/fpu/fpdiv.sv b/wally-pipelined/src/fpu/fpdiv.sv index 0a937b5b..f0f81bd2 100755 --- a/wally-pipelined/src/fpu/fpdiv.sv +++ b/wally-pipelined/src/fpu/fpdiv.sv @@ -90,11 +90,11 @@ module fpdiv ( assign exp2 = {2'b0, Float2[62:52]}; assign bias = {3'h0, 10'h3FF}; // Divide exponent - assign {exp_cout1, open, exp_diff} = exp1 - exp2 + bias; + assign {exp_cout1, open, exp_diff} = {2'b0, exp1} - {2'b0, exp2} + {2'b0, bias}; // Sqrt exponent (check if exponent is odd) assign exp_odd = Float1[52] ? 1'b0 : 1'b1; - assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + exp_odd; + assign {exp_cout2, exp_sqrt} = {1'b0, exp1} + {4'h0, 10'h3ff} + {13'b0, exp_odd}; // Choose correct exponent assign expF = op_type ? exp_sqrt[13:1] : exp_diff; diff --git a/wally-pipelined/src/fpu/rounder_div.sv b/wally-pipelined/src/fpu/rounder_div.sv index 1d2ff1cc..1eb50644 100755 --- a/wally-pipelined/src/fpu/rounder_div.sv +++ b/wally-pipelined/src/fpu/rounder_div.sv @@ -113,7 +113,7 @@ module rounder_div ( // 1.) we choose any qm0, qp0, q0 (since we shift mant) // 2.) we choose qp and we overflow (for RU) assign exp_ovf = |{qp[62:40], (qp[39:11] & {29{~P}})}; - assign Texp = exp_diff - {{13{1'b0}}, ~q1[63]} + {{13{1'b0}}, mux_mant[1]&qp1[63]&~exp_ovf}; + assign Texp = exp_diff - {{12{1'b0}}, ~q1[63]} + {{12{1'b0}}, mux_mant[1]&qp1[63]&~exp_ovf}; // Overflow only occurs for double precision, if Texp[10] to Texp[0] are // all ones. To encourage sharing with single precision overflow detection, diff --git a/wally-pipelined/src/fpu/unpacking.sv b/wally-pipelined/src/fpu/unpacking.sv index 3f80ee03..bc903044 100644 --- a/wally-pipelined/src/fpu/unpacking.sv +++ b/wally-pipelined/src/fpu/unpacking.sv @@ -75,6 +75,6 @@ module unpacking ( assign YZeroE = YExpZero & YFracZero; assign ZZeroE = ZExpZero & ZFracZero; - assign BiasE = 13'h3ff; // always use 1023 because exponents are unpacked to double precision + assign BiasE = 11'h3ff; // always use 1023 because exponents are unpacked to double precision endmodule \ No newline at end of file