diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index be67c99b..307c77b2 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit be67c99bd461742aa1c100bcc0732657faae2230
+Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86
diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv
index 931684e9..a08e4ff5 100644
--- a/pipelined/src/ppa/ppa.sv
+++ b/pipelined/src/ppa/ppa.sv
@@ -733,11 +733,47 @@ module ppa_flopenr_128 #(parameter WIDTH = 128) (
     else if (en) q <= #1 d;
 endmodule
 
-module csa #(parameter WIDTH=8) (
+module ppa_csa_8 #(parameter WIDTH = 8) (
   input logic [WIDTH-1:0] a, b, c,
 	output logic [WIDTH-1:0] sum, carry);
 
    assign sum = a ^ b ^ c;
    assign carry = (a & (b | c)) | (b & c);
 
-endmodule // csa
\ No newline at end of file
+endmodule
+
+module ppa_csa_16 #(parameter WIDTH = 16) (
+  input logic [WIDTH-1:0] a, b, c,
+	output logic [WIDTH-1:0] sum, carry);
+
+   assign sum = a ^ b ^ c;
+   assign carry = (a & (b | c)) | (b & c);
+
+endmodule
+
+module ppa_csa_32 #(parameter WIDTH = 32) (
+  input logic [WIDTH-1:0] a, b, c,
+	output logic [WIDTH-1:0] sum, carry);
+
+   assign sum = a ^ b ^ c;
+   assign carry = (a & (b | c)) | (b & c);
+
+endmodule
+
+module ppa_csa_64 #(parameter WIDTH = 64) (
+  input logic [WIDTH-1:0] a, b, c,
+	output logic [WIDTH-1:0] sum, carry);
+
+   assign sum = a ^ b ^ c;
+   assign carry = (a & (b | c)) | (b & c);
+
+endmodule
+
+module ppa_csa_128 #(parameter WIDTH = 128) (
+  input logic [WIDTH-1:0] a, b, c,
+	output logic [WIDTH-1:0] sum, carry);
+
+   assign sum = a ^ b ^ c;
+   assign carry = (a & (b | c)) | (b & c);
+
+endmodule
\ No newline at end of file
diff --git a/synthDC/ppaAnalyze.py b/synthDC/ppaAnalyze.py
index dd3fcf23..101e278f 100755
--- a/synthDC/ppaAnalyze.py
+++ b/synthDC/ppaAnalyze.py
@@ -292,6 +292,6 @@ def plotPPA(mod, freq=None):
 # writeCSV()
 # makeCoefTable()
 
-freqPlot('decoder', 8)
+freqPlot('flopr', 128)
 
-plotPPA('decoder')
\ No newline at end of file
+# plotPPA('add')
\ No newline at end of file
diff --git a/synthDC/ppaSynth.py b/synthDC/ppaSynth.py
index f939a8e3..4cf04537 100755
--- a/synthDC/ppaSynth.py
+++ b/synthDC/ppaSynth.py
@@ -44,13 +44,13 @@ def getData():
 allSynths = getData()
 arr = [-40, -20, -8, -6, -4, -2, 0, 2, 4, 6, 8, 10, 14, 20, 40]
 
-widths = [8]
-modules = ['decoder']
+widths = [32, 64, 128]
+modules = ['flopr']
 tech = 'sky90'
 LoT = []
 
-## initial sweep to get estimate of min delay
-# freqs = ['17200']
+# # # initial sweep to get estimate of min delay
+# freqs = ['7500']
 # for module in modules:
 #     for width in widths:
 #         for freq in freqs: