diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 5e5524a2..1488e528 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -91,9 +91,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 `define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 56'h80000000 -`define RAM_RANGE 56'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h80000000 +`define UNCORE_RAM_RANGE 56'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 56'h80000000 `define EXT_MEM_RANGE 56'h07FFFFFF diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 88d8f559..58e425b3 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -94,9 +94,9 @@ `define BOOTROM_BASE 56'h00001000 `define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b0 -`define RAM_BASE 56'h100000000 -`define RAM_RANGE 56'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b0 +`define UNCORE_RAM_BASE 56'h100000000 +`define UNCORE_RAM_RANGE 56'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b1 `define EXT_MEM_BASE 56'h80000000 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 8316c849..19098a0a 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -92,9 +92,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 34'h00001000 `define BOOTROM_RANGE 34'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 34'h80000000 +`define UNCORE_RAM_RANGE 34'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 975be656..6c2bdd31 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -91,9 +91,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 34'h00001000 `define BOOTROM_RANGE 34'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 34'h80000000 +`define UNCORE_RAM_RANGE 34'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 2f294c34..c785841d 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -92,9 +92,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 34'h00001000 `define BOOTROM_RANGE 34'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 34'h80000000 +`define UNCORE_RAM_RANGE 34'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index f25d4f9b..1cdd10d5 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -91,9 +91,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 34'h00001000 `define BOOTROM_RANGE 34'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 34'h80000000 -`define RAM_RANGE 34'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 34'h80000000 +`define UNCORE_RAM_RANGE 34'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 34'h80000000 `define EXT_MEM_RANGE 34'h07FFFFFF diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index bfedfd33..f2ca2420 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -96,9 +96,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 `define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 56'h80000000 -`define RAM_RANGE 56'h07FFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h80000000 +`define UNCORE_RAM_RANGE 56'h07FFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 56'h80000000 `define EXT_MEM_RANGE 56'h07FFFFFF diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index 5afe6e03..4c7c57ed 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -99,9 +99,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 56'h80000000 -`define RAM_RANGE 56'h7FFFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h80000000 +`define UNCORE_RAM_RANGE 56'h7FFFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 56'h80000000 `define EXT_MEM_RANGE 56'h07FFFFFF diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 315f8d07..f1806e0e 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -98,9 +98,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 56'h80000000 -`define RAM_RANGE 56'h7FFFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h80000000 +`define UNCORE_RAM_RANGE 56'h7FFFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 56'h80000000 `define EXT_MEM_RANGE 56'h07FFFFFF diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 0054bef7..5696252f 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -98,9 +98,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 56'h80000000 -`define RAM_RANGE 56'h7FFFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h80000000 +`define UNCORE_RAM_RANGE 56'h7FFFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 56'h80000000 `define EXT_MEM_RANGE 56'h07FFFFFF diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 80ae5718..ea3f74d4 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -98,9 +98,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 56'h80000000 -`define RAM_RANGE 56'h7FFFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h80000000 +`define UNCORE_RAM_RANGE 56'h7FFFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 56'h80000000 `define EXT_MEM_RANGE 56'h07FFFFFF diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 80521ac7..7b3d3523 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -98,9 +98,9 @@ `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF -`define RAM_SUPPORTED 1'b1 -`define RAM_BASE 56'h80000000 -`define RAM_RANGE 56'h7FFFFFFF +`define UNCORE_RAM_SUPPORTED 1'b1 +`define UNCORE_RAM_BASE 56'h80000000 +`define UNCORE_RAM_RANGE 56'h7FFFFFFF `define EXT_MEM_SUPPORTED 1'b0 `define EXT_MEM_BASE 56'h80000000 `define EXT_MEM_RANGE 56'h07FFFFFF diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 4dcbda66..e5dc27cf 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -49,7 +49,7 @@ module dtim( output logic DCacheMiss, output logic DCacheAccess); - simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( + simpleram #(.BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram ( .clk, .ByteMask(ByteMaskM), .a(CPUBusy | LSURWM[0] | reset ? IEUAdrM[31:0] : IEUAdrE[31:0]), // move mux out; this shouldn't be needed when stails are handled differently *** .we(LSURWM[0] & Cacheable & ~TrapM), // have to ignore write if Trap. diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index f0710e06..b2b5dac0 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -197,7 +197,7 @@ module lsu ( assign IgnoreRequest = IgnoreRequestTLB | TrapM; // The LSU allows both a DTIM and bus with cache. However, the PMA decoding presently - // use the same RAM_BASE addresss for both the DTIM and any RAM in the Uncore. + // use the same UNCORE_RAM_BASE addresss for both the DTIM and any RAM in the Uncore. if (`DMEM) begin : dtim // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index d2768033..8c31ada2 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -42,7 +42,7 @@ module adrdecs ( // Determine which region of physical memory (if any) is being accessed adrdec ddr4dec(PhysicalAddress, `EXT_MEM_BASE, `EXT_MEM_RANGE, `EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[7]); adrdec boottimdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[6]); - adrdec timdec(PhysicalAddress, `RAM_BASE, `RAM_RANGE, `RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[5]); + adrdec timdec(PhysicalAddress, `UNCORE_RAM_BASE, `UNCORE_RAM_RANGE, `UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[5]); adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[4]); adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]); diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 888489b9..883ee8e6 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -106,9 +106,9 @@ module uncore ( assign HSELBRIDGE = HSELGPIO | HSELCLINT | HSELPLIC | HSELUART; // if any of the bridge signals are selected // on-chip RAM - if (`RAM_SUPPORTED) begin : ram + if (`UNCORE_RAM_SUPPORTED) begin : ram ram #( - .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( + .BASE(`UNCORE_RAM_BASE), .RANGE(`UNCORE_RAM_RANGE)) ram ( .HCLK, .HRESETn, .HSELRam, .HADDR, .HWRITE, .HREADY, diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index c37a8f90..6f273acc 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -196,7 +196,7 @@ logic [3:0] dummy; // initialize tests localparam integer MemStartAddr = 0; - localparam integer MemEndAddr = `RAM_RANGE>>1+(`XLEN/32); + localparam integer MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32); initial begin @@ -278,7 +278,7 @@ logic [3:0] dummy; if (!begin_signature_addr) $display("begin_signature addr not found in %s", ProgramLabelMapFile); testadr = ($unsigned(begin_signature_addr))/(`XLEN/8); - testadrNoBase = (begin_signature_addr - `RAM_BASE)/(`XLEN/8); + testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8); #600; // give time for instructions in pipeline to finish if (TEST == "embench") begin // Writes contents of begin_signature to .sim.output file @@ -329,7 +329,7 @@ logic [3:0] dummy; while (signature[i] !== 'bx) begin logic [`XLEN-1:0] sig; if (`DMEM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadrNoBase+i]; - else if (`RAM_SUPPORTED) sig = dut.uncore.ram.ram.memory.RAM[testadrNoBase+i]; + else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin errors = errors+1; @@ -362,7 +362,7 @@ logic [3:0] dummy; else memfilename = {pathname, tests[test], ".elf.memfile"}; //$readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); - else if (`RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); + else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); if (riscofTest) begin @@ -452,7 +452,7 @@ module riscvassertions; assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); - assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); + assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF"); assert (`ZICSR_SUPPORTED == 1 | (`PMP_ENTRIES == 0 & `VIRTMEM_SUPPORTED == 0)) else $error("PMP_ENTRIES and VIRTMEM_SUPPORTED must be zero if ZICSR not supported."); assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); @@ -480,7 +480,7 @@ module DCacheFlushFSM genvar adr; - logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; + logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)]; if(`DCACHE) begin localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;