From b63927b474998da7935e57840ed913f45ab9b2f5 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Fri, 13 Jan 2023 13:56:01 -0600 Subject: [PATCH] Connected the axi_sdc_controller with an axi crossbar. Added an adrdec.sv to the adrdecs.sv file for the sake of the cache. Modified Uncore accordingly. --- fpga/generator/Makefile | 17 +- fpga/generator/wally.tcl | 3 + fpga/generator/xlnx_axi_crossbar.tcl | 31 + .../generator/xlnx_axi_dwidth_conv_32to64.tcl | 25 + .../generator/xlnx_axi_dwidth_conv_64to32.tcl | 27 + fpga/generator/xlnx_axi_dwidth_converter.tcl | 25 + fpga/src/fpgaTop.v | 654 ++++++++++++++++-- pipelined/src/mmu/adrdecs.sv | 7 +- pipelined/src/uncore/uncore.sv | 4 +- 9 files changed, 741 insertions(+), 52 deletions(-) create mode 100644 fpga/generator/xlnx_axi_crossbar.tcl create mode 100644 fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl create mode 100644 fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl create mode 100644 fpga/generator/xlnx_axi_dwidth_converter.tcl diff --git a/fpga/generator/Makefile b/fpga/generator/Makefile index f39a9bce..cdb74839 100644 --- a/fpga/generator/Makefile +++ b/fpga/generator/Makefile @@ -1,13 +1,13 @@ dst := IP # vcu118 -export XILINX_PART := xcvu9p-flga2104-2L-e -export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 -export board := vcu118 +# export XILINX_PART := xcvu9p-flga2104-2L-e +# export XILINX_BOARD := xilinx.com:vcu118:part0:2.4 +# export board := vcu118 # vcu108 -#export XILINX_PART := xcvu095-ffva2104-2-e -#export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 -#export board := vcu108 +export XILINX_PART := xcvu095-ffva2104-2-e +export XILINX_BOARD := xilinx.com:vcu108:part0:1.2 +export board := vcu108 all: FPGA @@ -18,7 +18,10 @@ FPGA: IP IP: $(dst)/xlnx_proc_sys_reset.log \ $(dst)/xlnx_ddr4-$(board).log \ $(dst)/xlnx_axi_clock_converter.log \ - $(dst)/xlnx_ahblite_axi_bridge.log + $(dst)/xlnx_ahblite_axi_bridge.log \ + $(dst)/xlnx_axi_crossbar.log \ + $(dst)/xlnx_axi_dwidth_conv_32to64.log \ + $(dst)/xlnx_axi_dwidth_conv_64to32.log $(dst)/%.log: %.tcl mkdir -p IP diff --git a/fpga/generator/wally.tcl b/fpga/generator/wally.tcl index 6afa9e66..a032a866 100644 --- a/fpga/generator/wally.tcl +++ b/fpga/generator/wally.tcl @@ -14,6 +14,9 @@ read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xln read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci +# Added crossbar - Jacob Pease <2023-01-12 Thu> +read_ip IP/xlnx_axi_crossbar.srcs/sources_1/ip/xlnx_axi_crossbar/xlnx_axi_crossbar.xci + read_verilog -sv [glob -type f ../../pipelined/src/*/*.sv ../../pipelined/src/*/*/*.sv] read_verilog {../src/fpgaTop.v} diff --git a/fpga/generator/xlnx_axi_crossbar.tcl b/fpga/generator/xlnx_axi_crossbar.tcl new file mode 100644 index 00000000..ba867a64 --- /dev/null +++ b/fpga/generator/xlnx_axi_crossbar.tcl @@ -0,0 +1,31 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_crossbar + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_crossbar -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +set_property -dict [list CONFIG.NUM_SI {2} \ + CONFIG.DATA_WIDTH {64} \ + CONFIG.ID_WIDTH {4} \ + CONFIG.M01_S01_READ_CONNECTIVITY {0} \ + CONFIG.M01_S01_WRITE_CONNECTIVITY {0} \ + CONFIG.M00_A00_BASE_ADDR {0x0000000080000000} \ + CONFIG.M01_A00_BASE_ADDR {0x0000000000013000}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl b/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl new file mode 100644 index 00000000..97edd97d --- /dev/null +++ b/fpga/generator/xlnx_axi_dwidth_conv_32to64.tcl @@ -0,0 +1,25 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_dwidth_conv_32to64 + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_32to64}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl b/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl new file mode 100644 index 00000000..3883a8a9 --- /dev/null +++ b/fpga/generator/xlnx_axi_dwidth_conv_64to32.tcl @@ -0,0 +1,27 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_dwidth_conv_64to32 + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +set_property -dict [list CONFIG.Component_Name {axi_dwidth_conv_64to32} \ + CONFIG.SI_DATA_WIDTH {64} \ + CONFIG.MI_DATA_WIDTH {32}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/generator/xlnx_axi_dwidth_converter.tcl b/fpga/generator/xlnx_axi_dwidth_converter.tcl new file mode 100644 index 00000000..ba979bf0 --- /dev/null +++ b/fpga/generator/xlnx_axi_dwidth_converter.tcl @@ -0,0 +1,25 @@ +set partNumber $::env(XILINX_PART) +set boardName $::env(XILINX_BOARD) + +# vcu118 board +#set partNumber xcvu9p-flga2104-2L-e +#set boardName xilinx.com:vcu118:part0:2.4 + +# kcu105 board +#set partNumber xcku040-ffva1156-2-e +#set boardName xilinx.com:kcu105:part0:1.7 + +set ipName xlnx_axi_dwidth_converter + +create_project $ipName . -force -part $partNumber +set_property board_part $boardName [current_project] + +create_ip -name axi_dwidth_converter -vendor xilinx.com -library ip -version 2.1 -module_name $ipName + +set_property -dict [list CONFIG.Component_Name {axi_dwidth_converter}] [get_ips $ipName] + +generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci] +launch_run -jobs 8 ${ipName}_synth_1 +wait_on_run ${ipName}_synth_1 diff --git a/fpga/src/fpgaTop.v b/fpga/src/fpgaTop.v index 6a26be74..48c475b4 100644 --- a/fpga/src/fpgaTop.v +++ b/fpga/src/fpgaTop.v @@ -38,7 +38,7 @@ module fpgaTop input UARTSin, output UARTSout, - input [3:0] SDCDat, + inout [3:0] SDCDat, output SDCCLK, inout SDCCmd, @@ -130,11 +130,13 @@ module fpgaTop wire m_axi_rlast; wire m_axi_rready; + // Extra Bus signals wire [3:0] BUS_axi_arregion; wire [3:0] BUS_axi_arqos; wire [3:0] BUS_axi_awregion; wire [3:0] BUS_axi_awqos; + // Bus signals wire [3:0] BUS_axi_awid; wire [7:0] BUS_axi_awlen; wire [2:0] BUS_axi_awsize; @@ -170,7 +172,7 @@ module fpgaTop wire BUS_axi_rvalid; wire BUS_axi_rlast; wire BUS_axi_rready; - + wire BUSCLK; @@ -179,9 +181,198 @@ module fpgaTop wire [511 : 0] dbg_bus; wire CLK208; - - + + // Crossbar to Bus ------------------------------------------------ + + wire s00_axi_aclk; + wire s00_axi_aresetn; + wire [31:0]s00_axi_awaddr; + wire [7:0]s00_axi_awlen; + wire [2:0]s00_axi_awsize; + wire [1:0]s00_axi_awburst; + wire [0:0]s00_axi_awlock; + wire [3:0]s00_axi_awcache; + wire [2:0]s00_axi_awprot; + wire [3:0]s00_axi_awregion; + wire [3:0]s00_axi_awqos; + wire s00_axi_awvalid; + wire s00_axi_awready; + wire [63:0]s00_axi_wdata; + wire [7:0]s00_axi_wstrb; + wire s00_axi_wlast; + wire s00_axi_wvalid; + wire s00_axi_wready; + wire [1:0]s00_axi_bresp; + wire s00_axi_bvalid; + wire s00_axi_bready; + wire [31:0]s00_axi_araddr; + wire [7:0]s00_axi_arlen; + wire [2:0]s00_axi_arsize; + wire [1:0]s00_axi_arburst; + wire [0:0]s00_axi_arlock; + wire [3:0]s00_axi_arcache; + wire [2:0]s00_axi_arprot; + wire [3:0]s00_axi_arregion; + wire [3:0]s00_axi_arqos; + wire s00_axi_arvalid; + wire s00_axi_arready; + wire [63:0]s00_axi_rdata; + wire [1:0]s00_axi_rresp; + wire s00_axi_rlast; + wire s00_axi_rvalid; + wire s00_axi_rready; + + // 64to32 dwidth converter input interface------------------------- + wire s01_axi_aclk; + wire s01_axi_aresetn; + wire [31:0]s01_axi_awaddr; + wire [7:0]s01_axi_awlen; + wire [2:0]s01_axi_awsize; + wire [1:0]s01_axi_awburst; + wire [0:0]s01_axi_awlock; + wire [3:0]s01_axi_awcache; + wire [2:0]s01_axi_awprot; + wire [3:0]s01_axi_awregion; + wire [3:0]s01_axi_awqos; // qos signals need to be 0 for SDC + wire s01_axi_awvalid; + wire s01_axi_awready; + wire [63:0]s01_axi_wdata; + wire [7:0]s01_axi_wstrb; + wire s01_axi_wlast; + wire s01_axi_wvalid; + wire s01_axi_wready; + wire [1:0]s01_axi_bresp; + wire s01_axi_bvalid; + wire s01_axi_bready; + wire [31:0]s01_axi_araddr; + wire [7:0]s01_axi_arlen; + wire [2:0]s01_axi_arsize; + wire [1:0]s01_axi_arburst; + wire [0:0]s01_axi_arlock; + wire [3:0]s01_axi_arcache; + wire [2:0]s01_axi_arprot; + wire [3:0]s01_axi_arregion; + wire [3:0]s01_axi_arqos; // + wire s01_axi_arvalid; + wire s01_axi_arready; + wire [63:0]s01_axi_rdata; + wire [1:0]s01_axi_rresp; + wire s01_axi_rlast; + wire s01_axi_rvalid; + wire s01_axi_rready; + + // Output Interface + wire [31:0]SDCin_axi_awaddr; + wire [7:0]SDCin_axi_awlen; + wire [2:0]SDCin_axi_awsize; + wire [1:0]SDCin_axi_awburst; + wire [0:0]SDCin_axi_awlock; + wire [3:0]SDCin_axi_awcache; + wire [2:0]SDCin_axi_awprot; + wire [3:0]SDCin_axi_awregion; + wire [3:0]SDCin_axi_awqos; + wire SDCin_axi_awvalid; + wire SDCin_axi_awready; + wire [31:0]SDCin_axi_wdata; + wire [3:0]SDCin_axi_wstrb; + wire SDCin_axi_wlast; + wire SDCin_axi_wvalid; + wire SDCin_axi_wready; + wire [1:0]SDCin_axi_bresp; + wire SDCin_axi_bvalid; + wire SDCin_axi_bready; + wire [31:0]SDCin_axi_araddr; + wire [7:0]SDCin_axi_arlen; + wire [2:0]SDCin_axi_arsize; + wire [1:0]SDCin_axi_arburst; + wire [0:0]SDCin_axi_arlock; + wire [3:0]SDCin_axi_arcache; + wire [2:0]SDCin_axi_arprot; + wire [3:0]SDCin_axi_arregion; + wire [3:0]SDCin_axi_arqos; + wire SDCin_axi_arvalid; + wire SDCin_axi_arready; + wire [31:0]SDCin_axi_rdata; + wire [1:0]SDCin_axi_rresp; + wire SDCin_axi_rlast; + wire SDCin_axi_rvalid; + wire SDCin_axi_rready; + // ---------------------------------------------------------------- + + // 32to64 dwidth converter input interface ----------------------- + wire [31:0]SDCout_axi_awaddr; + wire [7:0]SDCout_axi_awlen; + wire [2:0]SDCout_axi_awsize; + wire [1:0]SDCout_axi_awburst; + wire [0:0]SDCout_axi_awlock; + wire [3:0]SDCout_axi_awcache; + wire [2:0]SDCout_axi_awprot; + wire [3:0]SDCout_axi_awregion; + wire [3:0]SDCout_axi_awqos; + wire SDCout_axi_awvalid; + wire SDCout_axi_awready; + wire [31:0]SDCout_axi_wdata; + wire [3:0]SDCout_axi_wstrb; + wire SDCout_axi_wlast; + wire SDCout_axi_wvalid; + wire SDCout_axi_wready; + wire [1:0]SDCout_axi_bresp; + wire SDCout_axi_bvalid; + wire SDCout_axi_bready; + wire [31:0]SDCout_axi_araddr; + wire [7:0]SDCout_axi_arlen; + wire [2:0]SDCout_axi_arsize; + wire [1:0]SDCout_axi_arburst; + wire [0:0]SDCout_axi_arlock; + wire [3:0]SDCout_axi_arcache; + wire [2:0]SDCout_axi_arprot; + wire [3:0]SDCout_axi_arregion; + wire [3:0]SDCout_axi_arqos; + wire SDCout_axi_arvalid; + wire SDCout_axi_arready; + wire [31:0]SDCout_axi_rdata; + wire [1:0]SDCout_axi_rresp; + wire SDCout_axi_rlast; + wire SDCout_axi_rvalid; + wire SDCout_axi_rready; + + // Output Interface + wire [31:0]m01_axi_awaddr; + wire [7:0]m01_axi_awlen; + wire [2:0]m01_axi_awsize; + wire [1:0]m01_axi_awburst; + wire [0:0]m01_axi_awlock; + wire [3:0]m01_axi_awcache; + wire [2:0]m01_axi_awprot; + wire [3:0]m01_axi_awregion; + wire [3:0]m01_axi_awqos; + wire m01_axi_awvalid; + wire m01_axi_awready; + wire [31:0]m01_axi_wdata; + wire [3:0]m01_axi_wstrb; + wire m01_axi_wlast; + wire m01_axi_wvalid; + wire m01_axi_wready; + wire [1:0]m01_axi_bresp; + wire m01_axi_bvalid; + wire m01_axi_bready; + wire [31:0]m01_axi_araddr; + wire [7:0]m01_axi_arlen; + wire [2:0]m01_axi_arsize; + wire [1:0]m01_axi_arburst; + wire [0:0]m01_axi_arlock; + wire [3:0]m01_axi_arcache; + wire [2:0]m01_axi_arprot; + wire [3:0]m01_axi_arregion; + wire [3:0]m01_axi_arqos; + wire m01_axi_arvalid; + wire m01_axi_arready; + wire [31:0]m01_axi_rdata; + wire [1:0]m01_axi_rresp; + wire m01_axi_rlast; + wire m01_axi_rvalid; + wire m01_axi_rready; assign GPIOPinsIn = {28'b0, GPI}; assign GPO = GPIOPinsOut[4:0]; @@ -295,49 +486,432 @@ module fpgaTop .m_axi_rvalid(m_axi_rvalid), .m_axi_rlast(m_axi_rlast), .m_axi_rready(m_axi_rready)); + + wire [3:0] s00_axi_awid; + wire [7:0] s00_axi_awlen; + wire [2:0] s00_axi_awsize; + wire [1:0] s00_axi_awburst; + wire [3:0] s00_axi_awcache; + wire [31:0] s00_axi_awaddr; + wire [2:0] s00_axi_awprot; + wire s00_axi_awvalid; + wire s00_axi_awready; + wire s00_axi_awlock; + wire [63:0] s00_axi_wdata; + wire [7:0] s00_axi_wstrb; + wire s00_axi_wlast; + wire s00_axi_wvalid; + wire s00_axi_wready; + wire [3:0] s00_axi_bid; + wire [1:0] s00_axi_bresp; + wire s00_axi_bvalid; + wire s00_axi_bready; + wire [3:0] s00_axi_arid; + wire [7:0] s00_axi_arlen; + wire [2:0] s00_axi_arsize; + wire [1:0] s00_axi_arburst; + wire [2:0] s00_axi_arprot; + wire [3:0] s00_axi_arcache; + wire s00_axi_arvalid; + wire [31:0] s00_axi_araddr; + wire s00_axi_arlock; + wire s00_axi_arready; + wire [3:0] s00_axi_rid; + wire [63:0] s00_axi_rdata; + wire [1:0] s00_axi_rresp; + wire s00_axi_rvalid; + wire s00_axi_rlast; + wire s00_axi_rready; + wire [3:0] s01_axi_awid; + wire [7:0] s01_axi_awlen; + wire [2:0] s01_axi_awsize; + wire [1:0] s01_axi_awburst; + wire [3:0] s01_axi_awcache; + wire [31:0] s01_axi_awaddr; + wire [2:0] s01_axi_awprot; + wire s01_axi_awvalid; + wire s01_axi_awready; + wire s01_axi_awlock; + wire [63:0] s01_axi_wdata; + wire [7:0] s01_axi_wstrb; + wire s01_axi_wlast; + wire s01_axi_wvalid; + wire s01_axi_wready; + wire [3:0] s01_axi_bid; + wire [1:0] s01_axi_bresp; + wire s01_axi_bvalid; + wire s01_axi_bready; + wire [3:0] s01_axi_arid; + wire [7:0] s01_axi_arlen; + wire [2:0] s01_axi_arsize; + wire [1:0] s01_axi_arburst; + wire [2:0] s01_axi_arprot; + wire [3:0] s01_axi_arcache; + wire s01_axi_arvalid; + wire [31:0] s01_axi_araddr; + wire s01_axi_arlock; + wire s01_axi_arready; + wire [3:0] s01_axi_rid; + wire [63:0] s01_axi_rdata; + wire [1:0] s01_axi_rresp; + wire s01_axi_rvalid; + wire s01_axi_rlast; + wire s01_axi_rready; + + + // AXI Crossbar for arbitrating the SDC and CPU -------------- + xlnx_axi_crossbar xlnx_axi_crossbar_0 + (.aclk(CPUCLK), + .aresetn(peripheral_aresetn), + + // Connect Masters + .s_axi_awid({m_axi_awid, m01_axi_awid}), + .s_axi_awaddr({m_axi_awaddr, m01_axi_awaddr}), + .s_axi_awlen({m_axi_awlen, m01_axi_awlen}), + .s_axi_awsize({m_axi_awsize, m01_axi_awsize}), + .s_axi_awburst({m_axi_awburst, m01_axi_awburst}), + .s_axi_awlock({m_axi_awlock, m01_axi_awlock}), + .s_axi_awcache({m_axi_awcache, m01_axi_awcache}), + .s_axi_awprot({m_axi_awprot, m01_axi_awprot}), + .s_axi_awqos(8'b0), + .s_axi_awregion(8'b0), + .s_axi_awvalid({m_axi_awvalid, m01_axi_awvalid}), + .s_axi_awready({m_axi_awready, m01_axi_awready}), + .s_axi_wdata({m_axi_wdata, m01_axi_wdata}), + .s_axi_wstrb({m_axi_wstrb, m01_axi_wstrb}), + .s_axi_wlast({m_axi_wlast, m01_axi_wlast}), + .s_axi_wvalid({m_axi_wvalid, m01_axi_wvalid}), + .s_axi_wready({m_axi_wready, m01_axi_wready}), + .s_axi_bid({m_axi_bid, m01_axi_bid}), + .s_axi_bresp({m_axi_bresp, m01_axi_bresp}), + .s_axi_bvalid({m_axi_bvalid, m01_axi_bvalid}), + .s_axi_bready({m_axi_bready, m01_axi_bready}), + .s_axi_arid({m_axi_arid, m01_axi_arid}), + .s_axi_araddr({m_axi_araddr, m01_axi_araddr}), + .s_axi_arlen({m_axi_arlen, m01_axi_arlen}), + .s_axi_arsize({m_axi_arsize, m01_axi_arsize}), + .s_axi_arburst({m_axi_arburst, m01_axi_arburst}), + .s_axi_arlock({m_axi_arlock, m01_axi_arlock}), + .s_axi_arcache({m_axi_arcache, m01_axi_arcache}), + .s_axi_arprot({m_axi_arprot, m01_axi_arprot}), + .s_axi_arqos(8'b0), + .s_axi_arregion(8'b0), + .s_axi_arvalid({m_axi_arvalid, m01_axi_arvalid}), + .s_axi_arready({m_axi_arready, m01_axi_arready}), + .s_axi_rid({m_axi_rid, m01_axi_rid}), + .s_axi_rdata({m_axi_rdata, m01_axi_rdata}), + .s_axi_rresp({m_axi_rresp, m01_axi_rresp}), + .s_axi_rlast({m_axi_rlast, m01_axi_rlast}), + .s_axi_rvalid({m_axi_rvalid, m01_axi_rvalid}), + .s_axi_rready({m_axi_rready, m01_axi_rready}), + + // Connect Slaves + .m_axi_awid({s00_axi_awid, s01_axi_awid}), + .m_axi_awlen({s00_axi_awlen, s01_axi_awlen}), + .m_axi_awsize({s00_axi_awsize, s01_axi_awsize}), + .m_axi_awburst({s00_axi_awburst, s01_axi_awburst}), + .m_axi_awcache({s00_axi_awcache, s01_axi_awcache}), + .m_axi_awaddr({s00_axi_awaddr, s01_axi_awaddr}), + .m_axi_awprot({s00_axi_awprot, s01_axi_awprot}), + .m_axi_awregion({s00_axi_awregion, s01_axi_awregion}), + .m_axi_awqos({s00_axi_awqos, s01_axi_awqos}), + .m_axi_awvalid({s00_axi_awvalid, s01_axi_awvalid}), + .m_axi_awready({s00_axi_awready, s01_axi_awready}), + .m_axi_awlock({s00_axi_awlock, s01_axi_awlock}), + .m_axi_wdata({s00_axi_wdata, s01_axi_wdata}), + .m_axi_wstrb({s00_axi_wstrb, s01_axi_wstrb}), + .m_axi_wlast({s00_axi_wlast, s01_axi_wlast}), + .m_axi_wvalid({s00_axi_wvalid, s01_axi_wvalid}), + .m_axi_wready({s00_axi_wready, s01_axi_wready}), + .m_axi_bid({s00_axi_bid, s01_axi_bid}), + .m_axi_bresp({s00_axi_bresp, s01_axi_bresp}), + .m_axi_bvalid({s00_axi_bvalid, s01_axi_bvalid}), + .m_axi_bready({s00_axi_bready, s01_axi_bready}), + .m_axi_arid({s00_axi_arid, s01_axi_arid}), + .m_axi_arlen({s00_axi_arlen, s01_axi_arlen}), + .m_axi_arsize({s00_axi_arsize, s01_axi_arsize}), + .m_axi_arburst({s00_axi_arburst, s01_axi_arburst}), + .m_axi_arprot({s00_axi_arprot, s01_axi_arprot}), + .m_axi_arregion({s00_axi_arregion, s01_axi_arregion}), + .m_axi_arqos({s00_axi_arqos, s01_axi_arqos}), + .m_axi_arcache({s00_axi_arcache, s01_axi_arcache}), + .m_axi_arvalid({s00_axi_arvalid, s01_axi_arvalid}), + .m_axi_araddr({s00_axi_araddr, s01_axi_araddr}), + .m_axi_arlock({s00_axi_arlock, s01_axi_arlock}), + .m_axi_arready({s00_axi_arready, s01_axi_arready}), + .m_axi_rid({s00_axi_rid, s01_axi_rid}), + .m_axi_rdata({s00_axi_rdata, s01_axi_rdata}), + .m_axi_rresp({s00_axi_rresp, s01_axi_rresp}), + .m_axi_rvalid({s00_axi_rvalid, s01_axi_rvalid}), + .m_axi_rlast({s00_axi_rlast, s01_axi_rlast}), + .m_axi_rready({s00_axi_rready, s01_axi_rready}) + ); + + // ----------------------------------------------------- + + // SDC Implementation ---------------------------------- + // + // The SDC peripheral from Eugene Tarassov takes in an AXI4Lite + // interface and outputs an AXI4 interface. In order to convert from + // one to the other, we use these dwidth converters to make sure the + // bit widths match the rest of the bus. + + xlnx_axi_dwidth_conv_64to32 axi_conv_down + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + + // Slave interface + .s_axi_awaddr(s01_axi_awaddr), + .s_axi_awlen(s01_axi_awlen), + .s_axi_awsize(s01_axi_awsize), + .s_axi_awburst(s01_axi_awburst), + .s_axi_awlock(s01_axi_awlock), + .s_axi_awcache(s01_axi_awcache), + .s_axi_awprot(s01_axi_awprot), + .s_axi_awregion(s01_axi_awregion), + .s_axi_awqos(4'b0), + .s_axi_awvalid(s01_axi_awvalid), + .s_axi_awready(s01_axi_awready), + .s_axi_wdata(s01_axi_wdata), + .s_axi_wstrb(s01_axi_wstrb), + .s_axi_wlast(s01_axi_wlast), + .s_axi_wvalid(s01_axi_wvalid), + .s_axi_wready(s01_axi_wready), + .s_axi_bresp(s01_axi_bresp), + .s_axi_bvalid(s01_axi_bvalid), + .s_axi_bready(s01_axi_bready), + .s_axi_araddr(s01_axi_araddr), + .s_axi_arlen(s01_axi_arlen), + .s_axi_arsize(s01_axi_arsize), + .s_axi_arburst(s01_axi_arburst), + .s_axi_arlock(s01_axi_arlock), + .s_axi_arcache(s01_axi_arcache), + .s_axi_arprot(s01_axi_arprot), + .s_axi_arregion(s01_axi_arregion), + .s_axi_arqos(4'b0), + .s_axi_arvalid(s01_axi_arvalid), + .s_axi_arready(s01_axi_arready), + .s_axi_rdata(s01_axi_rdata), + .s_axi_rresp(s01_axi_rresp), + .s_axi_rlast(s01_axi_rlast), + .s_axi_rvalid(s01_axi_rvalid), + .s_axi_rready(s01_axi_rready), + + // Master interface + .m_axi_awaddr(SDCin_axi_awaddr), + .m_axi_awlen(SDCin_axi_awlen), + .m_axi_awsize(SDCin_axi_awsize), + .m_axi_awburst(SDCin_axi_awburst), + .m_axi_awlock(SDCin_axi_awlock), + .m_axi_awcache(SDCin_axi_awcache), + .m_axi_awprot(SDCin_axi_awprot), + .m_axi_awregion(SDCin_axi_awregion), + .m_axi_awqos(SDCin_axi_awqos), + .m_axi_awvalid(SDCin_axi_awvalid), + .m_axi_awready(SDCin_axi_awready), + .m_axi_wdata(SDCin_axi_wdata), + .m_axi_wstrb(SDCin_axi_wstrb), + .m_axi_wlast(SDCin_axi_wlast), + .m_axi_wvalid(SDCin_axi_wvalid), + .m_axi_wready(SDCin_axi_wready), + .m_axi_bresp(SDCin_axi_bresp), + .m_axi_bvalid(SDCin_axi_bvalid), + .m_axi_bready(SDCin_axi_bready), + .m_axi_araddr(SDCin_axi_araddr), + .m_axi_arlen(SDCin_axi_arlen), + .m_axi_arsize(SDCin_axi_arsize), + .m_axi_arburst(SDCin_axi_arburst), + .m_axi_arlock(SDCin_axi_arlock), + .m_axi_arcache(SDCin_axi_arcache), + .m_axi_arprot(SDCin_axi_arprot), + .m_axi_arregion(SDCin_axi_arregion), + .m_axi_arqos(SDCin_axi_arqos), + .m_axi_arvalid(SDCin_axi_arvalid), + .m_axi_arready(SDCin_axi_arready), + .m_axi_rdata(SDCin_axi_rdata), + .m_axi_rresp(SDCin_axi_rresp), + .m_axi_rlast(SDCin_axi_rlast), + .m_axi_rvalid(SDCin_axi_rvalid), + .m_axi_rready(SDCin_axi_rready), + ); + + axi_sdc_controller axiSDC + (.clock(CPUCLK), + .async_resetn(peripheral_aresetn), + + // Slave Interface + .s_axi_awaddr(SDCin_axi_awaddr[15:0]), + .s_axi_awvalid(SDCin_axi_awvalid), + .s_axi_awready(SDCin_axi_awready), + .s_axi_wdata(SDCin_axi_wdata), + .s_axi_wvalid(SDCin_axi_wvalid), + .s_axi_wready(SDCin_axi_wready), + .s_axi_bresp(SDCin_axi_bresp), + .s_axi_bvalid(SDCin_axi_bvalid), + .s_axi_bready(SDCin_axi_bready), + .s_axi_araddr(SDCin_axi_araddr[15:0]), + .s_axi_arvalid(SDCin_axi_arvalid), + .s_axi_arready(SDCin_axi_arready), + .s_axi_rdata(SDCin_axi_rdata), + .s_axi_rresp(SDCin_axi_rresp), + .s_axi_rvalid(SDCin_axi_rvalid), + .s_axi_rready(SDCin_axi_rready), + + // Master Interface + .m_axi_awaddr(SDCout_axi_awaddr), + .m_axi_awlen(SDCout_axi_awlen), + .m_axi_awvalid(SDCout_axi_awvalid), + .m_axi_awready(SDCout_axi_awready), + .m_axi_wdata(SDCout_axi_wdata), + .m_axi_wlast(SDCout_axi_wlast), + .m_axi_wvalid(SDCout_axi_wvalid), + .m_axi_wready(SDCout_axi_wready), + .m_axi_bresp(SDCout_axi_bresp), + .m_axi_bvalid(SDCout_axi_bvalid), + .m_axi_bready(SDCout_axi_bready), + .m_axi_araddr(SDCout_axi_araddr), + .m_axi_arlen(SDCout_axi_arlen), + .m_axi_arvalid(SDCout_axi_arvalid), + .m_axi_arready(SDCout_axi_arready), + .m_axi_rdata(SDCout_axi_rdata), + .m_axi_rlast(SDCout_axi_rlast), + .m_axi_rresp(SDCout_axi_rresp), + .m_axi_rvalid(SDCout_axi_rvalid), + .m_axi_rready(SDCout_axi_rready), + + // SDC interface + //.sdio_cmd(SDCcmd), + //.sdio_dat(SDCdat), + //.sdio_cd() + + + + ); + + xlnx_axi_dwidth_conv_32to64 axi_conv_up + (.s_axi_aclk(CPUCLK), + .s_axi_aresetn(peripheral_aresetn), + + // Slave interface + .s_axi_awaddr(SDCout_axi_awaddr), + .s_axi_awlen(SDCout_axi_awlen), + .s_axi_awsize(3'b0), + .s_axi_awburst(2'b0), + .s_axi_awlock(1'b0), + .s_axi_awcache(4'b0), + .s_axi_awprot(3'b0), + .s_axi_awregion(4'b0), + .s_axi_awqos(4'b0), + .s_axi_awvalid(SDCout_axi_awvalid), + .s_axi_awready(SDCout_axi_awready), + .s_axi_wdata(SDCout_axi_wdata), + .s_axi_wstrb(4'b0), + .s_axi_wlast(SDCout_axi_wlast), + .s_axi_wvalid(SDCout_axi_wvalid), + .s_axi_wready(SDCout_axi_wready), + .s_axi_bresp(SDCout_axi_bresp), + .s_axi_bvalid(SDCout_axi_bvalid), + .s_axi_bready(SDCout_axi_bready), + .s_axi_araddr(SDCout_axi_araddr), + .s_axi_arlen(SDCout_axi_arlen), + .s_axi_arsize(3'b0), + .s_axi_arburst(2'b0), + .s_axi_arlock(1'b0), + .s_axi_arcache(4'b0), + .s_axi_arprot(3'b0), + .s_axi_arregion(4'b0), + .s_axi_arqos(4'b0), + .s_axi_arvalid(SDCout_axi_arvalid), + .s_axi_arready(SDCout_axi_arready), + .s_axi_rdata(SDCout_axi_rdata), + //.s_axi_rresp(), + .s_axi_rlast(SDCout_axi_rlast), + .s_axi_rvalid(SDCout_axi_rvalid), + .s_axi_rready(SDCout_axi_rready), + + // Master interface + .m_axi_awaddr(m01_axi_awaddr), + .m_axi_awlen(m01_axi_awlen), + .m_axi_awsize(m01_axi_awsize), + .m_axi_awburst(m01_axi_awburst), + .m_axi_awlock(m01_axi_awlock), + .m_axi_awcache(m01_axi_awcache), + .m_axi_awprot(m01_axi_awprot), + .m_axi_awregion(m01_axi_awregion), + .m_axi_awqos(m01_axi_awqos), + .m_axi_awvalid(m01_axi_awvalid), + .m_axi_awready(m01_axi_awready), + .m_axi_wdata(m01_axi_wdata), + .m_axi_wstrb(m01_axi_wstrb), + .m_axi_wlast(m01_axi_wlast), + .m_axi_wvalid(m01_axi_wvalid), + .m_axi_wready(m01_axi_wready), + .m_axi_bresp(m01_axi_bresp), + .m_axi_bvalid(m01_axi_bvalid), + .m_axi_bready(m01_axi_bready), + .m_axi_araddr(m01_axi_araddr), + .m_axi_arlen(m01_axi_arlen), + .m_axi_arsize(m01_axi_arsize), + .m_axi_arburst(m01_axi_arburst), + .m_axi_arlock(m01_axi_arlock), + .m_axi_arcache(m01_axi_arcache), + .m_axi_arprot(m01_axi_arprot), + .m_axi_arregion(m01_axi_arregion), + .m_axi_arqos(m01_axi_arqos), + .m_axi_arvalid(m01_axi_arvalid), + .m_axi_arready(m01_axi_arready), + .m_axi_rdata(m01_axi_rdata), + .m_axi_rresp(m01_axi_rresp), + .m_axi_rlast(m01_axi_rlast), + .m_axi_rvalid(m01_axi_rvalid), + .m_axi_rready(m01_axi_rready), + ); + + // End SDC signals -------------------------------------------- + xlnx_axi_clock_converter xlnx_axi_clock_converter_0 (.s_axi_aclk(CPUCLK), .s_axi_aresetn(peripheral_aresetn), - .s_axi_awid(m_axi_awid), - .s_axi_awlen(m_axi_awlen), - .s_axi_awsize(m_axi_awsize), - .s_axi_awburst(m_axi_awburst), - .s_axi_awcache(m_axi_awcache), - .s_axi_awaddr(m_axi_awaddr[30:0]), - .s_axi_awprot(m_axi_awprot), + .s_axi_awid(s00_axi_awid), + .s_axi_awlen(s00_axi_awlen), + .s_axi_awsize(s00_axi_awsize), + .s_axi_awburst(s00_axi_awburst), + .s_axi_awcache(s00_axi_awcache), + .s_axi_awaddr(s00_axi_awaddr[30:0] ), + .s_axi_awprot(s00_axi_awprot), .s_axi_awregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_awqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_awvalid(m_axi_awvalid), - .s_axi_awready(m_axi_awready), - .s_axi_awlock(m_axi_awlock), - .s_axi_wdata(m_axi_wdata), - .s_axi_wstrb(m_axi_wstrb), - .s_axi_wlast(m_axi_wlast), - .s_axi_wvalid(m_axi_wvalid), - .s_axi_wready(m_axi_wready), - .s_axi_bid(m_axi_bid), - .s_axi_bresp(m_axi_bresp), - .s_axi_bvalid(m_axi_bvalid), - .s_axi_bready(m_axi_bready), - .s_axi_arid(m_axi_arid), - .s_axi_arlen(m_axi_arlen), - .s_axi_arsize(m_axi_arsize), - .s_axi_arburst(m_axi_arburst), - .s_axi_arprot(m_axi_arprot), + .s_axi_awvalid(s00_axi_awvalid), + .s_axi_awready(s00_axi_awready), + .s_axi_awlock(s00_axi_awlock), + .s_axi_wdata(s00_axi_wdata), + .s_axi_wstrb(s00_axi_wstrb), + .s_axi_wlast(s00_axi_wlast), + .s_axi_wvalid(s00_axi_wvalid), + .s_axi_wready(s00_axi_wready), + .s_axi_bid(s00_axi_bid), + .s_axi_bresp(s00_axi_bresp), + .s_axi_bvalid(s00_axi_bvalid), + .s_axi_bready(s00_axi_bready), + .s_axi_arid(s00_axi_arid), + .s_axi_arlen(s00_axi_arlen), + .s_axi_arsize(s00_axi_arsize), + .s_axi_arburst(s00_axi_arburst), + .s_axi_arprot(s00_axi_arprot), .s_axi_arregion(4'b0), // this could be a bug. bridge does not have these outputs .s_axi_arqos(4'b0), // this could be a bug. bridge does not have these outputs - .s_axi_arcache(m_axi_arcache), - .s_axi_arvalid(m_axi_arvalid), - .s_axi_araddr(m_axi_araddr[30:0]), - .s_axi_arlock(m_axi_arlock), - .s_axi_arready(m_axi_arready), - .s_axi_rid(m_axi_rid), - .s_axi_rdata(m_axi_rdata), - .s_axi_rresp(m_axi_rresp), - .s_axi_rvalid(m_axi_rvalid), - .s_axi_rlast(m_axi_rlast), - .s_axi_rready(m_axi_rready), + .s_axi_arcache(s00_axi_arcache), + .s_axi_arvalid(s00_axi_arvalid), + .s_axi_araddr(s00_axi_araddr[30:0]), + .s_axi_arlock(s00_axi_arlock), + .s_axi_arready(s00_axi_arready), + .s_axi_rid(s00_axi_rid), + .s_axi_rdata(s00_axi_rdata), + .s_axi_rresp(s00_axi_rresp), + .s_axi_rvalid(s00_axi_rvalid), + .s_axi_rlast(s00_axi_rlast), + .s_axi_rready(s00_axi_rready), .m_axi_aclk(BUSCLK), .m_axi_aresetn(~reset), @@ -380,7 +954,7 @@ module fpgaTop .m_axi_rvalid(BUS_axi_rvalid), .m_axi_rlast(BUS_axi_rlast), .m_axi_rready(BUS_axi_rready)); - + xlnx_ddr4 xlnx_ddr4_c0 (.c0_init_calib_complete(c0_init_calib_complete), .dbg_clk(dbg_clk), // open diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 4df5187d..3443af1a 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -31,7 +31,7 @@ module adrdecs ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic AccessRW, AccessRX, AccessRWX, input logic [1:0] Size, - output logic [10:0] SelRegions + output logic [11:0] SelRegions ); localparam logic [3:0] SUPPORTED_SIZE = (`LLEN == 32 ? 4'b0111 : 4'b1111); @@ -46,8 +46,9 @@ module adrdecs ( adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[3]); adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[2]); adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[1]); - - assign SelRegions[0] = ~|(SelRegions[10:1]); // none of the regions are selected + adrdec newsdc(PhysicalAddressm `SDC2_BASE, `SDC2RANGE, 1'b1, AccessRW, Size, SUPPORTED_SIZE, SelRegions[11]); + + assign SelRegions[0] = ~|(SelRegions[11:1]); // none of the regions are selected endmodule diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index 4d1a30e2..7ec5a922 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -63,7 +63,7 @@ module uncore ( logic [`XLEN-1:0] HREADRam, HREADSDC; - logic [10:0] HSELRegions; + logic [11:0] HSELRegions; logic HSELDTIM, HSELIROM, HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC; logic HSELDTIMD, HSELIROMD, HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD; logic HRESPRam, HRESPSDC; @@ -197,7 +197,7 @@ module uncore ( // takes more than 1 cycle to repsond it needs to hold on to the old select until the // device is ready. Hense this register must be selectively enabled by HREADY. // However on reset None must be seleted. - flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); + flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:0], 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); endmodule