From e98dd420bcf4e4d815d9e1546077fc6bea97c647 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 25 Mar 2021 00:10:44 -0400 Subject: [PATCH 2/6] future work comment about suspicious-looking verilog in csri.sv --- wally-pipelined/src/privileged/csri.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/privileged/csri.sv b/wally-pipelined/src/privileged/csri.sv index ee84c222..488c6ba4 100644 --- a/wally-pipelined/src/privileged/csri.sv +++ b/wally-pipelined/src/privileged/csri.sv @@ -49,7 +49,7 @@ module csri #(parameter // assumes no N-mode user interrupts always_comb begin - IntInM = 0; + IntInM = 0; // *** does this really work IntInM[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP From 717257d9ac039d2ad42db54c78df4c698ec081f6 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 25 Mar 2021 00:13:46 -0400 Subject: [PATCH 3/6] gitignore FunctionRadix.addr --- .gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitignore b/.gitignore index 8692d6bc..de0e5e82 100644 --- a/.gitignore +++ b/.gitignore @@ -10,4 +10,5 @@ wally-pipelined/wlft* wlft* /imperas-riscv-tests/FunctionRadix_32.addr /imperas-riscv-tests/FunctionRadix_64.addr +/imperas-riscv-tests/FunctionRadix.addr /imperas-riscv-tests/ProgramMap.txt From 1e3f683a9d9ef60875471a90cd8f6ab74dd4492b Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 25 Mar 2021 00:15:02 -0400 Subject: [PATCH 4/6] upgraded gpio bus interface --- wally-pipelined/src/uncore/gpio.sv | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/wally-pipelined/src/uncore/gpio.sv b/wally-pipelined/src/uncore/gpio.sv index 216e30dd..778cc535 100644 --- a/wally-pipelined/src/uncore/gpio.sv +++ b/wally-pipelined/src/uncore/gpio.sv @@ -33,6 +33,8 @@ module gpio ( input logic [7:0] HADDR, input logic [`XLEN-1:0] HWDATA, input logic HWRITE, + input logic HREADY, + input logic [1:0] HTRANS, output logic [`XLEN-1:0] HREADGPIO, output logic HRESPGPIO, HREADYGPIO, input logic [31:0] GPIOPinsIn, @@ -40,15 +42,19 @@ module gpio ( logic [31:0] INPUT_VAL, INPUT_EN, OUTPUT_EN, OUTPUT_VAL; - logic [7:0] entry; - logic memread, memwrite; + logic [7:0] entry, HADDRd; + logic initTrans, memread, memwrite; - assign memread = HSELGPIO & ~HWRITE; - assign memwrite = HSELGPIO & HWRITE; + assign initTrans = HREADY & HSELGPIO & (HTRANS != 2'b00); + + // Control Signals + flopenr #(1) memreadreg(HCLK, ~HRESETn, initTrans, ~HWRITE, memread); + flopenr #(1) memwritereg(HCLK, ~HRESETn, initTrans, HWRITE, memwrite); + flopenr #(8) haddrreg(HCLK, ~HRESETn, initTrans, HADDR, HADDRd); + + // Response Signals assign HRESPGPIO = 0; // OK - always_ff @(posedge HCLK) // delay response to data cycle - HREADYGPIO <= memread | memwrite; -// assign HREADYGPIO = 1; // Respond immediately + assign HREADYGPIO = 1; // never ask for wait states // word aligned reads generate @@ -103,7 +109,6 @@ module gpio ( if (~HRESETn) begin INPUT_EN <= 0; OUTPUT_EN <= 0; - //OUTPUT_VAL <= 0;// spec indicates synchronous rset (software control) end else if (memwrite) begin if (entry == 8'h04) INPUT_EN <= HWDATA; if (entry == 8'h08) OUTPUT_EN <= HWDATA; From 02e924e55a0fb2d9af25cae78b8b62a0637b77e9 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 25 Mar 2021 00:16:26 -0400 Subject: [PATCH 5/6] instrfaults not respecting stalls bugfix --- wally-pipelined/src/ifu/ifu.sv | 2 +- wally-pipelined/src/privileged/privileged.sv | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index bad52a94..eb65e167 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -162,7 +162,7 @@ module ifu ( endgenerate // Decode stage pipeline register and logic - flopenl #(32) InstrDReg(clk, reset, ~StallD, (FlushD ? nop : InstrF), nop, InstrRawD); + flopenl #(32) InstrDReg(clk, reset, ~StallD | FlushD, (FlushD ? nop : InstrF), nop, InstrRawD); flopenrc #(`XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD); // expand 16-bit compressed instructions to 32 bits diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 8a6854e9..c967d262 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -125,10 +125,10 @@ module privileged ( // pipeline fault signals flopenrc #(1) faultregD(clk, reset, FlushD, ~StallD, InstrAccessFaultF, InstrAccessFaultD); - floprc #(2) faultregE(clk, reset, FlushE, + flopenrc #(2) faultregE(clk, reset, FlushE, ~StallE, {IllegalIEUInstrFaultD, InstrAccessFaultD}, // ** vs IllegalInstrFaultInD {IllegalIEUInstrFaultE, InstrAccessFaultE}); - floprc #(2) faultregM(clk, reset, FlushM, + flopenrc #(2) faultregM(clk, reset, FlushM, ~StallM, {IllegalIEUInstrFaultE, InstrAccessFaultE}, {IllegalIEUInstrFaultM, InstrAccessFaultM}); From a3788eb21837cf857cb70ee423433b30a1b0ebf4 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 25 Mar 2021 02:23:30 -0400 Subject: [PATCH 6/6] added 1 tick delay to dtim flops --- wally-pipelined/src/uncore/dtim.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv index a5c4574e..29d938f1 100644 --- a/wally-pipelined/src/uncore/dtim.sv +++ b/wally-pipelined/src/uncore/dtim.sv @@ -85,15 +85,15 @@ module dtim #(parameter BASE=0, RANGE = 65535) ( generate if (`XLEN == 64) begin always_ff @(posedge HCLK) begin - HWADDR <= A; - HREADTim0 <= RAM[A[31:3]]; - if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= HWDATA; + HWADDR <= #1 A; + HREADTim0 <= #1 RAM[A[31:3]]; + if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA; end end else begin always_ff @(posedge HCLK) begin - HWADDR <= A; - HREADTim0 <= RAM[A[31:2]]; - if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= HWDATA; + HWADDR <= #1 A; + HREADTim0 <= #1 RAM[A[31:2]]; + if (memwrite && risingHREADYTim) RAM[HWADDR[31:2]] <= #1 HWDATA; end end endgenerate