From b4c7998ded5a6264980c12770f737f96bd6f8ea1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 23 Dec 2022 12:47:18 -0600 Subject: [PATCH] DON'T USE. First commit in attempt to move fpustall detection into the decode stage. --- pipelined/src/fpu/fctrl.sv | 21 ++++++++++++++++----- pipelined/src/fpu/fhazard.sv | 15 +++++++++------ pipelined/src/fpu/fpu.sv | 15 +++++++++------ pipelined/src/ieu/ieu.sv | 3 +-- pipelined/src/wally/wallypipelinedcore.sv | 6 +++--- 5 files changed, 38 insertions(+), 22 deletions(-) diff --git a/pipelined/src/fpu/fctrl.sv b/pipelined/src/fpu/fctrl.sv index 31ac865c..6f00bf0d 100755 --- a/pipelined/src/fpu/fctrl.sv +++ b/pipelined/src/fpu/fctrl.sv @@ -44,16 +44,18 @@ module fctrl ( input logic [1:0] STATUS_FS, // is FPU enabled? input logic FDivBusyE, // is the divider busy output logic IllegalFPUInstrM, // Is the instruction an illegal fpu instruction - output logic FRegWriteM, FRegWriteW, // FP register write enable + output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable output logic [2:0] FrmM, // FP rounding mode output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format output logic FDivStartE, IDivStartE, // Start division or squareroot + output logic XEnD, YEnD, ZEnD, output logic XEnE, YEnE, ZEnE, output logic FWriteIntE, FCvtIntE, FWriteIntM, // Write to integer register output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit output logic FCvtIntW, + output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input output logic [4:0] Adr1E, Adr2E, Adr3E // adresses of each input ); @@ -63,7 +65,6 @@ module fctrl ( logic FRegWriteD; // FP register write enable logic FDivStartD; // integer register write enable logic FWriteIntD; // integer register write enable - logic FRegWriteE; // FP register write enable logic [2:0] OpCtrlD; // Select which opperation to do in each component logic [1:0] PostProcSelD; // select result in the post processing unit logic [1:0] FResSelD; // Select one of the results that finish in the memory stage @@ -202,11 +203,18 @@ module fctrl ( // Y - all except cvt, mv, load, class, sqrt // Z - fma ops only // load/store mv int->fp cvt int->fp +/// *** turn into registers. assign XEnE = ~(((FResSelE==2'b10)&~FWriteIntE)|((FResSelE==2'b11)&FRegWriteE)|((FResSelE==2'b01)&(PostProcSelE==2'b00)&OpCtrlE[2])); // load/class mv cvt assign YEnE = ~(((FResSelE==2'b10)&(FWriteIntE|FRegWriteE))|(FResSelE==2'b11)|((FResSelE==2'b01)&((PostProcSelE==2'b00)|((PostProcSelE==2'b01)&OpCtrlE[0])))); assign ZEnE = (PostProcSelE==2'b10)&(FResSelE==2'b01)&(~OpCtrlE[2]|OpCtrlE[1]); + + assign XEnD = ~(((FResSelD==2'b10)&~FWriteIntD)|((FResSelD==2'b11)&FRegWriteD)|((FResSelD==2'b01)&(PostProcSelD==2'b00)&OpCtrlD[2])); +// load/class mv cvt + assign YEnD = ~(((FResSelD==2'b10)&(FWriteIntD|FRegWriteD))|(FResSelD==2'b11)|((FResSelD==2'b01)&((PostProcSelD==2'b00)|((PostProcSelD==2'b01)&OpCtrlD[0])))); + + assign ZEnD = (PostProcSelD==2'b10)&(FResSelD==2'b01)&(~OpCtrlD[2]|OpCtrlD[1]); // Final Res Sel: @@ -258,13 +266,16 @@ module fctrl ( // 00 - sign // 01 - negate sign // 10 - xor sign - + + assign Adr1D = InstrD[19:15]; + assign Adr2D = InstrD[24:20]; + assign Adr3D = InstrD[31:27]; + // D/E pipleine register flopenrc #(14+`FMTBITS) DECtrlReg3(clk, reset, FlushE, ~StallE, {FRegWriteD, PostProcSelD, FResSelD, FrmD, FmtD, OpCtrlD, FWriteIntD, IllegalFPUInstrD, FCvtIntD}, {FRegWriteE, PostProcSelE, FResSelE, FrmE, FmtE, OpCtrlE, FWriteIntE, IllegalFPUInstrE, FCvtIntE}); - flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {InstrD[19:15], InstrD[24:20], InstrD[31:27]}, - {Adr1E, Adr2E, Adr3E}); + flopenrc #(15) DEAdrReg(clk, reset, FlushE, ~StallE, {Adr1D, Adr2D, Adr3D}, {Adr1E, Adr2E, Adr3E}); flopenrc #(1) DEFDivStartReg(clk, reset, FlushE, ~StallE|FDivBusyE, FDivStartD, FDivStartE); if (`M_SUPPORTED) assign IDivStartE = MDUE & Funct3E[2]; else assign IDivStartE = 0; diff --git a/pipelined/src/fpu/fhazard.sv b/pipelined/src/fpu/fhazard.sv index 313e2343..62dee1f6 100644 --- a/pipelined/src/fpu/fhazard.sv +++ b/pipelined/src/fpu/fhazard.sv @@ -31,29 +31,34 @@ `include "wally-config.vh" module fhazard( + input logic [4:0] Adr1D, Adr2D, Adr3D, // read data adresses input logic [4:0] Adr1E, Adr2E, Adr3E, // read data adresses - input logic FRegWriteM, FRegWriteW, // is the fp register being written to - input logic [4:0] RdM, RdW, // the adress being written to + input logic FRegWriteE, FRegWriteM, FRegWriteW, // is the fp register being written to + input logic [4:0] RdE, RdM, RdW, // the adress being written to input logic [1:0] FResSelM, // the result being selected + input logic XEnD, YEnD, ZEnD, input logic XEnE, YEnE, ZEnE, output logic FPUStallD, // stall the decode stage output logic [1:0] ForwardXE, ForwardYE, ForwardZE // select a forwarded value ); + logic MatchDE; + // Decode-stage instruction source depends on result from execute stage instruction + assign MatchDE = ((Adr1D == RdE) & XEnD) | ((Adr2D == RdE) & YEnD) | ((Adr3D == RdE) & ZEnD); + assign FPUStallD = MatchDE & FRegWriteE; + always_comb begin // set defaults ForwardXE = 2'b00; // choose FRD1E ForwardYE = 2'b00; // choose FRD2E ForwardZE = 2'b00; // choose FRD3E - FPUStallD = 0; // if the needed value is in the memory stage - input 1 if(XEnE) if ((Adr1E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardXE = 2'b10; // choose FResM - else FPUStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr1E == RdW) & FRegWriteW) ForwardXE = 2'b01; // choose FPUResult64W @@ -63,7 +68,6 @@ module fhazard( if ((Adr2E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardYE = 2'b10; // choose FResM - else FPUStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr2E == RdW) & FRegWriteW) ForwardYE = 2'b01; // choose FPUResult64W @@ -73,7 +77,6 @@ module fhazard( if ((Adr3E == RdM) & FRegWriteM) // if the result will be FResM (can be taken from the memory stage) if(FResSelM == 2'b00) ForwardZE = 2'b10; // choose FResM - else FPUStallD = 1; // otherwise stall // if the needed value is in the writeback stage else if ((Adr3E == RdW) & FRegWriteW) ForwardZE = 2'b01; // choose FPUResult64W diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 5120a2ae..ca700be1 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -40,7 +40,7 @@ module fpu ( input logic StallE, StallM, StallW, // stall signals (from HZU) //input logic TrapM, input logic FlushE, FlushM, FlushW, // flush signals (from HZU) - input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) + input logic [4:0] RdE, RdM, RdW, // which FP register to write to (from IEU) input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) input logic [2:0] Funct3E, Funct3M, input logic MDUE, W64E, @@ -75,8 +75,11 @@ module fpu ( logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit + logic [4:0] Adr1D, Adr2D, Adr3D; // adresses of each input logic [4:0] Adr1E, Adr2E, Adr3E; // adresses of each input + logic XEnD, YEnD, ZEnD; logic XEnE, YEnE, ZEnE; + logic FRegWriteE; // regfile signals logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage @@ -167,9 +170,9 @@ module fpu ( fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]), .Funct3E, .MDUE, .InstrD, .StallE, .StallM, .StallW, .FlushE, .FlushM, .FlushW, .FRM_REGW, .STATUS_FS, .FDivBusyE, - .reset, .clk, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, - .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnE, .YEnE, .ZEnE, - .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1E, .Adr2E, .Adr3E); + .reset, .clk, .FRegWriteE, .FRegWriteM, .FRegWriteW, .FrmM, .FmtE, .FmtM, + .FDivStartE, .IDivStartE, .FWriteIntE, .FCvtIntE, .FWriteIntM, .OpCtrlE, .OpCtrlM, .IllegalFPUInstrM, .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE, + .FResSelE, .FResSelM, .FResSelW, .PostProcSelE, .PostProcSelM, .FCvtIntW, .Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E); // FP register file fregfile fregfile (.clk, .reset, .we4(FRegWriteW), @@ -196,8 +199,8 @@ module fpu ( // Hazard unit for FPU // - determines if any forwarding or stalls are needed - fhazard fhazard(.Adr1E, .Adr2E, .Adr3E, .FRegWriteM, .FRegWriteW, .RdM, .RdW, .FResSelM, - .XEnE, .YEnE, .ZEnE, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE); + fhazard fhazard(.Adr1D, .Adr2D, .Adr3D, .Adr1E, .Adr2E, .Adr3E, .FRegWriteE, .FRegWriteM, .FRegWriteW, .RdE, .RdM, .RdW, .FResSelM, + .XEnD, .YEnD, .ZEnD, .XEnE, .YEnE, .ZEnE, .FPUStallD, .ForwardXE, .ForwardYE, .ForwardZE); // forwarding muxs mux3 #(`FLEN) fxemux (FRD1E, FPUResultW, PreFpResM, ForwardXE, XE); diff --git a/pipelined/src/ieu/ieu.sv b/pipelined/src/ieu/ieu.sv index 8e8c3f5a..1136452d 100644 --- a/pipelined/src/ieu/ieu.sv +++ b/pipelined/src/ieu/ieu.sv @@ -53,7 +53,7 @@ module ieu ( output logic [2:0] Funct3M, // size and signedness to LSU output logic [`XLEN-1:0] SrcAM, // to privilege and fpu - output logic [4:0] RdM, + output logic [4:0] RdE, RdM, input logic [`XLEN-1:0] FIntResM, output logic InvalidateICacheM, FlushDCacheM, @@ -82,7 +82,6 @@ module ieu ( logic [2:0] ResultSrcW; logic ALUResultSrcE; logic SCE; - logic [4:0] RdE; logic FWriteIntM; logic DivW; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index 76adf9c9..22a0321d 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -85,7 +85,7 @@ module wallypipelinedcore ( logic SquashSCW; // floating point unit signals logic [2:0] FRM_REGW; - logic [4:0] RdM, RdW; + logic [4:0] RdE, RdM, RdW; logic FPUStallD; logic FWriteIntE; logic [`FLEN-1:0] FWriteDataM; @@ -226,7 +226,7 @@ module wallypipelinedcore ( .WriteDataM, // Write data to LSU .Funct3M, // size and signedness to LSU .SrcAM, // to privilege and fpu - .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, + .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, // Writeback stage .CSRReadValW, .MDUResultW, .FPIntDivResultW, @@ -392,7 +392,7 @@ module wallypipelinedcore ( .StallE, .StallM, .StallW, // stall signals from HZU //.TrapM, .FlushE, .FlushM, .FlushW, // flush signals from HZU - .RdM, .RdW, // which FP register to write to (from IEU) + .RdE, .RdM, .RdW, // which FP register to write to (from IEU) .STATUS_FS, // is floating-point enabled? .FRegWriteM, // FP register write enable .FpLoadStoreM,