diff --git a/pipelined/src/fpu/divshiftcalc.sv b/pipelined/src/fpu/divshiftcalc.sv
index 01d8f020..938bb5a3 100644
--- a/pipelined/src/fpu/divshiftcalc.sv
+++ b/pipelined/src/fpu/divshiftcalc.sv
@@ -8,11 +8,10 @@ module divshiftcalc(
     output logic [`LOGNORMSHIFTSZ-1:0] DivShiftAmt,
     output logic [`NORMSHIFTSZ-1:0] DivShiftIn,
     output logic DivResDenorm,
-    output logic [`NE+1:0] DivDenormShift
+    output logic DivDenormShiftPos
 );
     logic [`LOGNORMSHIFTSZ-1:0] NormShift, DivDenormShiftAmt;
-    //logic [`NE+1:0] DivDenormShift;
-    logic DivDenormShiftPos;
+    logic [`NE+1:0] DivDenormShift;
 
     logic [`DURLEN-1:0] DivEarlyTermShift = 0;
 
@@ -38,9 +37,10 @@ module divshiftcalc(
     // inital Left shift amount  = NF
     // shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
     assign NormShift = (`LOGNORMSHIFTSZ)'(`NF);
+
     // if the shift amount is negitive then don't shift (keep sticky bit)
     // need to multiply the early termination shift by LOGR*DIVCOPIES =  left shift of log2(LOGR*DIVCOPIES)
-    assign DivDenormShiftAmt = DivDenormShift[`LOGNORMSHIFTSZ-1:0]&{`LOGNORMSHIFTSZ{DivDenormShiftPos}};
+    assign DivDenormShiftAmt = DivDenormShiftPos ? DivDenormShift[`LOGNORMSHIFTSZ-1:0] : '0;
     assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift;
 
     assign DivShiftIn = {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1+(`RADIX/4)-`NF{1'b0}}};
diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv
index c1be1936..761ae04d 100644
--- a/pipelined/src/fpu/postprocess.sv
+++ b/pipelined/src/fpu/postprocess.sv
@@ -103,7 +103,7 @@ module postprocess (
     logic [`NE+1:0] Qe;
     logic DivByZero;
     logic DivResDenorm;
-    logic [`NE+1:0] DivDenormShift;
+    logic DivDenormShiftPos;
     // conversion signals
     logic [`CVTLEN+`NF:0] CvtShiftIn;    // number to be shifted
     logic [1:0] CvtNegResMsbs;
@@ -151,7 +151,7 @@ module postprocess (
                               .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
     fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe,
                           .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn);
-    divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShift, .DivShiftAmt, .DivShiftIn);
+    divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn);
 
     always_comb
         case(PostProcSel)
@@ -181,7 +181,7 @@ module postprocess (
     normshift normshift (.ShiftIn, .ShiftAmt, .Shifted);
 
     shiftcorrection shiftcorrection(.FmaOp, .FmaPreResultDenorm, .NormSumExp,
-                                .DivResDenorm, .DivDenormShift, .DivOp, .DivQe,
+                                .DivResDenorm, .DivDenormShiftPos, .DivOp, .DivQe,
                                 .Qe, .FmaSZero, .Shifted, .FmaMe, .Mf);
 
     ///////////////////////////////////////////////////////////////////////////////
diff --git a/pipelined/src/fpu/shiftcorrection.sv b/pipelined/src/fpu/shiftcorrection.sv
index 4839ba29..01be2f3f 100644
--- a/pipelined/src/fpu/shiftcorrection.sv
+++ b/pipelined/src/fpu/shiftcorrection.sv
@@ -34,7 +34,7 @@ module shiftcorrection(
     input logic                     DivOp,
     input logic                     DivResDenorm,
     input logic  [`NE+1:0]          DivQe,
-    input logic  [`NE+1:0]          DivDenormShift,
+    input logic                     DivDenormShiftPos,
     input logic  [`NE+1:0]          NormSumExp,          // exponent of the normalized sum not taking into account denormal or zero results
     input logic                     FmaPreResultDenorm,    // is the result denormalized - calculated before LZA corection
     input logic                     FmaSZero,
@@ -66,5 +66,5 @@ module shiftcorrection(
 
     // the quotent is in the range [.5,2) if there is no early termination
     // if the quotent < 1 and not denormal then subtract 1 to account for the normalization shift
-    assign Qe = ((DivResDenorm)&~DivDenormShift[`NE+1]) ? (`NE+2)'(0) : DivQe - {(`NE+1)'(0), ~LZAPlus1};
+    assign Qe = (DivResDenorm & DivDenormShiftPos) ? '0 : DivQe - {(`NE+1)'(0), ~LZAPlus1};
 endmodule
\ No newline at end of file