From b460b780aa22854bd1639501e77d849931a16abd Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Sat, 21 Jan 2023 20:52:58 -0600
Subject: [PATCH] Working toolchain install script for ubuntu.

---
 bin/wally-tool-chain-install.sh | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh
index 2f6f1691..4c26bbf5 100755
--- a/bin/wally-tool-chain-install.sh
+++ b/bin/wally-tool-chain-install.sh
@@ -8,10 +8,10 @@ NUM_THREADS=1
 sudo mkdir -p $RISCV
 
 # UPDATE / UPGRADE
-#apt update
+apt update
 
 # INSTALL 
-#apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev
+apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev
 
 ln -sf /usr/bin/python3 /usr/bin/python  # this is unforunate.  gcc needs python but it looks specifically for python and not python3 or python2.
 
@@ -20,7 +20,7 @@ cd $RISCV
 git clone https://github.com/riscv/riscv-gnu-toolchain
 cd riscv-gnu-toolchain
 ./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
-make -j $(NUM_THREADS)
+make
 make install
 
 # elf2hex
@@ -44,16 +44,16 @@ cd $RISCV
 git clone --recurse-submodules https://github.com/qemu/qemu
 cd qemu
 ./configure --target-list=riscv64-softmmu --prefix=$RISCV 
-make -j $(NUM_THREADS)
+make 
 make install
 
 # Spike
 cd $RISCV
 git clone https://github.com/riscv-software-src/riscv-isa-sim
-mkdir riscv-isa-sim/build
+mkdir -p riscv-isa-sim/build
 cd riscv-isa-sim/build
 ../configure --prefix=$RISCV --enable-commitlog
-make -j $(NUM_THREADS)
+make 
 make install 
 cd ../arch_test_target/spike/device
 sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include
@@ -66,7 +66,7 @@ git clone https://github.com/Z3Prover/z3.git
 cd z3
 python scripts/mk_make.py
 cd build
-make  -j $(NUM_THREADS) 
+make 
 make install
 cd ../..
 pip3 install chardet==3.0.4
@@ -78,9 +78,9 @@ opam install sail -y
 eval $(opam config env)
 git clone https://github.com/riscv/sail-riscv.git
 cd sail-riscv
-make -j $(NUM_THREADS)
-ARCH=RV32 make -j $(NUM_THREADS)
-ARCH=RV64 make -j $(NUM_THREADS) 
+make 
+ARCH=RV32 make
+ARCH=RV64 make
 ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
 ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32