From b3bfdbad18b90fc169404f78fc2b918fe8cb0ae4 Mon Sep 17 00:00:00 2001
From: cturek <cturek@hmc.edu>
Date: Sun, 13 Nov 2022 23:02:43 +0000
Subject: [PATCH] Added flops for n and m, added B=0 signal

---
 pipelined/src/fpu/fdivsqrt/fdivsqrt.sv        |  8 ++++----
 .../src/fpu/fdivsqrt/fdivsqrtpostproc.sv      |  4 ++--
 pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 20 +++++++++++--------
 3 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
index f5cf2e3f..2362b987 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv
@@ -64,13 +64,13 @@ module fdivsqrt(
   logic Firstun;
   logic WZero;
   logic SpecialCaseM;
-  logic [`DIVBLEN:0] n, p, m, L;
-  logic OTFCSwap, ALTB;
+  logic [`DIVBLEN:0] n, m;
+  logic OTFCSwap, ALTB, BZero;
 
   fdivsqrtpreproc fdivsqrtpreproc(
     .clk, .DivStartE, .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), 
     .Sqrt(SqrtE), .Ym(YmE), .XZero(XZeroE), .X, .Dpreproc, 
-    .n, .p, .m, .L, .OTFCSwap, .ALTB,
+    .n, .m, .OTFCSwap, .ALTB, .BZero,
     .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E);
   fdivsqrtfsm fdivsqrtfsm(
     .clk, .reset, .FmtE, .XsE, .SqrtE, 
@@ -85,6 +85,6 @@ module fdivsqrt(
   fdivsqrtpostproc fdivsqrtpostproc(
     .WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, 
     .SqrtM, .SpecialCaseM, .RemOp(Funct3E[1]),
-    .MDUE, .n, .ALTB, .m,
+    .MDUE, .n, .ALTB, .m, .BZero,
     .QmM, .WZero, .DivSM);
 endmodule
\ No newline at end of file
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
index 44c7f901..716f1225 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv
@@ -38,7 +38,7 @@ module fdivsqrtpostproc(
   input  logic Firstun,
   input  logic SqrtM,
   input  logic SpecialCaseM,
-  input  logic RemOp, MDUE, ALTB,
+  input  logic RemOp, MDUE, ALTB, BZero,
   input  logic [`DIVBLEN:0] n, m,
   output logic [`DIVb:0] QmM, 
   output logic WZero,
@@ -70,7 +70,7 @@ module fdivsqrtpostproc(
   end 
   assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide
 
-
+  
 
   // Determine if sticky bit is negative
   assign W = WC + WS;
diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
index 0ee67019..3d2f529a 100644
--- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
+++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv
@@ -41,8 +41,8 @@ module fdivsqrtpreproc (
   input  logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B
 	input  logic [2:0] 	Funct3E, Funct3M,
 	input  logic MDUE, W64E,
-  output logic [`DIVBLEN:0] n, p, m, L,
-  output logic OTFCSwap, ALTB,
+  output logic [`DIVBLEN:0] n, m,
+  output logic OTFCSwap, ALTB, BZero,
   output logic [`NE+1:0] QeM,
   output logic [`DIVb+3:0] X,
   output logic [`DIVN-2:0] Dpreproc
@@ -58,8 +58,9 @@ module fdivsqrtpreproc (
   logic  [`XLEN-1:0] PosA, PosB;
   logic  As, Bs, OTFCSwapTemp;
   logic  [`XLEN-1:0] A64, B64;
+  logic  [`DIVBLEN:0] Calcn, Calcm;
   logic  [`DIVBLEN:0] ZeroDiff, IntBits, RightShiftX;
-  logic  [`DIVBLEN:0] pPlusr, pPrCeil;
+  logic  [`DIVBLEN:0] pPlusr, pPrCeil, p, L;
   logic  [`LOGRK-1:0] pPrTrunc;
   logic  [`DIVb+3:0] PreShiftX;
 
@@ -75,23 +76,24 @@ module fdivsqrtpreproc (
   
   assign PosA = As ? -A64 : A64;
   assign PosB = Bs ? -B64 : B64;
+  assign BZero = |ForwardedSrcBE;
 
   assign ZeroBufX = MDUE ? {PosA, {`DIVb-`XLEN{1'b0}}} : {Xm, {`DIVb-`NF-1{1'b0}}};
   assign ZeroBufY = MDUE ? {PosB, {`DIVb-`XLEN{1'b0}}} : {Ym, {`DIVb-`NF-1{1'b0}}};
   lzc #(`DIVb) lzcX (ZeroBufX, L);
-  lzc #(`DIVb) lzcY (ZeroBufY, m);
+  lzc #(`DIVb) lzcY (ZeroBufY, Calcm);
 
   assign PreprocX = Xm[`NF-1:0]<<L;
-  assign PreprocY = Ym[`NF-1:0]<<m;
+  assign PreprocY = Ym[`NF-1:0]<<Calcm;
 
-  assign ZeroDiff = m - L;
+  assign ZeroDiff = Calcm - L;
   assign ALTB = ZeroDiff[`DIVBLEN]; // A less than B
   assign p = ALTB ? '0 : ZeroDiff;
 
   assign pPlusr = (`DIVBLEN)'(`LOGR) + p;
   assign pPrTrunc = pPlusr[`LOGRK-1:0];
   assign pPrCeil = (pPlusr >> `LOGRK) + {{`DIVBLEN-1{1'b0}}, |(pPrTrunc)};
-  assign n = (pPrCeil << `LOGK) - 1;
+  assign Calcn = (pPrCeil << `LOGK) - 1;
   assign IntBits = (`DIVBLEN)'(`RK) + p;
   assign RightShiftX = (`DIVBLEN)'(`RK) - {{(`DIVBLEN-`RK){1'b0}}, IntBits[`RK-1:0]};
 
@@ -115,7 +117,9 @@ module fdivsqrtpreproc (
   // DIVRESLEN/(r*`DIVCOPIES)
   flopen #(`NE+2) expflop(clk, DivStartE, Qe, QeM);
   flopen #(1) swapflop(clk, DivStartE, OTFCSwapTemp, OTFCSwap);
-  expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .L, .m, .Qe);
+  flopen #(`DIVBLEN+1) nflop(clk, DivStartE, Calcn, n);
+  flopen #(`DIVBLEN+1) mflop(clk, DivStartE, Calcm, m);
+  expcalc expcalc(.Fmt, .Xe, .Ye, .Sqrt, .XZero, .L, .m(Calcm), .Qe);
 
 endmodule