From b2f4d4aaa7ca3757752e01663215a368f33841ba Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Tue, 20 Sep 2022 10:49:14 -0500
Subject: [PATCH] Added chip enables to sram.

---
 pipelined/src/generic/mem/bram1p1rw.sv | 17 ++++++++++-------
 pipelined/src/generic/mem/brom1p1r.sv  |  3 ++-
 pipelined/src/ifu/ifu.sv               |  4 ++--
 pipelined/src/ifu/irom.sv              |  4 ++--
 pipelined/src/lsu/dtim.sv              |  4 ++--
 pipelined/src/lsu/lsu.sv               |  4 ++--
 pipelined/src/uncore/ram_ahb.sv        |  2 +-
 pipelined/src/uncore/rom_ahb.sv        |  2 +-
 8 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/pipelined/src/generic/mem/bram1p1rw.sv b/pipelined/src/generic/mem/bram1p1rw.sv
index bdf52d69..d4759b0b 100644
--- a/pipelined/src/generic/mem/bram1p1rw.sv
+++ b/pipelined/src/generic/mem/bram1p1rw.sv
@@ -45,6 +45,7 @@ module bram1p1rw
 	//----------------------------------------------------------------------
 	) (
 	   input logic 					 clk,
+	   input logic 					 ce,
 	   input logic 					 we,
 	   input logic [NUM_COL-1:0] 	 bwe,
 	   input logic [ADDR_WIDTH-1:0]  addr,
@@ -105,13 +106,15 @@ end
   
 
   always @ (posedge clk) begin
-	dout <= RAM[addr];    
-	if(we) begin
-	  for(i=0;i<NUM_COL;i=i+1) begin
-		if(bwe[i]) begin
-		  RAM[addr][i*COL_WIDTH +: COL_WIDTH] <= din[i*COL_WIDTH +:COL_WIDTH];
-		end
-	  end
+    if(ce) begin
+	  dout <= RAM[addr];    
+	  if(we) begin
+	    for(i=0;i<NUM_COL;i=i+1) begin
+		  if(bwe[i]) begin
+		    RAM[addr][i*COL_WIDTH +: COL_WIDTH] <= din[i*COL_WIDTH +:COL_WIDTH];
+		  end
+	    end
+      end
 	end
   end
 endmodule // bytewrite_tdp_ram_rf
diff --git a/pipelined/src/generic/mem/brom1p1r.sv b/pipelined/src/generic/mem/brom1p1r.sv
index ef58f925..c55b9b1e 100644
--- a/pipelined/src/generic/mem/brom1p1r.sv
+++ b/pipelined/src/generic/mem/brom1p1r.sv
@@ -41,6 +41,7 @@ module brom1p1r
 	//----------------------------------------------------------------------
 	) (
 	   input logic 					 clk,
+	   input logic 					 ce,
 	   input logic [ADDR_WIDTH-1:0]  addr,
 	   output logic [DATA_WIDTH-1:0] dout
 	   );
@@ -48,7 +49,7 @@ module brom1p1r
   logic [DATA_WIDTH-1:0] 			 ROM [(2**ADDR_WIDTH)-1:0];
 
   always @ (posedge clk) begin
-	dout <= ROM[addr];    
+    if(ce) dout <= ROM[addr];    
   end
 
   if(PRELOAD_ENABLED) begin
diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index cde1e02b..ab783ad3 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -190,13 +190,13 @@ module ifu (
     logic [`PA_BITS-1:0] IROMAdr;
     logic             IROMAccessRW;
     /* verilator lint_off WIDTH */
-    assign IROMAdr = CPUBusy | reset ? PCFSpill : PCNextFSpill; // zero extend or contract to PA_BITS
+    assign IROMAdr = reset ? PCFSpill : PCNextFSpill; // zero extend or contract to PA_BITS
     /* verilator lint_on WIDTH */
  
     adrdec iromdec(PCFExt, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, 1'b1, 2'b10, 4'b1111, SelIROM);
     //assign NonIROMMemRWM = {~SelIROM, 1'b0};
     assign NonIROMMemRWM = 2'b10;
-    irom irom(.clk, .reset, .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF));
+    irom irom(.clk, .reset, .ce(~CPUBusy), .Adr(CPUBusy | reset ? PCFSpill : PCNextFSpill), .ReadData(FinalInstrRawF));
  
   end else begin
     assign SelIROM = 0; assign NonIROMMemRWM = 2'b10;
diff --git a/pipelined/src/ifu/irom.sv b/pipelined/src/ifu/irom.sv
index c35d602d..79ceca2d 100644
--- a/pipelined/src/ifu/irom.sv
+++ b/pipelined/src/ifu/irom.sv
@@ -30,7 +30,7 @@
 `include "wally-config.vh"
 
 module irom(
-  input logic               clk, reset,
+  input logic               clk, reset, ce,
   input logic [`XLEN-1:0]   Adr,
   output logic [31:0]  ReadData
 );
@@ -38,6 +38,6 @@ module irom(
   localparam ADDR_WDITH = $clog2(`IROM_RANGE/8); 
   localparam OFFSET = $clog2(`LLEN/8);
 
-  brom1p1r #(ADDR_WDITH, 32) rom(.clk, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
+  brom1p1r #(ADDR_WDITH, 32) rom(.clk, .ce, .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadData));
 endmodule  
   
diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv
index 1d006ae2..5cbf7793 100644
--- a/pipelined/src/lsu/dtim.sv
+++ b/pipelined/src/lsu/dtim.sv
@@ -30,7 +30,7 @@
 `include "wally-config.vh"
 
 module dtim(
-  input logic               clk, reset,
+  input logic               clk, reset, ce,
   input logic [1:0]         MemRWM,
   input logic [`PA_BITS-1:0]   Adr,
   input logic               TrapM, 
@@ -47,6 +47,6 @@ module dtim(
   assign we = MemRWM[0]  & ~TrapM;  // have to ignore write if Trap.
 
   bram1p1rw #(`LLEN/8, 8, ADDR_WDITH) 
-    ram(.clk, .we, .bwe(ByteMaskM), .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
+    ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
 endmodule  
   
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 599c6803..3761a31a 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -213,7 +213,7 @@ module lsu (
     // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
     // Don't perform size checking on DTIM
     /* verilator lint_off WIDTH */
-    assign MemStage = CPUBusy | MemRWM[0] | reset; // 1 = M stage; 0 = E stage
+    assign MemStage = MemRWM[0] | reset; // 1 = M stage; 0 = E stage
     assign DTIMAdr = MemStage ? IEUAdrExtM : IEUAdrExtE; // zero extend or contract to PA_BITS
     /* verilator lint_on WIDTH */
     assign DTIMAccessRW = |MemRWM;
@@ -222,7 +222,7 @@ module lsu (
     //assign NonDTIMMemRWM = MemRWM & ~{2{SelDTIM}}; // disable access to bus-based memory map when DTIM is selected
     assign NonDTIMMemRWM = MemRWM; // *** fix
 
-    dtim dtim(.clk, .reset, .MemRWM,
+    dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM,
               .Adr(DTIMAdr),
               .TrapM, .WriteDataM(LSUWriteDataM), 
               .ReadDataWordM(ReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv
index b133b47f..d33e5ede 100644
--- a/pipelined/src/uncore/ram_ahb.sv
+++ b/pipelined/src/uncore/ram_ahb.sv
@@ -74,7 +74,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) (
 
   // single-ported RAM
   bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH, `FPGA)
-    memory(.clk(HCLK), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
+    memory(.clk(HCLK), .ce(1'b1), .we(memwriteD), .bwe(HWSTRB), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
 
   // use this to add arbitrary latency to ram. Helps test AHB controller correctness
   if(`RAM_LATENCY > 0) begin
diff --git a/pipelined/src/uncore/rom_ahb.sv b/pipelined/src/uncore/rom_ahb.sv
index bbcc5888..9128efb8 100644
--- a/pipelined/src/uncore/rom_ahb.sv
+++ b/pipelined/src/uncore/rom_ahb.sv
@@ -49,6 +49,6 @@ module rom_ahb #(parameter BASE=0, RANGE = 65535) (
 
   // single-ported ROM
   brom1p1r #(ADDR_WIDTH, `XLEN, `FPGA)
-    memory(.clk(HCLK), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));  
+    memory(.clk(HCLK), .ce(1'b1), .addr(HADDR[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRom));  
 endmodule