From b21e36a7886d0a6fc80f7ad010964990009be6ae Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 21 Sep 2022 04:55:43 -0700 Subject: [PATCH] Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc --- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 6 +++--- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 9 ++++++--- pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 4 ++-- pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 2 ++ pipelined/src/fpu/postproc/divshiftcalc.sv | 2 ++ 5 files changed, 15 insertions(+), 8 deletions(-) diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 49ecb5a1..43f7687c 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -61,7 +61,7 @@ module fdivsqrt( logic [`DIVb+1:0] FirstC; logic Firstun; logic WZero; - logic SpecialCase; + logic SpecialCaseM; fdivsqrtpreproc fdivsqrtpreproc( .clk, .DivStart(DivStartE), .Xm(XmE), .QeM, .Xe(XeE), .Fmt(FmtE), .Ye(YeE), @@ -70,11 +70,11 @@ module fdivsqrt( .clk, .reset, .FmtE, .XsE, .SqrtE, .DivBusy, .DivStart(DivStartE),.StallE, .StallM, .DivDone, .XZeroE, .YZeroE, .XNaNE, .YNaNE, - .XInfE, .YInfE, .WZero, .SpecialCase); + .XInfE, .YInfE, .WZero, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( .clk, .Firstun, .D, .FirstU, .FirstUM, .FirstC, .SqrtE, .SqrtM, .X,.Dpreproc, .FirstWS(WS), .FirstWC(WC), .NextWSN, .NextWCN, .DivStart(DivStartE), .Xe(XeE), .Ye(YeE), .XZeroE, .YZeroE, .DivBusy); - fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCase, .QmM, .WZero, .DivSM); + fdivsqrtpostproc fdivsqrtpostproc(.WS, .WC, .D, .FirstU, .FirstUM, .FirstC, .Firstun, .SqrtM, .SpecialCaseM, .QmM, .WZero, .DivSM); endmodule \ No newline at end of file diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 0eef83eb..3a71819e 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -45,7 +45,7 @@ module fdivsqrtfsm( input logic WZero, output logic DivDone, output logic DivBusy, - output logic SpecialCase + output logic SpecialCaseM ); typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype; @@ -53,9 +53,12 @@ module fdivsqrtfsm( logic [`DURLEN-1:0] step; logic [`DURLEN-1:0] cycles; + logic SpecialCaseE; // terminate immediately on special cases - assign SpecialCase = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); + assign SpecialCaseE = XZeroE | (YZeroE&~SqrtE) | XInfE | YInfE | XNaNE | YNaNE | (XsE&SqrtE); + + flopenr #(1) SpecialCaseReg(clk, reset, ~StallM, SpecialCaseE, SpecialCaseM); // DIVN = `NF+3 // NS = NF + 1 @@ -103,7 +106,7 @@ module fdivsqrtfsm( step <= cycles; // *** this should be adjusted to depend on the precision; sqrt should use one fewer step becasue firststep=1 // $display("Setting Nf = %d fbits %d cycles = %d FmtE %d FPSIZES = %d Q_NF = %d num = %d denom = %d\n", Nf, fbits, cycles, FmtE, `FPSIZES, `Q_NF, // (fbits +(`LOGR*`DIVCOPIES)-1), (`LOGR*`DIVCOPIES)); - if (SpecialCase) state <= #1 DONE; + if (SpecialCaseE) state <= #1 DONE; else state <= #1 BUSY; end else if (DivDone) begin if (StallM) state <= #1 DONE; diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 564b0766..e0acd0ed 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -37,7 +37,7 @@ module fdivsqrtpostproc( input logic [`DIVb+1:0] FirstC, input logic Firstun, input logic SqrtM, - input logic SpecialCase, + input logic SpecialCaseM, output logic [`DIVb:0] QmM, output logic WZero, output logic DivSM @@ -65,7 +65,7 @@ module fdivsqrtpostproc( end else begin assign WZero = weq0; end - assign DivSM = ~WZero & ~(SpecialCase & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide + assign DivSM = ~WZero & ~(SpecialCaseM & SqrtM); // ***unsure why SpecialCaseM has to be gated by SqrtM, but otherwise fails regression on divide // Determine if sticky bit is negative assign W = WC+WS; diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index 9b357862..2a6f6a9e 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -61,6 +61,8 @@ module fdivsqrtpreproc ( assign SqrtX = Xe[0]^XZeroCnt[0] ? {1'b0, ~XZero, PreprocX} : {~XZero, PreprocX, 1'b0}; assign DivX = {3'b000, ~XZero, PreprocX, {`DIVb-`NF{1'b0}}}; + + // *** explain why X is shifted between radices if (`RADIX == 2) assign X = Sqrt ? {3'b111, SqrtX, {`DIVb-1-`NF{1'b0}}} : DivX; else assign X = Sqrt ? {2'b11, SqrtX, {`DIVb-1-`NF{1'b0}}, 1'b0} : DivX; assign Dpreproc = {PreprocY, {`DIVN-1-`NF{1'b0}}}; diff --git a/pipelined/src/fpu/postproc/divshiftcalc.sv b/pipelined/src/fpu/postproc/divshiftcalc.sv index d5525576..cb671a80 100644 --- a/pipelined/src/fpu/postproc/divshiftcalc.sv +++ b/pipelined/src/fpu/postproc/divshiftcalc.sv @@ -73,6 +73,8 @@ module divshiftcalc( assign DivDenormShiftAmt = DivDenormShiftPos ? DivDenormShift[`LOGNORMSHIFTSZ-1:0] : '0; assign DivShiftAmt = DivResDenorm ? DivDenormShiftAmt : NormShift; + // *** explain why radix 4 division needs a left shift by 1 + // *** can this shift be moved into the shiftcorrection logic? if (`RADIX == 4) assign DivShiftIn = Sqrt ? {{`NF{1'b0}}, DivQm, {`NORMSHIFTSZ-`DIVb+1-`NF{1'b0}}} : {{`NF{1'b0}}, DivQm[`DIVb-1:0], {`NORMSHIFTSZ-`DIVb+2-`NF{1'b0}}}; else