From 9b2236b2a0e163721ae2cdc822aede24b8d57ae0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 16 Nov 2022 15:35:34 -0600 Subject: [PATCH 1/2] Progress on the cache replacement policy implementation. --- pipelined/src/cache/cachereplacementpolicy.sv | 82 ++++++------------- 1 file changed, 23 insertions(+), 59 deletions(-) diff --git a/pipelined/src/cache/cachereplacementpolicy.sv b/pipelined/src/cache/cachereplacementpolicy.sv index 42f0b441..1f7a65fc 100644 --- a/pipelined/src/cache/cachereplacementpolicy.sv +++ b/pipelined/src/cache/cachereplacementpolicy.sv @@ -56,9 +56,8 @@ module cachereplacementpolicy logic [NUMWAYS-2:0] cEn; -/* -----\/----- EXCLUDED -----\/----- // proposed generic solution - +/* -----\/----- EXCLUDED -----\/----- binencoder #(NUMWAYS) encoder(HitWay, HitWayEnc); // bit duplication @@ -70,11 +69,7 @@ module cachereplacementpolicy assign HitWayExpand[StartIndex : EndIndex] = {{DuplicationFactor}{HitWayEnc[row]}}; end - genvar r, a,s; - //localparam s = NUMWAYS-2; - - assign cEn[NUMWAYS-2] = '1; for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables localparam p = NUMWAYS - s; @@ -86,75 +81,44 @@ module cachereplacementpolicy assign cEn[t1] = cEn[s] & HitWayEnc[r]; end - mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, HitWayExpand, cEn, NewReplacement); + mux2 #(1) LRUMuxes[NUMWAYS-2:0](LineReplacementBits, ~HitWayExpand, cEn, NewReplacement); + + always_ff @(posedge clk) begin + if (reset) for (int set = 0; set < NUMLINES; set++) ReplacementBits[set] <= '0; + if(ce) begin + if (LRUWriteEn) begin + ReplacementBits[RAdr] <= NewReplacement; + LineReplacementBits <= #1 NewReplacement; + end else begin + LineReplacementBits <= #1 ReplacementBits[RAdr]; + end + end + end + + localparam HalfPoint = (2**$clog2(NUMWAYS)) / 2; + logic [NUMWAYS-2:0] ivec; + + + assign ivec[HalfPoint-1:0] = LineReplacementBits[HalfPoint-1:0]; + for(r = NUMWAYS-2; r >= HalfPoint; r--) begin + + end assign VictimWay[0] = ~LineReplacementBits[2] & ~LineReplacementBits[0]; assign VictimWay[1] = ~LineReplacementBits[2] & LineReplacementBits[0]; assign VictimWay[2] = LineReplacementBits[2] & ~LineReplacementBits[1]; assign VictimWay[3] = LineReplacementBits[2] & LineReplacementBits[1]; - -----/\----- EXCLUDED -----/\----- */ - - -/* -----\/----- EXCLUDED -----\/----- -// logic [NUMWAYS/2-1:0] rawEn [LOGNUMWAYS-1:0]; - for(r = LOGNUMWAYS-1; r >= 0; r--) begin - localparam integer g = 2**(LOGNUMWAYS-r-1); - for(a = g-1; a > 0; a--) begin - localparam t0 = s - 2**(g-1); - localparam t1 = t0 - 1; - localparam s = s - 1; - assign cEn[t0] = cEn[s] & ~HitWayEnc[r]; - assign cEn[t1] = cEn[s] & HitWayEnc[r]; - end - -----/\----- EXCLUDED -----/\----- */ -/* -----\/----- EXCLUDED -----\/----- - for(a = g-1; a > 0; a--) begin - localparam t0 = s - 2**(g-1); - localparam t1 = t0 - 1; - s = s - 1; - end - end -----/\----- EXCLUDED -----/\----- */ -/* -----\/----- EXCLUDED -----\/----- - always_comb begin - for(r = LOGNUMWAYS-1; r > 0; r--) begin - localparam g = 2**(LOGNUMWAYS-r-1); - for(a = g-1; a > 0; a--) begin - localparam t0 = s - 2**(g-1); - localparam t1 = t0 - 1; - s = s - 1; - end - end - end - -----/\----- EXCLUDED -----/\----- */ -/* -----\/----- EXCLUDED -----\/----- - - genvar row2; - logic [LOGNUMWAYS-1:0] indices [LOGNUMWAYS-1:0]; - integer jindex; - always_comb begin - rawEn[LOGNUMWAYS-1] = 1; - for(jindex = 0; jindex < LOGNUMWAYS-1; jindex++) begin - rawEn[jindex] = 0; - rawEn[jindex][~(HitWayEnc>>(jindex+1))] = 1; - - //cEn[2**(LOGNUMWAYS-jindex)-1+jindex:0] = rawEn[jindex][2**(LOGNUMWAYS-jindex)-1:0]; - - end - end - -----/\----- EXCLUDED -----/\----- */ // *** high priority to clean up -/* -----\/----- EXCLUDED -----\/----- initial begin assert (NUMWAYS == 2 || NUMWAYS == 4) else $error("Only 2 or 4 ways supported"); end - -----/\----- EXCLUDED -----/\----- */ // Replacement Bits: Register file // Needs to be resettable for simulation, but could omit reset for synthesis *** From ac0f6ddb7bf3309d8613aa6885542032ae18e15f Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 16 Nov 2022 15:38:37 -0600 Subject: [PATCH 2/2] I found the issue with the cache changes. FlushW is not asserted for all TrapM. Ecall and Ebreak don't flush the W stage. However the ifu's bus controllable must disable the BusRW for all traps. --- pipelined/src/ifu/ifu.sv | 6 +++--- pipelined/src/wally/wallypipelinedcore.sv | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index ee271fe1..17af36ec 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -221,7 +221,7 @@ module ifu ( cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) - icache(.clk, .reset, .FlushStage(FlushW), .CPUBusy, + icache(.clk, .reset, .FlushStage(TrapM), .CPUBusy, .FetchBuffer, .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheBusRW, @@ -238,7 +238,7 @@ module ifu ( ahbcacheinterface #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) ahbcacheinterface(.HCLK(clk), .HRESETn(~reset), .HRDATA, - .Flush(FlushW), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), + .Flush(TrapM), .CacheBusRW, .HSIZE(IFUHSIZE), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .HWSTRB(), .Funct3(3'b010), .HADDR(IFUHADDR), .HREADY(IFUHREADY), .HWRITE(IFUHWRITE), .CacheBusAdr(ICacheBusAdr), .BeatCount(), .Cacheable(CacheableF), .SelBusBeat(), .WriteDataM('0), .CacheBusAck(ICacheBusAck), .HWDATA(), .CacheableOrFlushCacheM(1'b0), .CacheReadDataWordM('0), @@ -257,7 +257,7 @@ module ifu ( // assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{SelIROM, SelIROM}; assign IFUHSIZE = 3'b010; - ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(FlushW), .HRESETn(~reset), .HREADY(IFUHREADY), + ahbinterface #(0) ahbinterface(.HCLK(clk), .Flush(TrapM), .HRESETn(~reset), .HREADY(IFUHREADY), .HRDATA(HRDATA), .HTRANS(IFUHTRANS), .HWRITE(IFUHWRITE), .HWDATA(), .HWSTRB(), .BusRW, .ByteMask(), .WriteData('0), .CPUBusy, .BusStall, .BusCommitted(BusCommittedF), .FetchBuffer(FetchBuffer)); diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index bce17875..8c41d62c 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -246,7 +246,7 @@ module wallypipelinedcore ( lsu lsu( .clk, .reset, .StallM, .FlushM, .StallW, - .FlushW, + .FlushW(TrapM), // CPU interface .MemRWM, .Funct3M, .Funct7M(InstrM[31:25]), .AtomicM,