From b0f199b57412c58e53743c8d9f484f0ec8736f9f Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 4 Jul 2021 18:05:22 -0400 Subject: [PATCH] Fixed TLB_ENTRIES merge conflict and handling of global PTEs --- wally-pipelined/src/lsu/lsu.sv | 2 +- wally-pipelined/src/mmu/tlb.sv | 5 +++-- wally-pipelined/src/mmu/tlbcam.sv | 2 +- wally-pipelined/src/mmu/tlbcamline.sv | 4 ++-- wally-pipelined/src/mmu/tlbram.sv | 4 ++-- wally-pipelined/src/mmu/tlbramline.sv | 6 ++++-- 6 files changed, 13 insertions(+), 10 deletions(-) diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index ee2bf31e..8d4df6ec 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -217,7 +217,7 @@ module lsu ( - mmu #(.TLB_ENTRIES(`DTLB_ENTRY_BITS), .IMMU(0)) + mmu #(.TLB_ENTRIES(`DTLB_ENTRIES), .IMMU(0)) dmmu(.TLBAccessType(MemRWMtoLSU), .VirtualAddress(MemAdrMtoLSU), .Size(Funct3MtoLSU[1:0]), diff --git a/wally-pipelined/src/mmu/tlb.sv b/wally-pipelined/src/mmu/tlb.sv index 644e56a5..75021265 100644 --- a/wally-pipelined/src/mmu/tlb.sv +++ b/wally-pipelined/src/mmu/tlb.sv @@ -95,7 +95,7 @@ module tlb #(parameter TLB_ENTRIES = 8, logic [`SVMODE_BITS-1:0] SvMode; logic [1:0] EffectivePrivilegeMode; // privilege mode, possibly modified by MPRV - logic [TLB_ENTRIES-1:0] ReadLines, WriteLines, WriteEnables, Global; // used as the one-hot encoding of WriteIndex + logic [TLB_ENTRIES-1:0] ReadLines, WriteLines, WriteEnables, PTE_G; // used as the one-hot encoding of WriteIndex // Sections of the virtual and physical addresses logic [`VPN_BITS-1:0] VirtualPageNumber; @@ -107,7 +107,7 @@ module tlb #(parameter TLB_ENTRIES = 8, logic [7:0] PTEAccessBits; logic [11:0] PageOffset; - logic PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits + logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R; // Useful PTE Control Bits logic [1:0] HitPageType; logic CAMHit; logic [`ASID_BITS-1:0] ASID; @@ -153,6 +153,7 @@ module tlb #(parameter TLB_ENTRIES = 8, tlbphysicalpagemask PageMask(VirtualPageNumber, PhysicalPageNumber, HitPageType, PhysicalPageNumberMixed); // unswizzle useful PTE bits + assign {PTE_D, PTE_A} = PTEAccessBits[7:6]; assign {PTE_U, PTE_X, PTE_W, PTE_R} = PTEAccessBits[4:1]; // Check whether the access is allowed, page faulting if not. diff --git a/wally-pipelined/src/mmu/tlbcam.sv b/wally-pipelined/src/mmu/tlbcam.sv index 996620cf..0ad81605 100644 --- a/wally-pipelined/src/mmu/tlbcam.sv +++ b/wally-pipelined/src/mmu/tlbcam.sv @@ -36,7 +36,7 @@ module tlbcam #(parameter TLB_ENTRIES = 8, input logic [1:0] PageTypeWriteVal, input logic TLBFlush, input logic [TLB_ENTRIES-1:0] WriteEnables, - input logic [TLB_ENTRIES-1:0] Global + input logic [TLB_ENTRIES-1:0] PTE_G, input logic [`ASID_BITS-1:0] ASID, output logic [TLB_ENTRIES-1:0] ReadLines, output logic [1:0] HitPageType, diff --git a/wally-pipelined/src/mmu/tlbcamline.sv b/wally-pipelined/src/mmu/tlbcamline.sv index e0381ed6..ebb9ce3f 100644 --- a/wally-pipelined/src/mmu/tlbcamline.sv +++ b/wally-pipelined/src/mmu/tlbcamline.sv @@ -34,7 +34,7 @@ module tlbcamline #(parameter KEY_BITS = 20, input logic [`VPN_BITS-1:0] VirtualPageNumber, // The requested page number to compare against the key input logic [`ASID_BITS-1:0] ASID, input logic WriteEnable, // Write a new entry to this line - input logic Global, + input logic PTE_G, input logic [1:0] PageTypeWriteVal, input logic TLBFlush, // Flush this line (set valid to 0) output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one? @@ -57,7 +57,7 @@ module tlbcamline #(parameter KEY_BITS = 20, logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1; logic MatchASID, Match0, Match1; - assign MatchASID = (ASID == Key_ASID) | Global; + assign MatchASID = (ASID == Key_ASID) | PTE_G; generate if (`XLEN == 32) begin diff --git a/wally-pipelined/src/mmu/tlbram.sv b/wally-pipelined/src/mmu/tlbram.sv index 0fc50854..98650d0b 100644 --- a/wally-pipelined/src/mmu/tlbram.sv +++ b/wally-pipelined/src/mmu/tlbram.sv @@ -33,14 +33,14 @@ module tlbram #(parameter TLB_ENTRIES = 8) ( input logic [TLB_ENTRIES-1:0] ReadLines, WriteEnables, output logic [`PPN_BITS-1:0] PhysicalPageNumber, output logic [7:0] PTEAccessBits, - output logic [TLB_ENTRIES-1:0] Global + output logic [TLB_ENTRIES-1:0] PTE_G ); logic [`XLEN-1:0] RamRead[TLB_ENTRIES-1:0]; logic [`XLEN-1:0] PageTableEntry; // Generate a flop for every entry in the RAM - tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead); + tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, ReadLines, WriteEnables, PTEWriteVal, RamRead, PTE_G); assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE assign PTEAccessBits = PageTableEntry[7:0]; diff --git a/wally-pipelined/src/mmu/tlbramline.sv b/wally-pipelined/src/mmu/tlbramline.sv index 77a0e89b..089f9366 100644 --- a/wally-pipelined/src/mmu/tlbramline.sv +++ b/wally-pipelined/src/mmu/tlbramline.sv @@ -29,10 +29,12 @@ module tlbramline #(parameter WIDTH) (input logic clk, reset, input logic re, we, input logic [WIDTH-1:0] d, - output logic [WIDTH-1:0] q); + output logic [WIDTH-1:0] q, + output logic PTE_G); logic [WIDTH-1:0] line; - + flopenr #(`XLEN) pteflop(clk, reset, we, d, line); assign q = re ? line : 0; + assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching endmodule \ No newline at end of file