diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 4c7180a3..b546a82b 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -36,7 +36,7 @@ module dcache input logic [6:0] Funct7M, input logic [1:0] AtomicM, input logic FlushDCacheM, - input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [11:0] IEUAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] MemPAdrM, // physical address input logic [11:0] VAdr, // when hptw writes dtlb we use this address to index SRAM. @@ -147,7 +147,7 @@ module dcache // Read Path CPU (IEU) side mux4 #(INDEXLEN) - AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + AdrSelMux(.d0(IEUAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(VAdr[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d2(MemPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d3(FlushAdr), diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index ef35f2f5..d0a046e1 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -43,14 +43,14 @@ module datapath ( input logic [`XLEN-1:0] PCE, input logic [`XLEN-1:0] PCLinkE, output logic [2:0] FlagsE, - output logic [`XLEN-1:0] PCTargetE, + output logic [`XLEN-1:0] IEUAdrE, output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B // Memory stage signals input logic StallM, FlushM, input logic FWriteIntM, input logic [`XLEN-1:0] FIntResM, output logic [`XLEN-1:0] SrcAM, - output logic [`XLEN-1:0] WriteDataM, MemAdrM, MemAdrE, + output logic [`XLEN-1:0] WriteDataM, // Writeback stage signals input logic StallW, FlushW, input logic FWriteIntW, @@ -80,7 +80,6 @@ module datapath ( logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; logic [`XLEN-1:0] WriteDataE; - logic [`XLEN-1:0] AddressE; // Memory stage signals logic [`XLEN-1:0] IEUResultM; logic [`XLEN-1:0] ResultM; @@ -111,16 +110,13 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ExtImmE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, AddressE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ExtImmE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); - assign MemAdrE = AddressE; // *** clean up this naming - assign PCTargetE = AddressE; // *** clean up this naming // Memory stage pipeline register flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM); - flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, MemAdrE, MemAdrM); flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, WriteDataE, WriteDataM); flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); mux2 #(`XLEN) resultmuxM(IEUResultM, FIntResM, FWriteIntM, ResultM); diff --git a/wally-pipelined/src/ieu/ieu.sv b/wally-pipelined/src/ieu/ieu.sv index 4619b337..101ca4da 100644 --- a/wally-pipelined/src/ieu/ieu.sv +++ b/wally-pipelined/src/ieu/ieu.sv @@ -37,7 +37,7 @@ module ieu ( input logic FWriteIntE, input logic IllegalFPUInstrE, input logic [`XLEN-1:0] FWriteDataE, - output logic [`XLEN-1:0] PCTargetE, + output logic [`XLEN-1:0] IEUAdrE, output logic MulDivE, W64E, output logic [2:0] Funct3E, output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B @@ -49,7 +49,7 @@ module ieu ( output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] AtomicE, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU - output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU + output logic [`XLEN-1:0] WriteDataM, // Address and write data to LSU output logic [2:0] Funct3M, // size and signedness to LSU output logic [`XLEN-1:0] SrcAM, // to privilege and fpu @@ -127,11 +127,11 @@ module ieu ( .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .IllegalFPUInstrE, .FWriteDataE, .PCE, .PCLinkE, .FlagsE, - .PCTargetE, + .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B // Memory stage signals .StallM, .FlushM, .FWriteIntM, .FIntResM, - .SrcAM, .WriteDataM, .MemAdrM, .MemAdrE, + .SrcAM, .WriteDataM, // Writeback stage signals .StallW, .FlushW, .FWriteIntW, .RegWriteW, .SquashSCW, .ResultSrcW, .ReadDataW, diff --git a/wally-pipelined/src/ifu/bpred.sv b/wally-pipelined/src/ifu/bpred.sv index 3121e725..56308b1d 100644 --- a/wally-pipelined/src/ifu/bpred.sv +++ b/wally-pipelined/src/ifu/bpred.sv @@ -45,7 +45,7 @@ module bpred // *** the specifics of how this is encode is subject to change. input logic PCSrcE, // AKA Branch Taken // Signals required to check the branch prediction accuracy. - input logic [`XLEN-1:0] PCTargetE, // The branch destination if the branch is taken. + input logic [`XLEN-1:0] IEUAdrE, // The branch destination if the branch is taken. input logic [`XLEN-1:0] PCD, // The address the branch predictor took. input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) input logic [4:0] InstrClassE, @@ -165,7 +165,7 @@ module bpred // update .UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE), .UpdatePC(PCE), - .UpdateTarget(PCTargetE), + .UpdateTarget(IEUAdrE), .UpdateInvalid(PredictionInstrClassWrongE), .UpdateInstrClass(InstrClassE)); @@ -218,7 +218,7 @@ module bpred // Check the prediction makes execution. // first check if the target or fallthrough address matches what was predicted. - assign TargetWrongE = PCTargetE != PCD; + assign TargetWrongE = IEUAdrE != PCD; assign FallThroughWrongE = PCLinkE != PCD; // If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected // Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index 09322609..8bc8a185 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -40,7 +40,7 @@ module ifu ( // Execute output logic [`XLEN-1:0] PCLinkE, input logic PCSrcE, - input logic [`XLEN-1:0] PCTargetE, + input logic [`XLEN-1:0] IEUAdrE, output logic [`XLEN-1:0] PCE, output logic BPPredWrongE, // Mem @@ -223,7 +223,7 @@ module ifu ( .SelBPPredF(SelBPPredF), .PCE(PCE), .PCSrcE(PCSrcE), - .PCTargetE(PCTargetE), + .IEUAdrE(IEUAdrE), .PCD(PCD), .PCLinkE(PCLinkE), .InstrClassE(InstrClassE), @@ -242,8 +242,8 @@ module ifu ( assign BPPredClassNonCFIWrongE = 1'b0; end endgenerate - // The true correct target is PCTargetE if PCSrcE is 1 else it is the fall through PCLinkE. - assign PCCorrectE = PCSrcE ? PCTargetE : PCLinkE; + // The true correct target is IEUAdrE if PCSrcE is 1 else it is the fall through PCLinkE. + assign PCCorrectE = PCSrcE ? IEUAdrE : PCLinkE; // pcadder // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index 791e4d4a..6fcf4013 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -49,9 +49,9 @@ module lsu output logic DCacheAccess, // address and write data - input logic [`XLEN-1:0] MemAdrM, - input logic [`XLEN-1:0] MemAdrE, - input logic [`XLEN-1:0] WriteDataM, + input logic [`XLEN-1:0] IEUAdrE, + output logic [`XLEN-1:0] MemAdrM, + input logic [`XLEN-1:0] WriteDataM, output logic [`XLEN-1:0] ReadDataM, // cpu privilege @@ -129,6 +129,8 @@ module lsu assign AnyCPUReqM = (|MemRWM) | (|AtomicM); + flopenrc #(`XLEN) AddressMReg(clk, reset, FlushM, ~StallM, IEUAdrE, MemAdrM); + // *** add generate to conditionally create hptw, lsuArb, and mmu // based on `MEM_VIRTMEM hptw hptw(.clk(clk), @@ -169,7 +171,7 @@ module lsu .Funct3M(Funct3M), .AtomicM(AtomicM), .MemAdrM(MemAdrM), - .MemAdrE(MemAdrE[11:0]), + .IEUAdrE(IEUAdrE[11:0]), .CommittedM(CommittedM), .PendingInterruptM(PendingInterruptM), .StallW(StallW), @@ -251,7 +253,7 @@ module lsu .Funct7M(Funct7M), .FlushDCacheM, .AtomicM(AtomicMtoDCache), - .MemAdrE(MemAdrEtoDCache), + .IEUAdrE(MemAdrEtoDCache), .MemPAdrM(MemPAdrM), .VAdr(MemAdrM[11:0]), .WriteDataM(WriteDataM), diff --git a/wally-pipelined/src/lsu/lsuArb.sv b/wally-pipelined/src/lsu/lsuArb.sv index c0647c2b..be73b085 100644 --- a/wally-pipelined/src/lsu/lsuArb.sv +++ b/wally-pipelined/src/lsu/lsuArb.sv @@ -40,7 +40,7 @@ module lsuArb input logic [2:0] Funct3M, input logic [1:0] AtomicM, input logic [`XLEN-1:0] MemAdrM, - input logic [11:0] MemAdrE, + input logic [11:0] IEUAdrE, input logic StallW, input logic PendingInterruptM, // to CPU @@ -85,7 +85,7 @@ module lsuArb assign AtomicMtoDCache = SelPTW ? 2'b00 : AtomicM; assign MemAdrMExt = {2'b00, MemAdrM}; assign MemPAdrMtoDCache = SelPTW ? TranslationPAdrM : MemAdrMExt[`PA_BITS-1:0]; - assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : MemAdrE[11:0]; + assign MemAdrEtoDCache = SelPTW ? TranslationPAdrE[11:0] : IEUAdrE[11:0]; assign StallWtoDCache = SelPTW ? 1'b0 : StallW; // always block interrupts when using the hardware page table walker. assign CommittedM = SelPTW ? 1'b1 : CommittedMfromDCache; diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv index 4e8dbc47..13c2e77a 100644 --- a/wally-pipelined/src/wally/wallypipelinedhart.sv +++ b/wally-pipelined/src/wally/wallypipelinedhart.sv @@ -68,7 +68,6 @@ module wallypipelinedhart ( (* mark_debug = "true" *) logic [31:0] InstrM; logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; - logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] PrivilegedNextPCM; (* mark_debug = "true" *) logic [1:0] MemRWM; @@ -122,7 +121,7 @@ module wallypipelinedhart ( // cpu lsu interface logic [2:0] Funct3M; - logic [`XLEN-1:0] MemAdrE; + logic [`XLEN-1:0] IEUAdrE; (* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM; (* mark_debug = "true" *) logic [`XLEN-1:0] MemAdrM; (* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM; @@ -170,7 +169,7 @@ module wallypipelinedhart ( .InstrReadF, .ICacheStallF, // Execute - .PCLinkE, .PCSrcE, .PCTargetE, .PCE, + .PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, // Mem @@ -209,7 +208,7 @@ module wallypipelinedhart ( // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .IllegalFPUInstrE, - .FWriteDataE, .PCTargetE, .MulDivE, .W64E, + .FWriteDataE, .IEUAdrE, .MulDivE, .W64E, .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B //.SrcAE, .SrcBE, .FWriteIntM, @@ -219,7 +218,7 @@ module wallypipelinedhart ( .MemRWM, // read/write control goes to LSU .AtomicE, // atomic control goes to LSU .AtomicM, // atomic control goes to LSU - .MemAdrM, .MemAdrE, .WriteDataM, // Address and write data to LSU + .WriteDataM, // Write data to LSU .Funct3M, // size and signedness to LSU .SrcAM, // to privilege and fpu .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, @@ -248,7 +247,7 @@ module wallypipelinedhart ( .CommittedM, .DCacheMiss, .DCacheAccess, .SquashSCW, //.DataMisalignedM(DataMisalignedM), - .MemAdrE, .MemAdrM, .WriteDataM, + .IEUAdrE, .MemAdrM, .WriteDataM, .ReadDataM, .FlushDCacheM, // connected to ahb (all stay the same) .DCtoAHBPAdrM, .DCtoAHBReadM, .DCtoAHBWriteM, .DCfromAHBAck, diff --git a/wally-pipelined/testbench/testbench-linux.sv b/wally-pipelined/testbench/testbench-linux.sv index b09b19aa..a64ca434 100644 --- a/wally-pipelined/testbench/testbench-linux.sv +++ b/wally-pipelined/testbench/testbench-linux.sv @@ -100,7 +100,7 @@ module testbench(); flopenrc #(`XLEN) PCWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ifu.PCM, PCW); flopenr #(32) InstrWReg(clk, reset, ~`STALLW, `FLUSHW ? nop : dut.hart.ifu.InstrM, InstrW); flopenrc #(1) controlregW(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.c.InstrValidM, InstrValidW); - flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.ieu.dp.MemAdrM, MemAdrW); + flopenrc #(`XLEN) MemAdrWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.MemAdrM, MemAdrW); flopenrc #(`XLEN) WriteDataWReg(clk, reset, `FLUSHW, ~`STALLW, dut.hart.WriteDataM, WriteDataW); flopenr #(1) TrapWReg(clk, reset, ~`STALLW, dut.hart.hzu.TrapM, TrapW);