diff --git a/pipelined/src/privileged/csrsr.sv b/pipelined/src/privileged/csrsr.sv
index 82e8b5d5..88669126 100644
--- a/pipelined/src/privileged/csrsr.sv
+++ b/pipelined/src/privileged/csrsr.sv
@@ -66,6 +66,7 @@ module csrsr (
                           STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
                           STATUS_SPP, /*STATUS_MPIE*/ 1'b0, STATUS_UBE, STATUS_SPIE,
                           /*1'b0, STATUS_MIE, 1'b0*/ 3'b0, STATUS_SIE, 1'b0};
+	assign MSTATUSH_REGW = '0; // *** does not exist when XLEN=64, but don't want it to have an undefined value.  Spec is not clear what it should be.
   end else begin: csrsr32 // RV32
     assign MSTATUS_REGW = {STATUS_SD, 8'b0,
                           STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
diff --git a/pipelined/testbench/common/rvvitrace.sv b/pipelined/testbench/common/rvvitrace.sv
index cc564d38..ece26558 100644
--- a/pipelined/testbench/common/rvvitrace.sv
+++ b/pipelined/testbench/common/rvvitrace.sv
@@ -39,6 +39,7 @@ module rvviTrace #(
   logic [4:0] 					 frf_a4;
   logic 						 frf_we4;
   logic [`XLEN-1:0] 			 CSRArray [logic[11:0]];
+  logic [`XLEN-1:0] 			 CSRArrayOld [logic[11:0]];
   logic 						 CSRWriteM, CSRWriteW;
   logic [11:0] 					 CSRAdrM, CSRAdrW;
 
@@ -202,10 +203,24 @@ module rvviTrace #(
 	assign f_wb[0][0][index] = frf_wb[index];
   end
 
+  // record previous csr value.
+  integer index4;
+  always_ff @(posedge clk) begin
+	for (index4 = 0; index4 < `NUM_CSRS; index4 += 1) begin
+	  if(CSRArray.exists(index4)) begin
+		CSRArrayOld[index4] = CSRArray[index4];
+	  end
+	end
+  end
+
+  // check for csr value change.
+  integer index5;
   always_comb begin
-	csr_wb[0][0] <= '0;
-	if(CSRWriteW)
-	  csr_wb[0][0][CSRAdrW] <= 1'b1;
+	for(index5 = 0; index5 < `NUM_CSRS; index5 += 1) begin
+	  if(CSRArray.exists(index5)) begin
+		csr_wb[0][0][index5] = CSRArrayOld[index5] != CSRArray[index5] ? 1'b1 : 1'b0;
+	  end else  csr_wb[0][0][index5] = '0;
+	end
   end
 
   integer index3;