From ac95087042862da64fcb854f7d64bd07cbf641c2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 17 Apr 2023 20:05:59 -0500 Subject: [PATCH] Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. --- fpga/constraints/constraints-ArtyA7.xdc | 4 +- fpga/generator/xlnx_ddr3-artya7-mig.prj | 98 ++++++++++++------------- fpga/src/fpgaTopArtyA7.v | 1 - 3 files changed, 51 insertions(+), 52 deletions(-) diff --git a/fpga/constraints/constraints-ArtyA7.xdc b/fpga/constraints/constraints-ArtyA7.xdc index c11d69a1..30cba8cc 100644 --- a/fpga/constraints/constraints-ArtyA7.xdc +++ b/fpga/constraints/constraints-ArtyA7.xdc @@ -42,8 +42,8 @@ set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [g # *** IOSTANDARD is probably wrong set_property PACKAGE_PIN A9 [get_ports UARTSin] set_property PACKAGE_PIN D10 [get_ports UARTSout] -set_max_delay -from [get_ports UARTSin] 10.000 -set_max_delay -to [get_ports UARTSout] 10.000 +set_max_delay -from [get_ports UARTSin] 14.000 +set_max_delay -to [get_ports UARTSout] 14.000 set_property IOSTANDARD LVCMOS33 [get_ports UARTSin] set_property IOSTANDARD LVCMOS33 [get_ports UARTSout] set_property DRIVE 4 [get_ports UARTSout] diff --git a/fpga/generator/xlnx_ddr3-artya7-mig.prj b/fpga/generator/xlnx_ddr3-artya7-mig.prj index d53a2069..32905a5b 100644 --- a/fpga/generator/xlnx_ddr3-artya7-mig.prj +++ b/fpga/generator/xlnx_ddr3-artya7-mig.prj @@ -65,57 +65,57 @@ 14 10 3 - 1.5V + 1.35V BANK_ROW_COLUMN - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/fpga/src/fpgaTopArtyA7.v b/fpga/src/fpgaTopArtyA7.v index 352d07cc..c682bca8 100644 --- a/fpga/src/fpgaTopArtyA7.v +++ b/fpga/src/fpgaTopArtyA7.v @@ -416,7 +416,6 @@ module fpgaTop .ddr3_dm(ddr3_dm), .ddr3_odt(ddr3_odt), - // clocks. I still don't understand why this needs two? .sys_clk_i(clk167), .clk_ref_i(clk200),