From d8ee0ea59de601da39a019074d711136fb502ac5 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 19 Dec 2022 22:46:11 -0600 Subject: [PATCH 01/31] Begin cleanup of ifu. partial move of pc muxes inside bp. --- pipelined/src/ifu/bpred.sv | 14 +++++++++++--- pipelined/src/ifu/ifu.sv | 5 +---- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 908d9a6b..4e231282 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -41,8 +41,8 @@ module bpred // the prediction input logic [31:0] InstrD, input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list - output logic [`XLEN-1:0] BPPredPCF, - output logic SelBPPredF, + input logic [`XLEN-1:0] PCPlus2or4F, + output logic [`XLEN-1:0] PCNext0F, // Update Predictor input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction // 1 hot encoding @@ -57,7 +57,7 @@ module bpred output logic [4:0] InstrClassM, // Report branch prediction status output logic BPPredWrongE, - output logic BPPredWrongM, + output logic BPPredWrongM, output logic BPPredDirWrongM, output logic BTBPredPCWrongM, output logic RASPredPCWrongM, @@ -76,6 +76,10 @@ module bpred logic [4:0] InstrClassD, InstrClassE; logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; + logic SelBPPredF; + logic [`XLEN-1:0] BPPredPCF; + + // Part 1 branch direction prediction @@ -250,4 +254,8 @@ module bpred .OldState(BPPredE), .NewState(UpdateBPPredE)); + + mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F)); + + endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index ce63a6c9..d6640a6c 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -306,16 +306,13 @@ module ifu ( //////////////////////////////////////////////////////////////////////////////////////////////// if (`BPRED_ENABLED) begin : bpred logic BPPredWrongM; - logic SelBPPredF; - logic [`XLEN-1:0] BPPredPCF; bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .InstrD, .PCNextF, .BPPredPCF, .SelBPPredF, .PCE, .PCSrcE, .IEUAdrE, + .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); - mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F)); // Mux only required on instruction class miss prediction. mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(PCBPWrongInvalidate)); From 565585b35abdd30ba7a9f4be8e91cb4e35dcc5f1 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 19 Dec 2022 22:51:55 -0600 Subject: [PATCH 02/31] Moved more muxes inside bp. --- pipelined/src/ifu/bpred.sv | 13 ++++++++++++- pipelined/src/ifu/ifu.sv | 10 ++-------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 4e231282..5e55c994 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -43,8 +43,13 @@ module bpred input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list input logic [`XLEN-1:0] PCPlus2or4F, output logic [`XLEN-1:0] PCNext0F, + output logic [`XLEN-1:0] PCCorrectE, + output logic [`XLEN-1:0] PCBPWrongInvalidate, // The address of the currently executing instruction + // Update Predictor input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction + input logic [`XLEN-1:0] PCF, // The address of the currently executing instruction + // 1 hot encoding // return, jump register, jump, branch // *** after reviewing the compressed instruction set I am leaning towards having the btb predict the instruction class. @@ -57,7 +62,6 @@ module bpred output logic [4:0] InstrClassM, // Report branch prediction status output logic BPPredWrongE, - output logic BPPredWrongM, output logic BPPredDirWrongM, output logic BTBPredPCWrongM, output logic RASPredPCWrongM, @@ -78,6 +82,8 @@ module bpred logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; + logic BPPredWrongM; + @@ -256,6 +262,11 @@ module bpred mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F)); + mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE)); + // Mux only required on instruction class miss prediction. + mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), + .s(BPPredWrongM), .y(PCBPWrongInvalidate)); + endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index d6640a6c..7b06c48b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -305,19 +305,13 @@ module ifu ( // Branch and Jump Predictor //////////////////////////////////////////////////////////////////////////////////////////////// if (`BPRED_ENABLED) begin : bpred - logic BPPredWrongM; bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredWrongM, + .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .PCBPWrongInvalidate, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); - // Mux only required on instruction class miss prediction. - mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), - .s(BPPredWrongM), .y(PCBPWrongInvalidate)); - mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE)); - end else begin : bpred assign BPPredWrongE = PCSrcE; assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0; From 2df18cc7589d0cbf2d96f4020a262241fbb47d7a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 19 Dec 2022 23:16:58 -0600 Subject: [PATCH 03/31] More bp/ifu pcmux cleanup. --- pipelined/src/ifu/bpred.sv | 17 ++++++++++++----- pipelined/src/ifu/ifu.sv | 13 +++++++------ 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 5e55c994..0cc33f7b 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -42,9 +42,9 @@ module bpred input logic [31:0] InstrD, input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list input logic [`XLEN-1:0] PCPlus2or4F, - output logic [`XLEN-1:0] PCNext0F, + output logic [`XLEN-1:0] PCNext1F, output logic [`XLEN-1:0] PCCorrectE, - output logic [`XLEN-1:0] PCBPWrongInvalidate, // The address of the currently executing instruction + output logic [`XLEN-1:0] NextValidPCE, // The address of the currently executing instruction // Update Predictor input logic [`XLEN-1:0] PCE, // The address of the currently executing instruction @@ -83,6 +83,8 @@ module bpred logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF; logic BPPredWrongM; + logic [`XLEN-1:0] PCNext0F; + @@ -262,11 +264,16 @@ module bpred mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F)); + + + mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE)); - // Mux only required on instruction class miss prediction. - mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), - .s(BPPredWrongM), .y(PCBPWrongInvalidate)); + // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. + // could also just use PCM+4 + mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(NextValidPCE)); + //assign NextValidPCE = PCE; + mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F)); endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 7b06c48b..b8294419 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -102,7 +102,7 @@ module ifu ( localparam [31:0] nop = 32'h00000013; // instruction for NOP logic [31:0] NextInstrD, NextInstrE; - logic [`XLEN-1:0] PCBPWrongInvalidate; + logic [`XLEN-1:0] NextValidPCE; (* mark_debug = "true" *) logic [`PA_BITS-1:0] PCPF; // used to either truncate or expand PCPF and PCNextF into `PA_BITS width. logic [`XLEN+1:0] PCFExt; @@ -288,10 +288,10 @@ module ifu ( assign PrivilegedChangePCM = RetM | TrapM; - mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F)); + // if(`ICACHE | `ZICSR_SUPPORTED) - mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(CSRWriteFenceM), - .y(PCNext2F)); + mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F)); +// mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F)); // else assign PCNext2F = PCNext1F; if(`ZICSR_SUPPORTED) mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), @@ -308,16 +308,17 @@ module ifu ( bpred bpred(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .InstrD, .PCNextF, .PCPlus2or4F, .PCNext0F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .PCBPWrongInvalidate, + .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .NextValidPCE, .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); end else begin : bpred + mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F)); assign BPPredWrongE = PCSrcE; assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0; assign PCNext0F = PCPlus2or4F; assign PCCorrectE = IEUAdrE; - assign PCBPWrongInvalidate = PCE; + assign NextValidPCE = PCE; end // pcadder From dedc08bd42ace2af716702020b7fc6ea2fcaecca Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 19 Dec 2022 23:33:12 -0600 Subject: [PATCH 04/31] several options for pcnextf on fence.i --- pipelined/src/ifu/bpred.sv | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 0cc33f7b..87d7557b 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -269,8 +269,14 @@ module bpred mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE)); // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. - // could also just use PCM+4 + // could also just use PCM+4, which should be pclinke mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(NextValidPCE)); + //logic [`XLEN-1:0] PCLinkM; + //flopenr #(`XLEN) PCPEReg(clk, reset, ~StallM, PCLinkE, PCLinkM); + //assign NextValidPCE = PCLinkM; + // of the three, the mux is the cheapest, but the least clear. + // this could move entirely into ifu with no relation to bp with the third. + //assign NextValidPCE = PCE; From caf457106a330eb845a34937db684e1ee78e31c2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 01:33:35 -0800 Subject: [PATCH 05/31] Replaced || and && with single ops --- pipelined/src/privileged/privdec.sv | 2 +- pipelined/src/privileged/trap.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/privileged/privdec.sv b/pipelined/src/privileged/privdec.sv index a63bf982..c31dca1d 100644 --- a/pipelined/src/privileged/privdec.sv +++ b/pipelined/src/privileged/privdec.sv @@ -52,7 +52,7 @@ module privdec ( // Decode privileged instructions /////////////////////////////////////////// assign sretM = PrivilegedM & (InstrM[31:20] == 12'b000100000010) & `S_SUPPORTED & - (PrivilegeModeW == `M_MODE || PrivilegeModeW == `S_MODE & ~STATUS_TSR); + (PrivilegeModeW == `M_MODE | PrivilegeModeW == `S_MODE & ~STATUS_TSR); assign mretM = PrivilegedM & (InstrM[31:20] == 12'b001100000010) & (PrivilegeModeW == `M_MODE); assign ecallM = PrivilegedM & (InstrM[31:20] == 12'b000000000000); assign ebreakM = PrivilegedM & (InstrM[31:20] == 12'b000000000001); diff --git a/pipelined/src/privileged/trap.sv b/pipelined/src/privileged/trap.sv index c5c749b8..ec3cc863 100644 --- a/pipelined/src/privileged/trap.sv +++ b/pipelined/src/privileged/trap.sv @@ -68,7 +68,7 @@ module trap ( assign Committed = CommittedM | CommittedF; assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); assign ValidIntsM = {12{~Committed}} & EnabledIntsM; - assign InterruptM = (|ValidIntsM) && InstrValidM; // suppress interrupt if the memory system has partially processed a request. + assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request. assign DelegateM = `S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM[3:0]] : MEDELEG_REGW[CauseM]) & (PrivilegeModeW == `U_MODE | PrivilegeModeW == `S_MODE); From 54e856c4f59985b8a11aa8ac7f169f729f21e1da Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 02:09:36 -0800 Subject: [PATCH 06/31] Renamed SRAM2P1R1W to lower case --- pipelined/src/generic/mem/SRAM2P1R1W.sv | 109 -------------------- pipelined/src/ifu/BTBPredictor.sv | 4 +- pipelined/src/ifu/globalHistoryPredictor.sv | 2 +- pipelined/src/ifu/gsharePredictor.sv | 2 +- pipelined/src/ifu/localHistoryPredictor.sv | 4 +- pipelined/src/ifu/twoBitPredictor.sv | 2 +- 6 files changed, 7 insertions(+), 116 deletions(-) delete mode 100644 pipelined/src/generic/mem/SRAM2P1R1W.sv diff --git a/pipelined/src/generic/mem/SRAM2P1R1W.sv b/pipelined/src/generic/mem/SRAM2P1R1W.sv deleted file mode 100644 index 513b7a36..00000000 --- a/pipelined/src/generic/mem/SRAM2P1R1W.sv +++ /dev/null @@ -1,109 +0,0 @@ -/////////////////////////////////////////// -// SRAM2P1R1W -// -// Written: Ross Thomposn -// Email: ross1728@gmail.com -// Created: February 14, 2021 -// Modified: -// -// Purpose: Behavioral model of two port SRAM. While this is synthesizable it will produce a flip flop based memory whi -// behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm. -// -// -// to preload this memory we can use the following command -// in modelsim's do file. -// mem load -infile -format -// example -// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module SRAM2P1R1W - #(parameter int DEPTH = 10, - parameter int WIDTH = 2 - ) - - (input logic clk, - // *** have to remove reset eventually - input logic reset, - - // port 1 is read only - input logic [DEPTH-1:0] RA1, - output logic [WIDTH-1:0] RD1, - input logic REN1, - - // port 2 is write only - input logic [DEPTH-1:0] WA1, - input logic [WIDTH-1:0] WD1, - input logic WEN1, - input logic [WIDTH-1:0] BitWEN1 - ); - - - logic [DEPTH-1:0] RA1Q, WA1Q; - logic WEN1Q; - logic [WIDTH-1:0] WD1Q; - - logic [WIDTH-1:0] mem[2**DEPTH-1:0]; - logic [WIDTH-1:0] bwe; - - - // SRAMs address busses are always registered first. - - flopenr #(DEPTH) RA1Reg(.clk(clk), - .reset(reset), - .en(REN1), - .d(RA1), - .q(RA1Q)); - - - flopenr #(DEPTH) WA1Reg(.clk(clk), - .reset(reset), - .en(REN1), - .d(WA1), - .q(WA1Q)); - - flopenr #(1) WEN1Reg(.clk(clk), - .reset(reset), - .en(1'b1), - .d(WEN1), - .q(WEN1Q)); - - flopenr #(WIDTH) WD1Reg(.clk(clk), - .reset(reset), - .en(REN1), - .d(WD1), - .q(WD1Q)); - // read port - assign RD1 = mem[RA1Q]; - - // write port - assign bwe = {WIDTH{WEN1Q}} & BitWEN1; - always_ff @(posedge clk) - mem[WA1Q] <= WD1Q & bwe | mem[WA1Q] & ~bwe; - -endmodule - - diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv index bcd04b8b..a07efcdf 100644 --- a/pipelined/src/ifu/BTBPredictor.sv +++ b/pipelined/src/ifu/BTBPredictor.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// SRAM2P1R1W +// sram2p1r1w // // Written: Ross Thomposn // Email: ross1728@gmail.com @@ -103,7 +103,7 @@ module BTBPredictor // *** need to add forwarding. // *** optimize for byte write enables - SRAM2P1R1W #(Depth, `XLEN+5) memory(.clk(clk), + sram2p1r1w #(Depth, `XLEN+5) memory(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1({{InstrClass, TargetPC}}), diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv index dd940140..f40eb172 100644 --- a/pipelined/src/ifu/globalHistoryPredictor.sv +++ b/pipelined/src/ifu/globalHistoryPredictor.sv @@ -113,7 +113,7 @@ module globalHistoryPredictor assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - SRAM2P1R1W #(k, 2) PHT(.clk(clk), + sram2p1r1w #(k, 2) PHT(.clk(clk), .reset(reset), //.RA1(GHR[k-1:0]), .RA1(GHRLookup), diff --git a/pipelined/src/ifu/gsharePredictor.sv b/pipelined/src/ifu/gsharePredictor.sv index f175361d..7a2b5627 100644 --- a/pipelined/src/ifu/gsharePredictor.sv +++ b/pipelined/src/ifu/gsharePredictor.sv @@ -110,7 +110,7 @@ module gsharePredictor assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - SRAM2P1R1W #(`BPRED_SIZE, 2) PHT(.clk(clk), + sram2p1r1w #(`BPRED_SIZE, 2) PHT(.clk(clk), .reset(reset), //.RA1(GHR[`BPRED_SIZE-1:0]), .RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 75798586..5826496a 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -60,7 +60,7 @@ module localHistoryPredictor assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]}; // INCASE we do ahead pipelining - // SRAM2P1R1W #(m,k) LHR(.clk(clk)), + // sram2p1r1w #(m,k) LHR(.clk(clk)), // .reset(reset), // .RA1(LookUpPCIndex), // need hashing function to get correct PC address // .RD1(LHRF), @@ -84,7 +84,7 @@ module localHistoryPredictor // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT // LHR referes to the address that the past k branches points to in the prediction stage // LHRE refers to the address that the past k branches points to in the exectution stage - SRAM2P1R1W #(k, 2) PHT(.clk(clk), + sram2p1r1w #(k, 2) PHT(.clk(clk), .reset(reset), .RA1(ForwardLHRNext), .RD1(PredictionMemory), diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv index 295f5e5e..59827526 100644 --- a/pipelined/src/ifu/twoBitPredictor.sv +++ b/pipelined/src/ifu/twoBitPredictor.sv @@ -60,7 +60,7 @@ module twoBitPredictor assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]}; - SRAM2P1R1W #(Depth, 2) PHT(.clk(clk), + sram2p1r1w #(Depth, 2) PHT(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1(PredictionMemory), From 2c46f22be554ea483b569e26b1f20fbc9ded5133 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 02:09:55 -0800 Subject: [PATCH 07/31] Renamed SRAM2P1R1W to lower case --- pipelined/src/generic/mem/sram2p1r1w.sv | 88 +++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 pipelined/src/generic/mem/sram2p1r1w.sv diff --git a/pipelined/src/generic/mem/sram2p1r1w.sv b/pipelined/src/generic/mem/sram2p1r1w.sv new file mode 100644 index 00000000..d18a9619 --- /dev/null +++ b/pipelined/src/generic/mem/sram2p1r1w.sv @@ -0,0 +1,88 @@ +/////////////////////////////////////////// +// sram2p1r1w +// +// Written: Ross Thomposn +// Email: ross1728@gmail.com +// Created: February 14, 2021 +// Modified: +// +// Purpose: Behavioral model of two port SRAM. While this is synthesizable it will produce a flip flop based memory which +// behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm. +// +// +// to preload this memory we can use the following command +// in modelsim's do file. +// mem load -infile -format +// example +// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// MIT LICENSE +// Permission is hereby granted, free of charge, to any person obtaining a copy of this +// software and associated documentation files (the "Software"), to deal in the Software +// without restriction, including without limitation the rights to use, copy, modify, merge, +// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons +// to whom the Software is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or +// substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, +// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR +// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE +// OR OTHER DEALINGS IN THE SOFTWARE. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module sram2p1r1w + #(parameter int DEPTH = 10, + parameter int WIDTH = 2 + ) + + (input logic clk, + input logic reset, + + // port 1 is read only + input logic [DEPTH-1:0] RA1, + output logic [WIDTH-1:0] RD1, + input logic REN1, + + // port 2 is write only + input logic [DEPTH-1:0] WA1, + input logic [WIDTH-1:0] WD1, + input logic WEN1, + input logic [WIDTH-1:0] BitWEN1 +); + + + logic [DEPTH-1:0] RA1Q, WA1Q; + logic WEN1Q; + logic [WIDTH-1:0] WD1Q; + + logic [WIDTH-1:0] mem[2**DEPTH-1:0]; + logic [WIDTH-1:0] bwe; + + + // SRAMs address busses are always registered first + flopenr #(DEPTH) RA1Reg(clk, reset, REN1, RA1, RA1Q); + flopenr #(DEPTH) WA1Reg(clk, reset, REN1, WA1, WA1Q); + flopr #(1) WEN1Reg(clk, reset, WEN1, WEN1Q); + flopenr #(WIDTH) WD1Reg(clk, reset, REN1, WD1, WD1Q); + + // read port + assign RD1 = mem[RA1Q]; + + // write port + assign bwe = {WIDTH{WEN1Q}} & BitWEN1; + always_ff @(posedge clk) + mem[WA1Q] <= WD1Q & bwe | mem[WA1Q] & ~bwe; + +endmodule + + From 08234cb1c76359515f0858b87096c1d7a0103cf5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 02:40:45 -0800 Subject: [PATCH 08/31] Remoed unused bram modules --- pipelined/src/generic/mem/bram1p1rw_64x128.sv | 67 ------------------- .../src/generic/mem/bram1p1rw_64x128wrap.sv | 35 ---------- .../src/generic/mem/bram1p1rw_64x44wrap.sv | 36 ---------- 3 files changed, 138 deletions(-) delete mode 100644 pipelined/src/generic/mem/bram1p1rw_64x128.sv delete mode 100644 pipelined/src/generic/mem/bram1p1rw_64x128wrap.sv delete mode 100644 pipelined/src/generic/mem/bram1p1rw_64x44wrap.sv diff --git a/pipelined/src/generic/mem/bram1p1rw_64x128.sv b/pipelined/src/generic/mem/bram1p1rw_64x128.sv deleted file mode 100644 index eaa5c7f7..00000000 --- a/pipelined/src/generic/mem/bram1p1rw_64x128.sv +++ /dev/null @@ -1,67 +0,0 @@ -/////////////////////////////////////////// -// block ram model should be equivalent to srsam. -// -// Written: Ross Thompson -// March 29, 2022 -// Modified: Based on UG901 vivado documentation. -// -// Purpose: On-chip RAM array -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// MIT LICENSE -// Permission is hereby granted, free of charge, to any person obtaining a copy of this -// software and associated documentation files (the "Software"), to deal in the Software -// without restriction, including without limitation the rights to use, copy, modify, merge, -// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons -// to whom the Software is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or -// substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, -// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR -// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE -// OR OTHER DEALINGS IN THE SOFTWARE. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// This model actually works correctly with vivado. - -`include "wally-config.vh" - -module bram1p1rw_64x128 - #( - //-------------------------------------------------------------------------- - parameter NUM_COL = 16, - parameter COL_WIDTH = 8, - parameter ADDR_WIDTH = 6, - // Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth - parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits - //---------------------------------------------------------------------- - ) ( - input logic clk, - input logic we, - input logic [NUM_COL-1:0] bwe, - input logic [ADDR_WIDTH-1:0] addr, - output logic [DATA_WIDTH-1:0] dout, - input logic [DATA_WIDTH-1:0] din - ); - // Core Memory - logic [DATA_WIDTH-1:0] RAM [(2**ADDR_WIDTH)-1:0]; - integer i; - - always @ (posedge clk) begin - dout <= RAM[addr]; - if(we) begin - for(i=0;i Date: Tue, 20 Dec 2022 02:57:51 -0800 Subject: [PATCH 09/31] sram1p1rw cleanup --- addins/riscv-arch-test | 2 +- pipelined/src/generic/mem/sram1p1rw.sv | 36 +++++++++++--------------- 2 files changed, 16 insertions(+), 22 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index e302d3ba..ee028eb3 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit e302d3bab41a46ec388691b1d961aa09fe2a4bc4 +Subproject commit ee028eb325525148a34420a4ca7959b24220a91e diff --git a/pipelined/src/generic/mem/sram1p1rw.sv b/pipelined/src/generic/mem/sram1p1rw.sv index eff148cb..45668125 100644 --- a/pipelined/src/generic/mem/sram1p1rw.sv +++ b/pipelined/src/generic/mem/sram1p1rw.sv @@ -44,8 +44,7 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( input logic [(WIDTH-1)/8:0] bwe, output logic [WIDTH-1:0] dout); - logic [WIDTH-1:0] RAM[DEPTH-1:0]; - + logic [WIDTH-1:0] RAM[DEPTH-1:0]; // *************************************************************************** // TRUE SRAM macro @@ -65,29 +64,24 @@ module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( // *************************************************************************** // READ first SRAM model // *************************************************************************** - end else begin + end else begin: ram integer i; - if (WIDTH%8 != 0) // handle msbs if not a multiple of 8 + + // Read + always @(posedge clk) + if(ce) dout <= #1 RAM[addr]; + + // Write divided into part for bytes and part for extra msbs + if(WIDTH >= 8) + always @(posedge clk) + if (ce & we) + for(i = 0; i < WIDTH/8; i++) + if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8]; + + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 always @(posedge clk) if (ce & we & bwe[WIDTH/8]) RAM[addr][WIDTH-1:WIDTH-WIDTH%8] <= #1 din[WIDTH-1:WIDTH-WIDTH%8]; - - always @(posedge clk) begin - if(ce) begin - dout <= #1 RAM[addr]; - end - end - if(WIDTH >= 8) begin - always @(posedge clk) begin - if(ce) begin - if(we) begin - for(i = 0; i < WIDTH/8; i++) - if(bwe[i]) - RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8]; - end - end - end - end end endmodule From e74d47bcb48ece617be64548ee277e578fa72997 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 08:36:45 -0800 Subject: [PATCH 10/31] Renamed renamed sram to ram --- pipelined/src/cache/cacheway.sv | 4 ++-- pipelined/src/generic/mem/{sram1p1rw.sv => ram1p1rwbe.sv} | 2 +- pipelined/src/generic/mem/{sram2p1r1w.sv => ram2p1r1wb.sv} | 4 ++-- pipelined/src/ifu/BTBPredictor.sv | 4 ++-- pipelined/src/ifu/globalHistoryPredictor.sv | 2 +- pipelined/src/ifu/gsharePredictor.sv | 2 +- pipelined/src/ifu/localHistoryPredictor.sv | 4 ++-- pipelined/src/ifu/twoBitPredictor.sv | 2 +- pipelined/src/lsu/dtim.sv | 2 +- pipelined/src/uncore/ram_ahb.sv | 2 +- 10 files changed, 14 insertions(+), 14 deletions(-) rename pipelined/src/generic/mem/{sram1p1rw.sv => ram1p1rwbe.sv} (98%) rename pipelined/src/generic/mem/{sram2p1r1w.sv => ram2p1r1wb.sv} (98%) diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 5f986954..0639fcf9 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -116,7 +116,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, // Tag Array ///////////////////////////////////////////////////////////////////////////////////////////// - sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), + ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk, .ce(CacheEn), .addr(CAdr), .dout(ReadTag), .bwe('1), .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); @@ -139,7 +139,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, localparam integer LOGNUMSRAM = $clog2(NUMSRAM); for(words = 0; words < NUMSRAM; words++) begin: word - sram1p1rw #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr), + ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr), .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]), .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]), .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words])); diff --git a/pipelined/src/generic/mem/sram1p1rw.sv b/pipelined/src/generic/mem/ram1p1rwbe.sv similarity index 98% rename from pipelined/src/generic/mem/sram1p1rw.sv rename to pipelined/src/generic/mem/ram1p1rwbe.sv index 45668125..0a7f7424 100644 --- a/pipelined/src/generic/mem/sram1p1rw.sv +++ b/pipelined/src/generic/mem/ram1p1rwbe.sv @@ -35,7 +35,7 @@ `include "wally-config.vh" -module sram1p1rw #(parameter DEPTH=128, WIDTH=256) ( +module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) ( input logic clk, input logic ce, input logic [$clog2(DEPTH)-1:0] addr, diff --git a/pipelined/src/generic/mem/sram2p1r1w.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv similarity index 98% rename from pipelined/src/generic/mem/sram2p1r1w.sv rename to pipelined/src/generic/mem/ram2p1r1wb.sv index d18a9619..ff3257eb 100644 --- a/pipelined/src/generic/mem/sram2p1r1w.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// sram2p1r1w +// ram2p1r1wb // // Written: Ross Thomposn // Email: ross1728@gmail.com @@ -40,7 +40,7 @@ `include "wally-config.vh" -module sram2p1r1w +module ram2p1r1wb #(parameter int DEPTH = 10, parameter int WIDTH = 2 ) diff --git a/pipelined/src/ifu/BTBPredictor.sv b/pipelined/src/ifu/BTBPredictor.sv index a07efcdf..f03bbdd5 100644 --- a/pipelined/src/ifu/BTBPredictor.sv +++ b/pipelined/src/ifu/BTBPredictor.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// sram2p1r1w +// ram2p1r1wb // // Written: Ross Thomposn // Email: ross1728@gmail.com @@ -103,7 +103,7 @@ module BTBPredictor // *** need to add forwarding. // *** optimize for byte write enables - sram2p1r1w #(Depth, `XLEN+5) memory(.clk(clk), + ram2p1r1wb #(Depth, `XLEN+5) memory(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1({{InstrClass, TargetPC}}), diff --git a/pipelined/src/ifu/globalHistoryPredictor.sv b/pipelined/src/ifu/globalHistoryPredictor.sv index f40eb172..6d06dc8c 100644 --- a/pipelined/src/ifu/globalHistoryPredictor.sv +++ b/pipelined/src/ifu/globalHistoryPredictor.sv @@ -113,7 +113,7 @@ module globalHistoryPredictor assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - sram2p1r1w #(k, 2) PHT(.clk(clk), + ram2p1r1wb #(k, 2) PHT(.clk(clk), .reset(reset), //.RA1(GHR[k-1:0]), .RA1(GHRLookup), diff --git a/pipelined/src/ifu/gsharePredictor.sv b/pipelined/src/ifu/gsharePredictor.sv index 7a2b5627..ff111a3e 100644 --- a/pipelined/src/ifu/gsharePredictor.sv +++ b/pipelined/src/ifu/gsharePredictor.sv @@ -110,7 +110,7 @@ module gsharePredictor assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0]; // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT - sram2p1r1w #(`BPRED_SIZE, 2) PHT(.clk(clk), + ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk), .reset(reset), //.RA1(GHR[`BPRED_SIZE-1:0]), .RA1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]), diff --git a/pipelined/src/ifu/localHistoryPredictor.sv b/pipelined/src/ifu/localHistoryPredictor.sv index 5826496a..97b2b6f5 100644 --- a/pipelined/src/ifu/localHistoryPredictor.sv +++ b/pipelined/src/ifu/localHistoryPredictor.sv @@ -60,7 +60,7 @@ module localHistoryPredictor assign LookUpPCIndex = {LookUpPC[m+1] ^ LookUpPC[1], LookUpPC[m:2]}; // INCASE we do ahead pipelining - // sram2p1r1w #(m,k) LHR(.clk(clk)), + // ram2p1r1wb #(m,k) LHR(.clk(clk)), // .reset(reset), // .RA1(LookUpPCIndex), // need hashing function to get correct PC address // .RD1(LHRF), @@ -84,7 +84,7 @@ module localHistoryPredictor // Make Prediction by reading the correct address in the PHT and also update the new address in the PHT // LHR referes to the address that the past k branches points to in the prediction stage // LHRE refers to the address that the past k branches points to in the exectution stage - sram2p1r1w #(k, 2) PHT(.clk(clk), + ram2p1r1wb #(k, 2) PHT(.clk(clk), .reset(reset), .RA1(ForwardLHRNext), .RD1(PredictionMemory), diff --git a/pipelined/src/ifu/twoBitPredictor.sv b/pipelined/src/ifu/twoBitPredictor.sv index 59827526..5ffb29d3 100644 --- a/pipelined/src/ifu/twoBitPredictor.sv +++ b/pipelined/src/ifu/twoBitPredictor.sv @@ -60,7 +60,7 @@ module twoBitPredictor assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]}; - sram2p1r1w #(Depth, 2) PHT(.clk(clk), + ram2p1r1wb #(Depth, 2) PHT(.clk(clk), .reset(reset), .RA1(LookUpPCIndex), .RD1(PredictionMemory), diff --git a/pipelined/src/lsu/dtim.sv b/pipelined/src/lsu/dtim.sv index 8f991883..9d83332f 100644 --- a/pipelined/src/lsu/dtim.sv +++ b/pipelined/src/lsu/dtim.sv @@ -46,7 +46,7 @@ module dtim( assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. - sram1p1rw #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) + ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(Adr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); endmodule diff --git a/pipelined/src/uncore/ram_ahb.sv b/pipelined/src/uncore/ram_ahb.sv index df87bb47..230b54c9 100644 --- a/pipelined/src/uncore/ram_ahb.sv +++ b/pipelined/src/uncore/ram_ahb.sv @@ -73,7 +73,7 @@ module ram_ahb #(parameter BASE=0, RANGE = 65535) ( mux2 #(`PA_BITS) adrmux(HADDR, HADDRD, memwriteD | ~HREADY, RamAddr); // single-ported RAM - sram1p1rw #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1), + ram1p1rwbe #(.DEPTH(RANGE/8), .WIDTH(`XLEN)) memory(.clk(HCLK), .ce(1'b1), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .we(memwriteD), .din(HWDATA), .bwe(HWSTRB), .dout(HREADRam)); From 03c700d91c67952b6f0f3ba5a3114ccd15c601f6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 10:56:33 -0800 Subject: [PATCH 11/31] Restored rv32d arch test after new push --- tests/riscof/spike/spike_rv32imc_isa.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/riscof/spike/spike_rv32imc_isa.yaml b/tests/riscof/spike/spike_rv32imc_isa.yaml index f3caef84..04a5da18 100644 --- a/tests/riscof/spike/spike_rv32imc_isa.yaml +++ b/tests/riscof/spike/spike_rv32imc_isa.yaml @@ -1,11 +1,11 @@ hart_ids: [0] hart0: - ISA: RV32IMAFCZicsr_Zifencei + ISA: RV32IMAFDCZicsr_Zifencei physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x40001125 + reset-val: 0x4000112D rv32: accessible: true mxl: From 684d260005fa5e4729d28a66ebf98c5fe3737afe Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 12:58:54 -0600 Subject: [PATCH 12/31] Reorganized IFU PCNextF logic. --- pipelined/src/ifu/bpred.sv | 31 ++++++++--------- pipelined/src/ifu/ifu.sv | 56 +++++++++++++++---------------- pipelined/src/ifu/spillsupport.sv | 9 ++--- 3 files changed, 48 insertions(+), 48 deletions(-) diff --git a/pipelined/src/ifu/bpred.sv b/pipelined/src/ifu/bpred.sv index 87d7557b..eacdb814 100644 --- a/pipelined/src/ifu/bpred.sv +++ b/pipelined/src/ifu/bpred.sv @@ -43,7 +43,6 @@ module bpred input logic [`XLEN-1:0] PCNextF, // *** forgot to include this one on the I/O list input logic [`XLEN-1:0] PCPlus2or4F, output logic [`XLEN-1:0] PCNext1F, - output logic [`XLEN-1:0] PCCorrectE, output logic [`XLEN-1:0] NextValidPCE, // The address of the currently executing instruction // Update Predictor @@ -84,13 +83,10 @@ module bpred logic [`XLEN-1:0] BPPredPCF; logic BPPredWrongM; logic [`XLEN-1:0] PCNext0F; - - - - + logic [`XLEN-1:0] PCCorrectE; // Part 1 branch direction prediction - + // look into the 2 port Sram model. something is wrong. if (`BPTYPE == "BPTWOBIT") begin:Predictor twoBitPredictor DirPredictor(.clk, .reset, .StallF, .LookUpPC(PCNextF), @@ -263,23 +259,28 @@ module bpred .NewState(UpdateBPPredE)); + // Selects the BP or PC+2/4. mux2 #(`XLEN) pcmux0(.d0(PCPlus2or4F), .d1(BPPredPCF), .s(SelBPPredF), .y(PCNext0F)); + // If the prediction is wrong select the correct address. + mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F)); - - + // Correct branch/jump target. mux2 #(`XLEN) pccorrectemux(.d0(PCLinkE), .d1(IEUAdrE), .s(PCSrcE), .y(PCCorrectE)); + // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. - // could also just use PCM+4, which should be pclinke - mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(NextValidPCE)); + // could also just use PCM+4, or PCLinkM + // ONLY valid for class prediction. add option for class prediction. +// if(`BPCLASS) begin + mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(.d0(PCE), .d1(PCF), .s(BPPredWrongM), .y(NextValidPCE)); +// end else begin +// assign NextValidPCE = PCE; +// end + //logic [`XLEN-1:0] PCLinkM; //flopenr #(`XLEN) PCPEReg(clk, reset, ~StallM, PCLinkE, PCLinkM); //assign NextValidPCE = PCLinkM; // of the three, the mux is the cheapest, but the least clear. // this could move entirely into ifu with no relation to bp with the third. - - //assign NextValidPCE = PCE; - - - mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F)); + endmodule diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index b8294419..f33737ec 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -85,9 +85,8 @@ module ifu ( output logic ICacheAccess, output logic ICacheMiss ); - (* mark_debug = "true" *) logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; + (* mark_debug = "true" *) logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; logic BranchMisalignedFaultE; - logic PrivilegedChangePCM; logic IllegalCompInstrD; logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; logic [`XLEN-3:0] PCPlusUpperF; @@ -286,41 +285,19 @@ module ifu ( // PCNextF logic //////////////////////////////////////////////////////////////////////////////////////////////// - assign PrivilegedChangePCM = RetM | TrapM; - - // if(`ICACHE | `ZICSR_SUPPORTED) mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F)); // mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F)); // else assign PCNext2F = PCNext1F; - if(`ZICSR_SUPPORTED) + if(`ZICSR_SUPPORTED) begin + logic PrivilegedChangePCM; + assign PrivilegedChangePCM = RetM | TrapM; mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), - .y(UnalignedPCNextF)); - else assign UnalignedPCNextF = PCNext2F; - + .y(UnalignedPCNextF)); + end else assign UnalignedPCNextF = PCNext2F; assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); - //////////////////////////////////////////////////////////////////////////////////////////////// - // Branch and Jump Predictor - //////////////////////////////////////////////////////////////////////////////////////////////// - if (`BPRED_ENABLED) begin : bpred - bpred bpred(.clk, .reset, - .StallF, .StallD, .StallE, .StallM, - .FlushD, .FlushE, .FlushM, - .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCSrcE, .IEUAdrE, .PCCorrectE, .PCF, .NextValidPCE, - .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, - .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); - - end else begin : bpred - mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F)); - assign BPPredWrongE = PCSrcE; - assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0; - assign PCNext0F = PCPlus2or4F; - assign PCCorrectE = IEUAdrE; - assign NextValidPCE = PCE; - end - // pcadder // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC @@ -334,6 +311,27 @@ module ifu ( else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4 + + //////////////////////////////////////////////////////////////////////////////////////////////// + // Branch and Jump Predictor + //////////////////////////////////////////////////////////////////////////////////////////////// + if (`BPRED_ENABLED) begin : bpred + bpred bpred(.clk, .reset, + .StallF, .StallD, .StallE, .StallM, + .FlushD, .FlushE, .FlushM, + .InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE, + .PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, + .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM); + + end else begin : bpred + mux2 #(`XLEN) pcmux1(.d0(PCPlus2or4F), .d1(IEUAdrE), .s(PCSrcE), .y(PCNext1F)); + assign BPPredWrongE = PCSrcE; + assign {BPPredDirWrongM, BTBPredPCWrongM, RASPredPCWrongM, BPPredClassNonCFIWrongM} = '0; + assign PCNext0F = PCPlus2or4F; + assign NextValidPCE = PCE; + end + + //////////////////////////////////////////////////////////////////////////////////////////////// // Decode stage pipeline register and compressed instruction decoding. //////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index b247c2d3..5a6efe0b 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -59,10 +59,11 @@ module spillsupport #(parameter CACHE_ENABLED) typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype; (* mark_debug = "true" *) statetype CurrState, NextState; - mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), - .s(PCF[1]), .y(PCPlus2F)); - mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), - .y(PCNextFSpill)); + // compute PCF+2 + mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); + // select between PCNextF and PCF+2 + mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), .y(PCNextFSpill)); + // select between PCF adn PCF+2 mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; From f0ef5caf32ed22096657c0ed987fd01bed65ba9a Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 11:22:26 -0800 Subject: [PATCH 13/31] Memory cleanup --- pipelined/src/generic/mem/ram2p1r1wb.sv | 6 ++++++ pipelined/src/generic/mem/rom1p1r.sv | 1 + 2 files changed, 7 insertions(+) diff --git a/pipelined/src/generic/mem/ram2p1r1wb.sv b/pipelined/src/generic/mem/ram2p1r1wb.sv index ff3257eb..c11246d3 100644 --- a/pipelined/src/generic/mem/ram2p1r1wb.sv +++ b/pipelined/src/generic/mem/ram2p1r1wb.sv @@ -70,6 +70,12 @@ module ram2p1r1wb // SRAMs address busses are always registered first + // *** likely issued DH and RT 12/20/22 + // wrong enable for write port registers + // prefer to code read like ram1p1rw + // prefer not to have two-cycle write latency + // will require branch predictor changes + flopenr #(DEPTH) RA1Reg(clk, reset, REN1, RA1, RA1Q); flopenr #(DEPTH) WA1Reg(clk, reset, REN1, WA1, WA1Q); flopr #(1) WEN1Reg(clk, reset, WEN1, WEN1Q); diff --git a/pipelined/src/generic/mem/rom1p1r.sv b/pipelined/src/generic/mem/rom1p1r.sv index daed8da5..bbdc246b 100644 --- a/pipelined/src/generic/mem/rom1p1r.sv +++ b/pipelined/src/generic/mem/rom1p1r.sv @@ -52,6 +52,7 @@ module rom1p1r if(ce) dout <= ROM[addr]; end + // for FPGA, initialize with zero-stage bootloader if(PRELOAD_ENABLED) begin initial begin ROM[0] = 64'h9581819300002197; From 8029b12f2a336862dc25ab6b39a27ac8e5778cb0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 16:33:49 -0600 Subject: [PATCH 14/31] Renumbered bits for PCPlusUpper. --- pipelined/src/ifu/ifu.sv | 8 +++++++- pipelined/src/ifu/spillsupport.sv | 2 +- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index f33737ec..427e9038 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -89,7 +89,7 @@ module ifu ( logic BranchMisalignedFaultE; logic IllegalCompInstrD; logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; - logic [`XLEN-3:0] PCPlusUpperF; + logic [`XLEN-1:2] PCPlusUpperF; logic CompressedF; logic [31:0] InstrRawD, InstrRawF, IROMInstrF, ICacheInstrF; logic [31:0] FinalInstrRawF; @@ -304,6 +304,12 @@ module ifu ( // choose PC+2 or PC+4 based on CompressedF, which arrives later. // Speeds up critical path as compared to selecting adder input based on CompressedF // *** consider gating PCPlusUpperF to provide the reset. +/* -----\/----- EXCLUDED -----\/----- + assign PCPlus2or4F[0] = '0; + assign PCPlus2or4F[1] = CompressedF ^ PCF[1]; + assign PCPlus2or4F[`XLEN-1:2] = CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlusUpperF; + -----/\----- EXCLUDED -----/\----- */ + always_comb if(reset) PCPlus2or4F = '0; else if (CompressedF) // add 2 diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 5a6efe0b..546beeca 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -37,7 +37,7 @@ module spillsupport #(parameter CACHE_ENABLED) input logic reset, input logic StallF, Flush, input logic [`XLEN-1:0] PCF, - input logic [`XLEN-3:0] PCPlusUpperF, + input logic [`XLEN-1:2] PCPlusUpperF, input logic [`XLEN-1:0] PCNextF, input logic [31:0] InstrRawF, input logic IFUCacheBusStallF, From e7702e48b748680713bd24217e85fce6e07ea76d Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 14:43:30 -0800 Subject: [PATCH 15/31] FPU remove unused signals --- pipelined/regression/lint-wally | 5 +++-- pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv | 5 +---- pipelined/src/fpu/fma/fma.sv | 3 +-- pipelined/src/fpu/fma/fmaadd.sv | 2 +- pipelined/src/fpu/fpu.sv | 11 +++++------ pipelined/src/fpu/postproc/postprocess.sv | 7 ++----- pipelined/src/fpu/postproc/resultsign.sv | 1 - pipelined/src/fpu/postproc/roundsign.sv | 3 --- pipelined/src/ifu/spillsupport.sv | 2 +- pipelined/src/uncore/uncore.sv | 3 +-- 10 files changed, 15 insertions(+), 27 deletions(-) diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index 705fbd61..eaeb1f51 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -5,9 +5,10 @@ export PATH=$PATH:/usr/local/bin/ verilator=`which verilator` basepath=$(dirname $0)/.. -for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do +#for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do +for config in rv64gc; do echo "$config linting..." - if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes); then + if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes --Wall); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index ae927c97..06f39a3e 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -37,7 +37,7 @@ module fdivsqrtqsel2 ( ); logic [3:0] p, g; - logic magnitude, sign, cout; + logic magnitude, sign; logic pos, neg; // The quotient selection logic is presented for simplicity, not @@ -48,9 +48,6 @@ module fdivsqrtqsel2 ( assign p = ps ^ pc; assign g = ps & pc; - //assign magnitude = ~(&p[2:0]); - assign cout = g[2] | (p[2] & (g[1] | p[1] & g[0])); - //assign sign = p[3] ^ cout; assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & (ps[0]^pc[0])); assign sign = (ps[3]^pc[3])^ diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index fa71d905..6a872d6d 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -41,7 +41,6 @@ module fma( output logic ZmSticky, // sticky bit that is calculated during alignment output logic KillProd, // set the product to zero before addition if the product is too small to matter output logic [3*`NF+5:0] Sm, // the positive sum's significand - output logic NegSum, // was the sum negitive output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A) output logic As, // the aligned addend's sign (modified Z sign for other opperations) output logic Ps, // the product's sign @@ -84,7 +83,7 @@ module fma( // // Addition/LZA // /////////////////////////////////////////////////////////////////////////////// - fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .NegSum, .InvA, .Sm, .Se, .Ss); + fmaadd add(.Am, .Pm, .Ze, .Pe, .Ps, .As, .KillProd, .ZmSticky, .AmInv, .PmKilled, .InvA, .Sm, .Se, .Ss); fmalza #(3*`NF+6) lza(.A(AmInv), .Pm({PmKilled, 1'b0, InvA&Ps&ZmSticky&KillProd}), .Cin(InvA & ~(ZmSticky & ~KillProd)), .sub(InvA), .SCnt); endmodule diff --git a/pipelined/src/fpu/fma/fmaadd.sv b/pipelined/src/fpu/fma/fmaadd.sv index 2b5d2c4a..16cf6b05 100644 --- a/pipelined/src/fpu/fma/fmaadd.sv +++ b/pipelined/src/fpu/fma/fmaadd.sv @@ -41,12 +41,12 @@ module fmaadd( input logic [`NE+1:0] Pe, output logic [3*`NF+5:0] AmInv, // aligned addend possibly inverted output logic [2*`NF+1:0] PmKilled, // the product's mantissa possibly killed - output logic NegSum, // was the sum negitive output logic Ss, output logic [`NE+1:0] Se, output logic [3*`NF+5:0] Sm // the positive sum ); logic [3*`NF+5:0] PreSum, NegPreSum; // possibly negitive sum + logic NegSum; // was the sum negitive /////////////////////////////////////////////////////////////////////////////// // Addition diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 4b73a71b..c264cff3 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -113,7 +113,6 @@ module fpu ( logic [`NE+1:0] SeE,SeM; logic KillProdE, KillProdM; logic InvAE, InvAM; - logic NegSumE, NegSumM; logic AsE, AsM; logic PsE, PsM; logic SsE, SsM; @@ -258,7 +257,7 @@ module fpu ( .OpCtrl(OpCtrlE), .Fmt(FmtE), .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), .Sm(SmE), .Pe(PeE), - .NegSum(NegSumE), .InvA(InvAE), .SCnt(SCntE), + .InvA(InvAE), .SCnt(SCntE), .ZmSticky(ZmStickyE), .KillProd(KillProdE)); // divide and squareroot @@ -355,9 +354,9 @@ module fpu ( flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM); flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM); flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, PeE, PeM); - flopenrc #($clog2(3*`NF+7)+9+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, - {ZmStickyE, KillProdE, InvAE, SCntE, NegSumE, AsE, PsE, SsE, SeE}, - {ZmStickyM, KillProdM, InvAM, SCntM, NegSumM, AsM, PsM, SsM, SeM}); + flopenrc #($clog2(3*`NF+7)+8+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, + {ZmStickyE, KillProdE, InvAE, SCntE, AsE, PsE, SsE, SeE}, + {ZmStickyM, KillProdM, InvAM, SCntM, AsM, PsM, SsM, SeM}); flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, {CeE, CvtShiftAmtE, CvtResDenormUfE, CsE, IntZeroE, CvtLzcInE}, {CeM, CvtShiftAmtM, CvtResDenormUfM, CsM, IntZeroM, CvtLzcInM}); @@ -379,7 +378,7 @@ module fpu ( postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), .FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */ - .FmaNegSum(NegSumM), .FmaInvA(InvAM), .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), + .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), .CvtCe(CeM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM), .CvtLzcIn(CvtLzcInM), .IntZero(IntZeroM), .PostProcSel(PostProcSelM), .PostProcRes(PostProcResM), .PostProcFlg(PostProcFlgM), .FCvtIntRes(FCvtIntResM)); diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv index bcac6de5..e5577a9e 100644 --- a/pipelined/src/fpu/postproc/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -52,8 +52,6 @@ module postprocess ( input logic [3*`NF+5:0] FmaSm, // the positive sum input logic FmaZmS, // sticky bit that is calculated during alignment input logic FmaKillProd, // set the product to zero before addition if the product is too small to matter - input logic FmaNegSum, // was the sum negitive - input logic FmaInvA, // do you invert Z input logic FmaSs, input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count //divide signals @@ -196,8 +194,7 @@ module postprocess ( // round to nearest max magnitude - roundsign roundsign(.FmaPs, .FmaAs, .FmaInvA, .FmaOp, .DivOp, .CvtOp, .FmaNegSum, - .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms); + roundsign roundsign(.FmaOp, .DivOp, .CvtOp, .Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms); round round(.OutFmt, .Frm, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe, .Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResDenormUf, .Mf, .ToInt, .CvtResUf, @@ -208,7 +205,7 @@ module postprocess ( // Sign calculation /////////////////////////////////////////////////////////////////////////////// - resultsign resultsign(.Frm, .FmaPs, .FmaAs, .FmaMe, .R, .S, .G, + resultsign resultsign(.Frm, .FmaPs, .FmaAs, .R, .S, .G, .FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Ws); /////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/fpu/postproc/resultsign.sv b/pipelined/src/fpu/postproc/resultsign.sv index cd7a096f..2e1a3cf0 100644 --- a/pipelined/src/fpu/postproc/resultsign.sv +++ b/pipelined/src/fpu/postproc/resultsign.sv @@ -35,7 +35,6 @@ module resultsign( input logic ZInf, input logic InfIn, input logic FmaOp, - input logic [`NE+1:0] FmaMe, input logic FmaSZero, input logic Mult, input logic R, diff --git a/pipelined/src/fpu/postproc/roundsign.sv b/pipelined/src/fpu/postproc/roundsign.sv index 1618f501..b8c15518 100644 --- a/pipelined/src/fpu/postproc/roundsign.sv +++ b/pipelined/src/fpu/postproc/roundsign.sv @@ -30,11 +30,8 @@ `include "wally-config.vh" module roundsign( - input logic FmaPs, FmaAs, - input logic FmaInvA, input logic Xs, input logic Ys, - input logic FmaNegSum, input logic Sqrt, input logic FmaOp, input logic DivOp, diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 5a6efe0b..9f2c4aea 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -63,7 +63,7 @@ module spillsupport #(parameter CACHE_ENABLED) mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); // select between PCNextF and PCF+2 mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), .y(PCNextFSpill)); - // select between PCF adn PCF+2 + // select between PCF and PCF+2 mux2 #(`XLEN) pcspillmux(.d0(PCF), .d1(PCPlus2F), .s(SelSpillF), .y(PCFSpill)); assign SpillF = &PCF[$clog2(SPILLTHRESHOLD)+1:1]; diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index d782ce7a..3cde211c 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -201,8 +201,7 @@ module uncore ( // takes more than 1 cycle to repsond it needs to hold on to the old select until the // device is ready. Hense this register must be selectively enabled by HREADY. // However on reset None must be seleted. - flopenr #(10) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions[10:1], {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); - flopenl #(1) hseldelayreg2(HCLK, ~HRESETn, HREADY, HSELRegions[0], 1'b1, HSELNoneD); + flopenl #(11) hseldelayreg(HCLK, ~HRESETn, HREADY, HSELRegions, 11'b1, {HSELDTIMD, HSELIROMD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD, HSELNoneD}); flopenr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HREADY, HSELBRIDGE, HSELBRIDGED); endmodule From 65cbff928375e2f2df6c93995b9790ae2888c70d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 17:01:20 -0600 Subject: [PATCH 16/31] Changed long names of vectored pcm signals. --- pipelined/src/privileged/csr.sv | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 23104f7f..d12bd100 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -97,7 +97,7 @@ module csr #(parameter logic IllegalCSRMWriteReadonlyM; logic [`XLEN-1:0] CSRReadVal2M; logic [11:0] MIP_REGW_writeable; - logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector, NextFaultMtvalM; + logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic MTrapM, STrapM; @@ -126,26 +126,26 @@ module csr #(parameter // > Allowing coarser alignments in Vectored mode enables vectoring to be // > implemented without a hardware adder circuit. // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with - // [untested] PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:7], CauseM[3:0], 4'b0000} + // [untested] TrapVector = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000} // However, this is program dependent, so not implemented at this time. always_comb - if (NextPrivilegeModeM == `S_MODE) PrivilegedTrapVector = STVEC_REGW; - else PrivilegedTrapVector = MTVEC_REGW; + if (NextPrivilegeModeM == `S_MODE) TVec = STVEC_REGW; + else TVec = MTVEC_REGW; if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec always_comb - if (PrivilegedTrapVector[1:0] == 2'b01 & InterruptM) - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00}; + if (TVec[1:0] == 2'b01 & InterruptM) + TrapVector = {TVec[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00}; else - PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; + TrapVector = {TVec[`XLEN-1:2], 2'b00}; end else begin - assign PrivilegedVectoredTrapVector = {PrivilegedTrapVector[`XLEN-1:2], 2'b00}; + assign TrapVector = {TVec[`XLEN-1:2], 2'b00}; end always_comb - if (TrapM) PrivilegedNextPCM = PrivilegedVectoredTrapVector; + if (TrapM) PrivilegedNextPCM = TrapVector; else if (mretM) PrivilegedNextPCM = MEPC_REGW; else PrivilegedNextPCM = SEPC_REGW; From 35ad49502f446bba6a4124977e8b8f705a8d2453 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 17:34:11 -0600 Subject: [PATCH 17/31] Implement FENCE.I as NOP when ZIFENCEI is not supported. --- pipelined/src/ieu/controller.sv | 6 +++++- pipelined/src/ifu/ifu.sv | 4 ++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index d1aa1b8e..1565656c 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -127,7 +127,10 @@ module controller( 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // illegal instruction 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // flw - only legal if FP supported - 7'b0001111: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence + 7'b0001111: if(`ZIFENCEI_SUPPORTED) + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence + else + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence 7'b0010011: ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc 7'b0011011: if (`XLEN == 64) @@ -180,6 +183,7 @@ module controller( assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUInstrFaultD ? `CTRLW'b0 : ControlsD; + assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 427e9038..7f1f10f3 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -285,10 +285,10 @@ module ifu ( // PCNextF logic //////////////////////////////////////////////////////////////////////////////////////////////// -// if(`ICACHE | `ZICSR_SUPPORTED) + if(`ICACHE | `ZIFENCEI_SUPPORTED) mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F)); // mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F)); -// else assign PCNext2F = PCNext1F; + else assign PCNext2F = PCNext1F; if(`ZICSR_SUPPORTED) begin logic PrivilegedChangePCM; assign PrivilegedChangePCM = RetM | TrapM; From 8f640f050f8ef517c054173c0d23942b993c5004 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 15:38:30 -0800 Subject: [PATCH 18/31] IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI --- pipelined/src/ieu/controller.sv | 2 +- pipelined/src/ifu/ifu.sv | 13 ++++++------- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index 1565656c..85da2a0c 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -130,7 +130,7 @@ module controller( 7'b0001111: if(`ZIFENCEI_SUPPORTED) ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence else - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop 7'b0010011: ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc 7'b0011011: if (`XLEN == 64) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 7f1f10f3..8952b355 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -285,16 +285,15 @@ module ifu ( // PCNextF logic //////////////////////////////////////////////////////////////////////////////////////////////// - if(`ICACHE | `ZIFENCEI_SUPPORTED) + if(`ZICSR_SUPPORTED | `ZIFENCEI_SUPPORTED) mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F)); -// mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F)); else assign PCNext2F = PCNext1F; if(`ZICSR_SUPPORTED) begin - logic PrivilegedChangePCM; - assign PrivilegedChangePCM = RetM | TrapM; - mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), - .y(UnalignedPCNextF)); - end else assign UnalignedPCNextF = PCNext2F; + logic PrivilegedChangePCM; + assign PrivilegedChangePCM = RetM | TrapM; + mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF)); + end else + assign UnalignedPCNextF = PCNext2F; assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); From 97593e8a6f4d81026ee7a6ba2fa72c67d7fd130d Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 17:55:45 -0600 Subject: [PATCH 19/31] Moved privileged pc logic into privileged unit. --- pipelined/src/ifu/ifu.sv | 14 +++++--------- pipelined/src/privileged/csr.sv | 10 ++++++++-- pipelined/src/privileged/privileged.sv | 8 ++++---- pipelined/src/wally/wallypipelinedcore.sv | 12 ++++++------ 4 files changed, 23 insertions(+), 21 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 7f1f10f3..913abf71 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -54,7 +54,8 @@ module ifu ( // Mem input logic RetM, TrapM, output logic CommittedF, - input logic [`XLEN-1:0] PrivilegedNextPCM, + input logic [`XLEN-1:0] UnalignedPCNextF, + output logic [`XLEN-1:0] PCNext2F, input logic CSRWriteFenceM, input logic InvalidateICacheM, output logic [31:0] InstrD, InstrM, @@ -85,7 +86,7 @@ module ifu ( output logic ICacheAccess, output logic ICacheMiss ); - (* mark_debug = "true" *) logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; + (* mark_debug = "true" *) logic [`XLEN-1:0] PCNextF; logic BranchMisalignedFaultE; logic IllegalCompInstrD; logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; @@ -116,7 +117,7 @@ module ifu ( logic GatedStallF; (* mark_debug = "true" *) logic [31:0] PostSpillInstrRawF; // branch predictor signal - logic [`XLEN-1:0] PCNext1F, PCNext2F, PCNext0F; + logic [`XLEN-1:0] PCNext1F, PCNext0F; logic BusCommittedF, CacheCommittedF; logic SelIROM; @@ -289,12 +290,7 @@ module ifu ( mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(NextValidPCE), .s(CSRWriteFenceM),.y(PCNext2F)); // mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCM+4), .s(CSRWriteFenceM),.y(PCNext2F)); else assign PCNext2F = PCNext1F; - if(`ZICSR_SUPPORTED) begin - logic PrivilegedChangePCM; - assign PrivilegedChangePCM = RetM | TrapM; - mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), - .y(UnalignedPCNextF)); - end else assign UnalignedPCNextF = PCNext2F; + assign PCNextF = {UnalignedPCNextF[`XLEN-1:1], 1'b0}; // hart-SPEC p. 21 about 16-bit alignment flopenl #(`XLEN) pcreg(clk, reset, ~StallF, PCNextF, `RESET_VECTOR, PCF); diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index d12bd100..fc9a9f68 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -40,7 +40,7 @@ module csr #(parameter input logic FlushE, FlushM, FlushW, input logic StallE, StallM, StallW, input logic [31:0] InstrM, - input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, + input logic [`XLEN-1:0] PCM, SrcAM, IEUAdrM, PCNext2F, input logic CSRReadM, CSRWriteM, TrapM, mretM, sretM, wfiM, InterruptM, input logic MTimerInt, MExtInt, SExtInt, MSwInt, input logic [63:0] MTIME_CLINT, @@ -70,7 +70,7 @@ module csr #(parameter input logic [4:0] SetFflagsM, output logic [2:0] FRM_REGW, - output logic [`XLEN-1:0] CSRReadValW, PrivilegedNextPCM, + output logic [`XLEN-1:0] CSRReadValW, UnalignedPCNextF, output logic IllegalCSRAccessM, BigEndianM ); @@ -100,6 +100,8 @@ module csr #(parameter logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic MTrapM, STrapM; + logic [`XLEN-1:0] PrivilegedNextPCM; + logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; @@ -149,6 +151,10 @@ module csr #(parameter else if (mretM) PrivilegedNextPCM = MEPC_REGW; else PrivilegedNextPCM = SEPC_REGW; + logic PrivilegedChangePCM; + assign PrivilegedChangePCM = mretM | sretM | TrapM; + mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF)); + /////////////////////////////////////////// // CSRWriteValM /////////////////////////////////////////// diff --git a/pipelined/src/privileged/privileged.sv b/pipelined/src/privileged/privileged.sv index 74e0c8ac..ef805a8a 100644 --- a/pipelined/src/privileged/privileged.sv +++ b/pipelined/src/privileged/privileged.sv @@ -33,10 +33,10 @@ module privileged ( input logic FlushD, FlushE, FlushM, FlushW, StallD, StallE, StallM, StallW, (* mark_debug = "true" *) input logic CSRReadM, CSRWriteM, input logic [`XLEN-1:0] SrcAM, - input logic [`XLEN-1:0] PCM, + input logic [`XLEN-1:0] PCM, PCNext2F, input logic [31:0] InstrM, output logic [`XLEN-1:0] CSRReadValW, - output logic [`XLEN-1:0] PrivilegedNextPCM, + output logic [`XLEN-1:0] UnalignedPCNextF, output logic RetM, TrapM, output logic sfencevmaM, input logic InstrValidM, CommittedM, CommittedF, @@ -122,7 +122,7 @@ module privileged ( csr csr(.clk, .reset, .FlushE, .FlushM, .FlushW, .StallE, .StallM, .StallW, - .InstrM, .PCM, .SrcAM, .IEUAdrM, + .InstrM, .PCM, .SrcAM, .IEUAdrM, .PCNext2F, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, .MTIME_CLINT, @@ -142,7 +142,7 @@ module privileged ( .PMPADDR_ARRAY_REGW, .SetFflagsM, .FRM_REGW, - .CSRReadValW,.PrivilegedNextPCM, + .CSRReadValW,.UnalignedPCNextF, .IllegalCSRAccessM, .BigEndianM); privpiperegs ppr(.clk, .reset, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index ef6cdc1e..f33d0f4a 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -69,7 +69,7 @@ module wallypipelinedcore ( logic [`XLEN-1:0] PCF, PCD, PCE, PCLinkE; (* mark_debug = "true" *) logic [`XLEN-1:0] PCM; logic [`XLEN-1:0] CSRReadValW, MDUResultW; - logic [`XLEN-1:0] PrivilegedNextPCM; + logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F; (* mark_debug = "true" *) logic [1:0] MemRWM; (* mark_debug = "true" *) logic InstrValidM; logic InstrMisalignedFaultM; @@ -173,7 +173,7 @@ module wallypipelinedcore ( .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .FlushW, // Fetch - .HRDATA, .PCF, .IFUHADDR, + .HRDATA, .PCF, .IFUHADDR, .PCNext2F, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, .ICacheAccess, .ICacheMiss, @@ -183,7 +183,7 @@ module wallypipelinedcore ( .BPPredWrongE, // Mem - .RetM, .TrapM, .CommittedF, .PrivilegedNextPCM, .InvalidateICacheM, .CSRWriteFenceM, + .RetM, .TrapM, .CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM, .InstrD, .InstrM, .PCM, .InstrClassM, .BPPredDirWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredClassNonCFIWrongM, @@ -334,8 +334,8 @@ module wallypipelinedcore ( .clk, .reset, .FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW, - .CSRReadM, .CSRWriteM, .SrcAM, .PCM, - .InstrM, .CSRReadValW, .PrivilegedNextPCM, + .CSRReadM, .CSRWriteM, .SrcAM, .PCM, .PCNext2F, + .InstrM, .CSRReadValW, .UnalignedPCNextF, .RetM, .TrapM, .sfencevmaM, .InstrValidM, .CommittedM, .CommittedF, @@ -362,7 +362,7 @@ module wallypipelinedcore ( ); end else begin assign CSRReadValW = 0; - assign PrivilegedNextPCM = 0; + assign UnalignedPCNextF = PCNext2F; assign RetM = 0; assign TrapM = 0; assign wfiM = 0; From 80be2e7be5b845a1302a47ae47f21b7187b71862 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 20 Dec 2022 18:05:44 -0600 Subject: [PATCH 20/31] privileged pc mux cleanup. --- pipelined/src/privileged/csr.sv | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index fc9a9f68..c14a7a00 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -100,8 +100,8 @@ module csr #(parameter logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic MTrapM, STrapM; - logic [`XLEN-1:0] PrivilegedNextPCM; - + logic [`XLEN-1:0] XEPC_REG; + logic RetM; logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; @@ -146,14 +146,10 @@ module csr #(parameter assign TrapVector = {TVec[`XLEN-1:2], 2'b00}; end - always_comb - if (TrapM) PrivilegedNextPCM = TrapVector; - else if (mretM) PrivilegedNextPCM = MEPC_REGW; - else PrivilegedNextPCM = SEPC_REGW; - - logic PrivilegedChangePCM; - assign PrivilegedChangePCM = mretM | sretM | TrapM; - mux2 #(`XLEN) pcmux3(.d0(PCNext2F), .d1(PrivilegedNextPCM), .s(PrivilegedChangePCM), .y(UnalignedPCNextF)); + assign RetM = mretM | sretM; + mux2 #(`XLEN) xepcMux(SEPC_REGW, MEPC_REGW, mretM, XEPC_REG); + mux3 #(`XLEN) pcmux3(PCNext2F, XEPC_REG, TrapVector, {TrapM, RetM}, UnalignedPCNextF); + /////////////////////////////////////////// // CSRWriteValM From dd0a02f0c8b4902232bb44745df067c08fbfbdb3 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 16:24:04 -0800 Subject: [PATCH 21/31] Converted tvecmux to structural --- pipelined/regression/lint-wally | 2 +- pipelined/src/privileged/csr.sv | 17 ++++++++++------- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/pipelined/regression/lint-wally b/pipelined/regression/lint-wally index eaeb1f51..b51797e6 100755 --- a/pipelined/regression/lint-wally +++ b/pipelined/regression/lint-wally @@ -8,7 +8,7 @@ basepath=$(dirname $0)/.. #for config in rv32e rv64gc rv32gc rv32ic rv32i rv64i rv64fpquad; do for config in rv64gc; do echo "$config linting..." - if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes --Wall); then + if !($verilator --lint-only "$@" --top-module wallypipelinedsoc "-I$basepath/config/shared" "-I$basepath/config/$config" $basepath/src/*/*.sv $basepath/src/*/*/*.sv --relative-includes ); then echo "Exiting after $config lint due to errors or warnings" exit 1 fi diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index c14a7a00..75e63589 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -100,8 +100,9 @@ module csr #(parameter logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; logic MTrapM, STrapM; - logic [`XLEN-1:0] XEPC_REG; + logic [`XLEN-1:0] EPC; logic RetM; + logic SelMtvec; logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; @@ -120,7 +121,7 @@ module csr #(parameter endcase /////////////////////////////////////////// - // Trap Vectoring + // Trap Vectoring & Returns /////////////////////////////////////////// // // POSSIBLE OPTIMIZATION: @@ -131,9 +132,8 @@ module csr #(parameter // [untested] TrapVector = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000} // However, this is program dependent, so not implemented at this time. - always_comb - if (NextPrivilegeModeM == `S_MODE) TVec = STVEC_REGW; - else TVec = MTVEC_REGW; + assign SelMtvec = (NextPrivilegeModeM == `M_MODE); + mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvec, TVec); if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec always_comb @@ -146,9 +146,12 @@ module csr #(parameter assign TrapVector = {TVec[`XLEN-1:2], 2'b00}; end + // Trap Returns + // A trap sets the PC to TrapVector + // A return sets the PC to MEPC or SEPC assign RetM = mretM | sretM; - mux2 #(`XLEN) xepcMux(SEPC_REGW, MEPC_REGW, mretM, XEPC_REG); - mux3 #(`XLEN) pcmux3(PCNext2F, XEPC_REG, TrapVector, {TrapM, RetM}, UnalignedPCNextF); + mux2 #(`XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC); + mux3 #(`XLEN) pcmux3(PCNext2F, EPC, TrapVector, {TrapM, RetM}, UnalignedPCNextF); /////////////////////////////////////////// From 5d91b3044f1ca9ab23b9254f7e582e8cd0906054 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 20 Dec 2022 16:53:09 -0800 Subject: [PATCH 22/31] Clean up vecgtored interrupts --- pipelined/src/privileged/csr.sv | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 75e63589..f68c9d88 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -97,12 +97,13 @@ module csr #(parameter logic IllegalCSRMWriteReadonlyM; logic [`XLEN-1:0] CSRReadVal2M; logic [11:0] MIP_REGW_writeable; - logic [`XLEN-1:0] TVec, TrapVector, NextFaultMtvalM; + logic [`XLEN-1:0] TVecM, TrapVectorM, NextFaultMtvalM; logic MTrapM, STrapM; logic [`XLEN-1:0] EPC; logic RetM; - logic SelMtvec; + logic SelMtvecM; + logic [`XLEN-1:0] TVecAlignedM; logic InstrValidNotFlushedM; assign InstrValidNotFlushedM = ~StallW & ~FlushW; @@ -129,30 +130,30 @@ module csr #(parameter // > Allowing coarser alignments in Vectored mode enables vectoring to be // > implemented without a hardware adder circuit. // For example, we could require m/stvec be aligned on 7 bits to let us replace the adder directly below with - // [untested] TrapVector = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000} + // [untested] TrapVectorM = {TVec[`XLEN-1:7], CauseM[3:0], 4'b0000} // However, this is program dependent, so not implemented at this time. - assign SelMtvec = (NextPrivilegeModeM == `M_MODE); - mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvec, TVec); + // Select trap vector from STVEC or MTVEC and word-align + assign SelMtvecM = (NextPrivilegeModeM == `M_MODE); + mux2 #(`XLEN) tvecmux(STVEC_REGW, MTVEC_REGW, SelMtvecM, TVecM); + assign TVecAlignedM = {TVecM[`XLEN-1:2], 2'b00}; + // Support vectored interrupts if(`VECTORED_INTERRUPTS_SUPPORTED) begin:vec - always_comb - if (TVec[1:0] == 2'b01 & InterruptM) - TrapVector = {TVec[`XLEN-1:2] + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM}, 2'b00}; - else - TrapVector = {TVec[`XLEN-1:2], 2'b00}; - end - else begin - assign TrapVector = {TVec[`XLEN-1:2], 2'b00}; - end + logic VectoredM; + logic [`XLEN-1:0] TVecPlusCauseM; + assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01); + assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; + mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); + end else + assign TrapVectorM = TVecAlignedM; // Trap Returns // A trap sets the PC to TrapVector // A return sets the PC to MEPC or SEPC assign RetM = mretM | sretM; mux2 #(`XLEN) epcmux(SEPC_REGW, MEPC_REGW, mretM, EPC); - mux3 #(`XLEN) pcmux3(PCNext2F, EPC, TrapVector, {TrapM, RetM}, UnalignedPCNextF); - + mux3 #(`XLEN) pcmux3(PCNext2F, EPC, TrapVectorM, {TrapM, RetM}, UnalignedPCNextF); /////////////////////////////////////////// // CSRWriteValM From fe723af1af8a5a86976992337f870cd8ce998a8a Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 08:35:43 -0600 Subject: [PATCH 23/31] Comments about PC+2/4. --- pipelined/src/ifu/ifu.sv | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index e1747311..f48c0c88 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -301,10 +301,16 @@ module ifu ( // *** consider gating PCPlusUpperF to provide the reset. /* -----\/----- EXCLUDED -----\/----- assign PCPlus2or4F[0] = '0; - assign PCPlus2or4F[1] = CompressedF ^ PCF[1]; - assign PCPlus2or4F[`XLEN-1:2] = CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlusUpperF; + assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]); + assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlusUpperF; -----/\----- EXCLUDED -----/\----- */ - +/* -----\/----- EXCLUDED -----\/----- + assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0]; + -----/\----- EXCLUDED -----/\----- */ + + // *** There is actually a bug in the regression test. We fetched an address which returns data with + // an X. This version of the code does not die because if CompressedF is an X it just defaults to the last + // option. The above code would work, but propagates the x. always_comb if(reset) PCPlus2or4F = '0; else if (CompressedF) // add 2 From a02b40cf029f2d7ae8696a32c3fa7ef4a3340106 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 08:41:47 -0600 Subject: [PATCH 24/31] Changes to wave file. --- pipelined/regression/wave.do | 437 ++++++++++++++++++----------------- 1 file changed, 221 insertions(+), 216 deletions(-) diff --git a/pipelined/regression/wave.do b/pipelined/regression/wave.do index ca7a13d9..96f3a7a0 100644 --- a/pipelined/regression/wave.do +++ b/pipelined/regression/wave.do @@ -136,7 +136,6 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE -add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 @@ -218,217 +217,218 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM -add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM -add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK -add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW -add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW -add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate -add wave -noupdate -expand -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag -add wave -noupdate -expand -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid -add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} -add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM -add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData -add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay -add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck -add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord -add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal -add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM -add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM -add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk -add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCF -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr -add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE -add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF -add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM -add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF -add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt -add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority -add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask +add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW +add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM +add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM +add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM +add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK +add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW +add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW +add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay} +add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate +add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag +add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]} +add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM} +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid +add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag} +add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM +add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData +add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay +add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck +add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord +add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM +add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM +add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal +add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM +add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM +add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk +add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCF +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr +add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE +add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF +add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM +add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF +add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM +add wave -noupdate -expand -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr +add wave -noupdate -expand -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr +add wave -noupdate -expand -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt +add wave -noupdate -expand -group plic /testbench/dut/uncore/uncore/plic/plic/SExtInt +add wave -noupdate -expand -group plic /testbench/dut/uncore/uncore/plic/plic/Dout +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intClaim +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intEn +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intInProgress +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPending +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intPriority +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/intThreshold +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/nextIntPending +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/requests +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqMatrix +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/priorities_with_irqs +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/max_priority_with_irqs +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/irqs_at_max_priority +add wave -noupdate -expand -group plic -expand -group internals /testbench/dut/uncore/uncore/plic/plic/threshMask add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsIn add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsOut add wave -noupdate -group GPIO /testbench/dut/uncore/uncore/gpio/gpio/GPIOPinsEn @@ -491,8 +491,6 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F -add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM -add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0 @@ -610,8 +608,15 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/fregfile/rf add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn add wave -noupdate /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayCntEn +add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HADDR +add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HTRANS +add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HREADY +add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HSELRegions +add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HSELNoneD +add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HSELPLICD +add wave -noupdate -expand -group uncore /testbench/dut/uncore/uncore/HRDATA TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {108364 ns} 0} +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {471877 ns} 0} quietly wave cursor active 5 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 @@ -627,4 +632,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {108270 ns} {108846 ns} +WaveRestoreZoom {471640 ns} {472086 ns} From ac94b55e7432e0ebe97fb33811d2a0d574b0f7f2 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 09:00:09 -0600 Subject: [PATCH 25/31] Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. Switched to even simplier PC+2/4 logic. --- pipelined/src/ifu/ifu.sv | 4 ++-- pipelined/src/uncore/plic_apb.sv | 5 +++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index f48c0c88..6248d3a3 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -299,11 +299,9 @@ module ifu ( // choose PC+2 or PC+4 based on CompressedF, which arrives later. // Speeds up critical path as compared to selecting adder input based on CompressedF // *** consider gating PCPlusUpperF to provide the reset. -/* -----\/----- EXCLUDED -----\/----- assign PCPlus2or4F[0] = '0; assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]); assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlusUpperF; - -----/\----- EXCLUDED -----/\----- */ /* -----\/----- EXCLUDED -----\/----- assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0]; -----/\----- EXCLUDED -----/\----- */ @@ -311,12 +309,14 @@ module ifu ( // *** There is actually a bug in the regression test. We fetched an address which returns data with // an X. This version of the code does not die because if CompressedF is an X it just defaults to the last // option. The above code would work, but propagates the x. +/* -----\/----- EXCLUDED -----\/----- always_comb if(reset) PCPlus2or4F = '0; else if (CompressedF) // add 2 if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00}; else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4 + -----/\----- EXCLUDED -----/\----- */ //////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/pipelined/src/uncore/plic_apb.sv b/pipelined/src/uncore/plic_apb.sv index 7b3a9585..fd7a4d8f 100644 --- a/pipelined/src/uncore/plic_apb.sv +++ b/pipelined/src/uncore/plic_apb.sv @@ -59,7 +59,7 @@ module plic_apb ( input logic UARTIntr,GPIOIntr, (* mark_debug = "true" *) output logic MExtInt, SExtInt); - logic memwrite, memread, initTrans; + logic memwrite, memread; logic [23:0] entry; (* mark_debug = "true" *) logic [31:0] Din, Dout; @@ -130,7 +130,8 @@ module plic_apb ( // Read synchronously because a read can have side effect of changing intInProgress if (memread) casez(entry) - 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; + 24'h000000: Dout <= #1 32'b0; // there is no intPriority[0] + 24'h0000??: Dout <= #1 {29'b0,intPriority[entry[7:2]]}; `ifdef PLIC_NUM_SRC_LT_32 24'h001000: Dout <= #1 {{(31-`N){1'b0}},intPending,1'b0}; 24'h002000: Dout <= #1 {{(31-`N){1'b0}},intEn[0],1'b0}; From 3d95aa3423abe92665063510e1ca0b9194b695cc Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 09:18:00 -0600 Subject: [PATCH 26/31] Added timeout check to testbench. A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error. --- pipelined/testbench/testbench.sv | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index bd1f4bb6..030f348d 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -428,6 +428,27 @@ logic [3:0] dummy; end end end + + // check for hange up. + logic [`XLEN-1:0] OldPCW; + integer WatchDogTimerCount; + localparam WatchDogTimerThreshold = 1000000; + logic WatchDogTimeOut; + always_ff @(posedge clk) begin + OldPCW <= PCW; + if(OldPCW == PCW) WatchDogTimerCount = WatchDogTimerCount + 1'b1; + else WatchDogTimerCount = '0; + end + + always_comb begin + WatchDogTimeOut = WatchDogTimerCount >= WatchDogTimerThreshold; + if(WatchDogTimeOut) begin + $display("FAILURE: Watch Dog Time Out triggered. PCW stuck at %x for more than %d cycles", PCW, WatchDogTimerCount); + $stop; + end + end + + endmodule module riscvassertions; From 6858b7568cbea5d5fe3cf0518afe59d8bb485d74 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 09:18:30 -0600 Subject: [PATCH 27/31] Renamed PCPlusUpperF to PCPlus4F. --- pipelined/src/ifu/ifu.sv | 14 +++++++------- pipelined/src/ifu/spillsupport.sv | 4 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 6248d3a3..19b46a0b 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -90,7 +90,7 @@ module ifu ( logic BranchMisalignedFaultE; logic IllegalCompInstrD; logic [`XLEN-1:0] PCPlus2or4F, PCLinkD; - logic [`XLEN-1:2] PCPlusUpperF; + logic [`XLEN-1:2] PCPlus4F; logic CompressedF; logic [31:0] InstrRawD, InstrRawF, IROMInstrF, ICacheInstrF; logic [31:0] FinalInstrRawF; @@ -131,7 +131,7 @@ module ifu ( if(`C_SUPPORTED) begin : SpillSupport - spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(TrapM), .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF(InstrRawF), + spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .Flush(TrapM), .PCF, .PCPlus4F, .PCNextF, .InstrRawF(InstrRawF), .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport @@ -295,13 +295,13 @@ module ifu ( // pcadder // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32 - assign PCPlusUpperF = PCF[`XLEN-1:2] + 1; // add 4 to PC + assign PCPlus4F = PCF[`XLEN-1:2] + 1; // add 4 to PC // choose PC+2 or PC+4 based on CompressedF, which arrives later. // Speeds up critical path as compared to selecting adder input based on CompressedF - // *** consider gating PCPlusUpperF to provide the reset. + // *** consider gating PCPlus4F to provide the reset. assign PCPlus2or4F[0] = '0; assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]); - assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlusUpperF; + assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlus4F; /* -----\/----- EXCLUDED -----\/----- assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0]; -----/\----- EXCLUDED -----/\----- */ @@ -313,9 +313,9 @@ module ifu ( always_comb if(reset) PCPlus2or4F = '0; else if (CompressedF) // add 2 - if (PCF[1]) PCPlus2or4F = {PCPlusUpperF, 2'b00}; + if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00}; else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; - else PCPlus2or4F = {PCPlusUpperF, PCF[1:0]}; // add 4 + else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4 -----/\----- EXCLUDED -----/\----- */ diff --git a/pipelined/src/ifu/spillsupport.sv b/pipelined/src/ifu/spillsupport.sv index 8c8c2ead..55de81f4 100644 --- a/pipelined/src/ifu/spillsupport.sv +++ b/pipelined/src/ifu/spillsupport.sv @@ -37,7 +37,7 @@ module spillsupport #(parameter CACHE_ENABLED) input logic reset, input logic StallF, Flush, input logic [`XLEN-1:0] PCF, - input logic [`XLEN-1:2] PCPlusUpperF, + input logic [`XLEN-1:2] PCPlus4F, input logic [`XLEN-1:0] PCNextF, input logic [31:0] InstrRawF, input logic IFUCacheBusStallF, @@ -60,7 +60,7 @@ module spillsupport #(parameter CACHE_ENABLED) (* mark_debug = "true" *) statetype CurrState, NextState; // compute PCF+2 - mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlusUpperF, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); + mux2 #(`XLEN) pcplus2mux(.d0({PCF[`XLEN-1:2], 2'b10}), .d1({PCPlus4F, 2'b00}), .s(PCF[1]), .y(PCPlus2F)); // select between PCNextF and PCF+2 mux2 #(`XLEN) pcnextspillmux(.d0(PCNextF), .d1(PCPlus2F), .s(SelNextSpillF & ~Flush), .y(PCNextFSpill)); // select between PCF and PCF+2 From 91f948a91ced25c9541ea46acea0a4af84fa4821 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 09:19:34 -0600 Subject: [PATCH 28/31] The optimzied PC+2/4 logic still hanges on wally32priv. --- pipelined/src/ifu/ifu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index 19b46a0b..4df8d413 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -299,9 +299,11 @@ module ifu ( // choose PC+2 or PC+4 based on CompressedF, which arrives later. // Speeds up critical path as compared to selecting adder input based on CompressedF // *** consider gating PCPlus4F to provide the reset. +/* -----\/----- EXCLUDED -----\/----- assign PCPlus2or4F[0] = '0; assign PCPlus2or4F[1] = ~reset & (CompressedF ^ PCF[1]); assign PCPlus2or4F[`XLEN-1:2] = reset ? '0 : CompressedF & ~PCF[1] ? PCF[`XLEN-1:2] : PCPlus4F; + -----/\----- EXCLUDED -----/\----- */ /* -----\/----- EXCLUDED -----\/----- assign PCPlus2or4F[1:0] = reset ? 2'b00 : CompressedF ? PCF[1] ? 2'b00 : 2'b10 : PCF[1:0]; -----/\----- EXCLUDED -----/\----- */ @@ -309,14 +311,12 @@ module ifu ( // *** There is actually a bug in the regression test. We fetched an address which returns data with // an X. This version of the code does not die because if CompressedF is an X it just defaults to the last // option. The above code would work, but propagates the x. -/* -----\/----- EXCLUDED -----\/----- always_comb if(reset) PCPlus2or4F = '0; else if (CompressedF) // add 2 if (PCF[1]) PCPlus2or4F = {PCPlus4F, 2'b00}; else PCPlus2or4F = {PCF[`XLEN-1:2], 2'b10}; else PCPlus2or4F = {PCPlus4F, PCF[1:0]}; // add 4 - -----/\----- EXCLUDED -----/\----- */ //////////////////////////////////////////////////////////////////////////////////////////////// From 0b4186f1e87f6677f1f0087363f26f7abab1842e Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 12:05:49 -0600 Subject: [PATCH 29/31] Vectored interrupts now require 64 byte alignment. Eliminates adder. --- pipelined/src/privileged/csr.sv | 3 ++- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 22 ++++++++--------- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 24 +++++++++---------- 3 files changed, 25 insertions(+), 24 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index f68c9d88..5fe94770 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -143,7 +143,8 @@ module csr #(parameter logic VectoredM; logic [`XLEN-1:0] TVecPlusCauseM; assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01); - assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; + //assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; + assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); end else assign TrapVectorM = TVecAlignedM; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index ac3d81c3..a6c1cedd 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -299,23 +299,23 @@ end_trap_triggers: // -------------------------------------------------------------------------------------------- -.align 2 +.align 6 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. - j segfault_\MODE\() // 2: reserved - j m_soft_vector_\MODE\() // 3: breakpoint - j segfault_\MODE\() // 4: reserved - j s_time_vector_\MODE\() // 5: load access fault - j segfault_\MODE\() // 6: reserved - j m_time_vector_\MODE\() // 7: store access fault - j segfault_\MODE\() // 8: reserved - j s_ext_vector_\MODE\() // 9: ecall from S-mode - j segfault_\MODE\() // 10: reserved - j m_ext_vector_\MODE\() // 11: ecall from M-mode + j segfault_\MODE\() + j m_soft_vector_\MODE\() + j segfault_\MODE\() + j s_time_vector_\MODE\() + j segfault_\MODE\() + j m_time_vector_\MODE\() + j segfault_\MODE\() + j s_ext_vector_\MODE\() + j segfault_\MODE\() + j m_ext_vector_\MODE\() // 12 through >=16 are reserved or designated for platform use trap_unvectored_\MODE\(): diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index a0691f2b..e75c339e 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -293,23 +293,23 @@ end_trap_triggers: // // -------------------------------------------------------------------------------------------- -.align 3 +.align 6 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented // otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code // No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way - j s_soft_vector_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table. - j segfault_\MODE\() // 2: reserved - j m_soft_vector_\MODE\() // 3: breakpoint - j segfault_\MODE\() // 4: reserved - j s_time_vector_\MODE\() // 5: load access fault - j segfault_\MODE\() // 6: reserved - j m_time_vector_\MODE\() // 7: store access fault - j segfault_\MODE\() // 8: reserved - j s_ext_vector_\MODE\() // 9: ecall from S-mode - j segfault_\MODE\() // 10: reserved - j m_ext_vector_\MODE\() // 11: ecall from M-mode + j s_soft_vector_\MODE\() + j segfault_\MODE\() + j m_soft_vector_\MODE\() + j segfault_\MODE\() + j s_time_vector_\MODE\() + j segfault_\MODE\() + j m_time_vector_\MODE\() + j segfault_\MODE\() + j s_ext_vector_\MODE\() + j segfault_\MODE\() + j m_ext_vector_\MODE\() // 12 through >=16 are reserved or designated for platform use trap_unvectored_\MODE\(): From c3b43b2fac67079c5a57ed8c18db4d30a2d1e089 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 21 Dec 2022 13:16:09 -0600 Subject: [PATCH 30/31] Waiting on fix for wally64periph uart test. would like to remove vectored interrupt adder. --- pipelined/src/privileged/csr.sv | 6 ++++-- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 3 ++- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 3 ++- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/pipelined/src/privileged/csr.sv b/pipelined/src/privileged/csr.sv index 5fe94770..1b2ed42e 100644 --- a/pipelined/src/privileged/csr.sv +++ b/pipelined/src/privileged/csr.sv @@ -143,8 +143,10 @@ module csr #(parameter logic VectoredM; logic [`XLEN-1:0] TVecPlusCauseM; assign VectoredM = InterruptM & (TVecM[1:0] == 2'b01); - //assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; - assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; + // *** Would like you use concat version, but breaks uart test wally64priv when + // mtvec is aligned to 64 bytes. + assign TVecPlusCauseM = TVecAlignedM + {{(`XLEN-2-`LOG_XLEN){1'b0}}, CauseM, 2'b00}; + //assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM[3:0], 2'b00}; mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); end else assign TrapVectorM = TVecAlignedM; diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index a6c1cedd..82279e92 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -299,7 +299,8 @@ end_trap_triggers: // -------------------------------------------------------------------------------------------- -.align 6 +//.align 6 +.align 2 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index e75c339e..bd43eb11 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -293,7 +293,8 @@ end_trap_triggers: // // -------------------------------------------------------------------------------------------- -.align 6 +//.align 6 +.align 3 trap_handler_\MODE\(): j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler // *** ASSUMES that a cause value of 0 for an interrupt is unimplemented From e327d70cdc3cba80ab984a5e99a48cfb1f76719d Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 21 Dec 2022 11:31:22 -0800 Subject: [PATCH 31/31] Removed unused FPU signals --- pipelined/src/fpu/fma/fma.sv | 7 ++++--- pipelined/src/fpu/fpu.sv | 17 +++++++---------- pipelined/src/fpu/postproc/fmashiftcalc.sv | 2 -- pipelined/src/fpu/postproc/postprocess.sv | 4 +--- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/pipelined/src/fpu/fma/fma.sv b/pipelined/src/fpu/fma/fma.sv index 6a872d6d..ce42aaa1 100644 --- a/pipelined/src/fpu/fma/fma.sv +++ b/pipelined/src/fpu/fma/fma.sv @@ -37,9 +37,7 @@ module fma( input logic XZero, YZero, ZZero, // is the input zero input logic [2:0] OpCtrl, // 000 = fmadd (X*Y)+Z, 001 = fmsub (X*Y)-Z, 010 = fnmsub -(X*Y)+Z, 011 = fnmadd -(X*Y)-Z, 100 = fmul (X*Y) input logic [`FMTBITS-1:0] Fmt, // format of the result single double half or quad - output logic [`NE+1:0] Pe, // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign output logic ZmSticky, // sticky bit that is calculated during alignment - output logic KillProd, // set the product to zero before addition if the product is too small to matter output logic [3*`NF+5:0] Sm, // the positive sum's significand output logic InvA, // Was A inverted for effective subtraction (P-A or -P+A) output logic As, // the aligned addend's sign (modified Z sign for other opperations) @@ -47,12 +45,15 @@ module fma( output logic Ss, // the sum's sign output logic [`NE+1:0] Se, output logic [$clog2(3*`NF+7)-1:0] SCnt // normalization shift count - ); +); logic [2*`NF+1:0] Pm; // the product's significand in U(2.2Nf) format logic [3*`NF+5:0] Am; // addend aligned's mantissa for addition in U(NF+5.2NF+1) logic [3*`NF+5:0] AmInv; // aligned addend's mantissa possibly inverted logic [2*`NF+1:0] PmKilled; // the product's mantissa possibly killed + logic KillProd; // set the product to zero before addition if the product is too small to matter + logic [`NE+1:0] Pe; // the product's exponent B(NE+2.0) format; adds 2 bits to allow for size of number and negative sign + /////////////////////////////////////////////////////////////////////////////// // Calculate the product // - When multipliying two fp numbers, add the exponents diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index c264cff3..afa645cd 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -108,10 +108,8 @@ module fpu ( // Fma Signals logic [3*`NF+5:0] SmE, SmM; - logic [`NE+1:0] PeE, PeM; logic ZmStickyE, ZmStickyM; logic [`NE+1:0] SeE,SeM; - logic KillProdE, KillProdM; logic InvAE, InvAM; logic AsE, AsM; logic PsE, PsM; @@ -256,9 +254,9 @@ module fpu ( .XZero(XZeroE), .YZero(YZeroE), .ZZero(ZZeroE), .OpCtrl(OpCtrlE), .Fmt(FmtE), .As(AsE), .Ps(PsE), .Ss(SsE), .Se(SeE), - .Sm(SmE), .Pe(PeE), + .Sm(SmE), .InvA(InvAE), .SCnt(SCntE), - .ZmSticky(ZmStickyE), .KillProd(KillProdE)); + .ZmSticky(ZmStickyE)); // divide and squareroot // - fdiv @@ -353,10 +351,9 @@ module fpu ( {XsM, YsM, XZeroM, YZeroM, ZZeroM, XInfM, YInfM, ZInfM, XNaNM, YNaNM, ZNaNM, XSNaNM, YSNaNM, ZSNaNM, ZDenormM}); flopenrc #(1) EMRegCmpFlg (clk, reset, FlushM, ~StallM, PreNVE, PreNVM); flopenrc #(3*`NF+6) EMRegFma2(clk, reset, FlushM, ~StallM, SmE, SmM); - flopenrc #(`NE+2) EMRegFma3(clk, reset, FlushM, ~StallM, PeE, PeM); - flopenrc #($clog2(3*`NF+7)+8+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, - {ZmStickyE, KillProdE, InvAE, SCntE, AsE, PsE, SsE, SeE}, - {ZmStickyM, KillProdM, InvAM, SCntM, AsM, PsM, SsM, SeM}); + flopenrc #($clog2(3*`NF+7)+7+`NE) EMRegFma4(clk, reset, FlushM, ~StallM, + {ZmStickyE, InvAE, SCntE, AsE, PsE, SsE, SeE}, + {ZmStickyM, InvAM, SCntM, AsM, PsM, SsM, SeM}); flopenrc #(`NE+`LOGCVTLEN+`CVTLEN+4) EMRegCvt(clk, reset, FlushM, ~StallM, {CeE, CvtShiftAmtE, CvtResDenormUfE, CsE, IntZeroE, CvtLzcInE}, {CeM, CvtShiftAmtM, CvtResDenormUfM, CsM, IntZeroM, CvtLzcInM}); @@ -375,8 +372,8 @@ module fpu ( assign FpLoadStoreM = FResSelM[1]; - postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), .FmaPe(PeM), - .FmaZmS(ZmStickyM), .FmaKillProd(KillProdM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), + postprocess postprocess(.Xs(XsM), .Ys(YsM), .Ze(ZeM), .Xm(XmM), .Ym(YmM), .Zm(ZmM), .Frm(FrmM), .Fmt(FmtM), + .FmaZmS(ZmStickyM), .XZero(XZeroM), .YZero(YZeroM), .ZZero(ZZeroM), .XInf(XInfM), .YInf(YInfM), .DivQm(QmM), .FmaSs(SsM), .ZInf(ZInfM), .XNaN(XNaNM), .YNaN(YNaNM), .ZNaN(ZNaNM), .XSNaN(XSNaNM), .YSNaN(YSNaNM), .ZSNaN(ZSNaNM), .FmaSm(SmM), .DivQe(QeM), /*.DivDone(DivDoneM), */ .ZDenorm(ZDenormM), .FmaAs(AsM), .FmaPs(PsM), .OpCtrl(OpCtrlM), .FmaSCnt(SCntM), .FmaSe(SeM), .CvtCe(CeM), .CvtResDenormUf(CvtResDenormUfM),.CvtShiftAmt(CvtShiftAmtM), .CvtCs(CsM), .ToInt(FWriteIntM), .DivS(DivSM), diff --git a/pipelined/src/fpu/postproc/fmashiftcalc.sv b/pipelined/src/fpu/postproc/fmashiftcalc.sv index 03209ca9..ce9ff79b 100644 --- a/pipelined/src/fpu/postproc/fmashiftcalc.sv +++ b/pipelined/src/fpu/postproc/fmashiftcalc.sv @@ -32,10 +32,8 @@ module fmashiftcalc( input logic [3*`NF+5:0] FmaSm, // the positive sum input logic [`NE-1:0] Ze, // exponent of Z - input logic [`NE+1:0] FmaPe, // X exponent + Y exponent - bias input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // normalization shift count input logic [`FMTBITS-1:0] Fmt, // precision 1 = double 0 = single - input logic FmaKillProd, // is the product set to zero input logic [`NE+1:0] FmaSe, output logic [`NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account denormal or zero results output logic FmaSZero, // is the result denormalized - calculated before LZA corection diff --git a/pipelined/src/fpu/postproc/postprocess.sv b/pipelined/src/fpu/postproc/postprocess.sv index e5577a9e..0880d33e 100644 --- a/pipelined/src/fpu/postproc/postprocess.sv +++ b/pipelined/src/fpu/postproc/postprocess.sv @@ -48,10 +48,8 @@ module postprocess ( input logic FmaAs, // the modified Z sign - depends on instruction input logic FmaPs, // the product's sign input logic [`NE+1:0] FmaSe, - input logic [`NE+1:0] FmaPe, // Product exponent input logic [3*`NF+5:0] FmaSm, // the positive sum input logic FmaZmS, // sticky bit that is calculated during alignment - input logic FmaKillProd, // set the product to zero before addition if the product is too small to matter input logic FmaSs, input logic [$clog2(3*`NF+7)-1:0] FmaSCnt, // the normalization shift count //divide signals @@ -148,7 +146,7 @@ module postprocess ( cvtshiftcalc cvtshiftcalc(.ToInt, .CvtCe, .CvtResDenormUf, .Xm, .CvtLzcIn, .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); - fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaPe, .FmaSCnt, .Fmt, .FmaKillProd, .NormSumExp, .FmaSe, + fmashiftcalc fmashiftcalc(.FmaSm, .Ze, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe, .FmaSZero, .FmaPreResultDenorm, .FmaShiftAmt, .FmaShiftIn); divshiftcalc divshiftcalc(.Fmt, .Sqrt, .DivQe, .DivQm, .DivResDenorm, .DivDenormShiftPos, .DivShiftAmt, .DivShiftIn);