From a9e884acc803c5db4bf54b558d5a70b5cab9551a Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 26 Feb 2023 17:28:05 -0800 Subject: [PATCH] Moved TLB into subdirectory of MMU --- src/mmu/tlb/tlb.sv | 121 +++++++++++++++++++++++++++++++++ src/mmu/tlb/tlbcam.sv | 62 +++++++++++++++++ src/mmu/tlb/tlbcamline.sv | 106 +++++++++++++++++++++++++++++ src/mmu/tlb/tlbcontrol.sv | 113 ++++++++++++++++++++++++++++++ src/mmu/tlb/tlblru.sv | 56 +++++++++++++++ src/mmu/tlb/tlbmixer.sv | 69 +++++++++++++++++++ src/mmu/tlb/tlbram.sv | 54 +++++++++++++++ src/mmu/tlb/tlbramline.sv | 43 ++++++++++++ src/mmu/{ => tlb}/vm64check.sv | 6 +- 9 files changed, 627 insertions(+), 3 deletions(-) create mode 100644 src/mmu/tlb/tlb.sv create mode 100644 src/mmu/tlb/tlbcam.sv create mode 100644 src/mmu/tlb/tlbcamline.sv create mode 100644 src/mmu/tlb/tlbcontrol.sv create mode 100644 src/mmu/tlb/tlblru.sv create mode 100644 src/mmu/tlb/tlbmixer.sv create mode 100644 src/mmu/tlb/tlbram.sv create mode 100644 src/mmu/tlb/tlbramline.sv rename src/mmu/{ => tlb}/vm64check.sv (90%) diff --git a/src/mmu/tlb/tlb.sv b/src/mmu/tlb/tlb.sv new file mode 100644 index 00000000..f8bf0d17 --- /dev/null +++ b/src/mmu/tlb/tlb.sv @@ -0,0 +1,121 @@ +/////////////////////////////////////////// +// tlb.sv +// +// Written: jtorrey@hmc.edu 16 February 2021 +// Modified: kmacsaigoren@hmc.edu 1 June 2021 +// Implemented SV48 on top of SV39. This included adding the SvMode signal, +// and using it to decide the translate signal and get the virtual page number +// +// Purpose: Translation lookaside buffer +// Cache of virtural-to-physical address translations +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +/** + * SV32 specs + * ---------- + * Virtual address [31:0] (32 bits) + * [________________________________] + * |--VPN1--||--VPN0--||----OFF---| + * 10 10 12 + * + * Physical address [33:0] (34 bits) + * [__________________________________] + * |---PPN1---||--PPN0--||----OFF---| + * 12 10 12 + * + * Page Table Entry [31:0] (32 bits) + * [________________________________] + * |---PPN1---||--PPN0--|||DAGUXWRV + * 12 10 ^^ + * RSW(2) -- for OS + */ + +`include "wally-config.vh" + +// The TLB will have 2**ENTRY_BITS total entries +module tlb #(parameter TLB_ENTRIES = 8, ITLB = 0) ( + input logic clk, reset, + input logic [`SVMODE_BITS-1:0] SATP_MODE, // Current address translation mode + input logic [`ASID_BITS-1:0] SATP_ASID, + input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, + input logic [1:0] STATUS_MPP, + input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor + input logic ReadAccess, + input logic WriteAccess, + input logic DisableTranslation, + input logic [`XLEN-1:0] VAdr, // address input before translation (could be physical or virtual) + input logic [`XLEN-1:0] PTE, + input logic [1:0] PageTypeWriteVal, + input logic TLBWrite, + input logic TLBFlush, + output logic [`PA_BITS-1:0] TLBPAdr, + output logic TLBMiss, + output logic TLBHit, + output logic Translate, + output logic TLBPageFault, + output logic DAPageFault +); + + logic [TLB_ENTRIES-1:0] Matches, WriteEnables, PTE_Gs; // used as the one-hot encoding of WriteIndex + // Sections of the virtual and physical addresses + logic [`VPN_BITS-1:0] VPN; + logic [`PPN_BITS-1:0] PPN; + // Sections of the page table entry + logic [7:0] PTEAccessBits; + logic [1:0] HitPageType; + logic CAMHit; + logic SV39Mode; + logic Misaligned; + logic MegapageMisaligned; + + if(`XLEN == 32) begin + assign MegapageMisaligned = |(PPN[9:0]); // must have zero PPN0 + assign Misaligned = (HitPageType == 2'b01) & MegapageMisaligned; + end else begin // 64-bit + logic GigapageMisaligned, TerapageMisaligned; + assign TerapageMisaligned = |(PPN[26:0]); // must have zero PPN2, PPN1, PPN0 + assign GigapageMisaligned = |(PPN[17:0]); // must have zero PPN1 and PPN0 + assign MegapageMisaligned = |(PPN[8:0]); // must have zero PPN0 + assign Misaligned = ((HitPageType == 2'b11) & TerapageMisaligned) | + ((HitPageType == 2'b10) & GigapageMisaligned) | + ((HitPageType == 2'b01) & MegapageMisaligned); + end + + assign VPN = VAdr[`VPN_BITS+11:12]; + + tlbcontrol #(ITLB) tlbcontrol(.SATP_MODE, .VAdr, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, + .PrivilegeModeW, .ReadAccess, .WriteAccess, .DisableTranslation, .TLBFlush, + .PTEAccessBits, .CAMHit, .Misaligned, .TLBMiss, .TLBHit, .TLBPageFault, + .DAPageFault, .SV39Mode, .Translate); + + tlblru #(TLB_ENTRIES) lru(.clk, .reset, .TLBWrite, .TLBFlush, .Matches, .CAMHit, .WriteEnables); + tlbcam #(TLB_ENTRIES, `VPN_BITS + `ASID_BITS, `VPN_SEGMENT_BITS) + tlbcam(.clk, .reset, .VPN, .PageTypeWriteVal, .SV39Mode, .TLBFlush, .WriteEnables, .PTE_Gs, + .SATP_ASID, .Matches, .HitPageType, .CAMHit); + tlbram #(TLB_ENTRIES) tlbram(.clk, .reset, .PTE, .Matches, .WriteEnables, .PPN, .PTEAccessBits, .PTE_Gs); + + // Replace segments of the virtual page number with segments of the physical + // page number. For 4 KB pages, the entire virtual page number is replaced. + // For superpages, some segments are considered offsets into a larger page. + tlbmixer Mixer(.VPN, .PPN, .HitPageType, .Offset(VAdr[11:0]), .TLBHit, .TLBPAdr); + +endmodule diff --git a/src/mmu/tlb/tlbcam.sv b/src/mmu/tlb/tlbcam.sv new file mode 100644 index 00000000..449411e2 --- /dev/null +++ b/src/mmu/tlb/tlbcam.sv @@ -0,0 +1,62 @@ +/////////////////////////////////////////// +// tlbcam.sv +// +// Written: jtorrey@hmc.edu 16 February 2021 +// Modified: kmacsaigoren@hmc.edu 1 June 2021 +// Implemented SV48 on top of SV39. This included adding the SvMode signal input and wally constants +// Mostly this was to make the cam_lines work. +// +// Purpose: Stores virtual page numbers with cached translations. +// Determines whether a given virtual page number is in the TLB. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbcam #(parameter TLB_ENTRIES = 8, KEY_BITS = 20, SEGMENT_BITS = 10) ( + input logic clk, reset, + input logic [`VPN_BITS-1:0] VPN, + input logic [1:0] PageTypeWriteVal, + input logic SV39Mode, + input logic TLBFlush, + input logic [TLB_ENTRIES-1:0] WriteEnables, + input logic [TLB_ENTRIES-1:0] PTE_Gs, + input logic [`ASID_BITS-1:0] SATP_ASID, + output logic [TLB_ENTRIES-1:0] Matches, + output logic [1:0] HitPageType, + output logic CAMHit +); + + logic [1:0] PageTypeRead [TLB_ENTRIES-1:0]; + + // TLB_ENTRIES CAM lines, each of which will independently consider + // whether the requested virtual address is a match. Each line stores the + // original virtual page number from when the address was written, regardless + // of page type. However, matches are determined based on a subset of the + // page number segments. + + tlbcamline #(KEY_BITS, SEGMENT_BITS) camlines[TLB_ENTRIES-1:0]( + .clk, .reset, .VPN, .SATP_ASID, .SV39Mode, .PTE_G(PTE_Gs), .PageTypeWriteVal, .TLBFlush, + .WriteEnable(WriteEnables), .PageTypeRead, .Match(Matches)); + assign CAMHit = |Matches & ~TLBFlush; + or_rows #(TLB_ENTRIES,2) PageTypeOr(PageTypeRead, HitPageType); +endmodule + diff --git a/src/mmu/tlb/tlbcamline.sv b/src/mmu/tlb/tlbcamline.sv new file mode 100644 index 00000000..9f7a68e8 --- /dev/null +++ b/src/mmu/tlb/tlbcamline.sv @@ -0,0 +1,106 @@ +/////////////////////////////////////////// +// tlbcamline.sv +// +// Written: tfleming@hmc.edu & jtorrey@hmc.edu 6 April 2021 +// Modified: kmacsaigoren@hmc.edu 1 June 2021 +// Implemented SV48 on top of SV39. This included adding SvMode input signal and the wally constants +// Mostly this was done to make the PageNumberMixer work. +// +// Purpose: CAM line for the translation lookaside buffer (TLB) +// Determines whether a virtual page number matches the stored key. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbcamline #(parameter KEY_BITS = 20, SEGMENT_BITS = 10) ( + input logic clk, reset, + input logic [`VPN_BITS-1:0] VPN, // The requested page number to compare against the key + input logic [`ASID_BITS-1:0] SATP_ASID, + input logic SV39Mode, + input logic WriteEnable, // Write a new entry to this line + input logic PTE_G, + input logic [1:0] PageTypeWriteVal, + input logic TLBFlush, // Flush this line (set valid to 0) + output logic [1:0] PageTypeRead, // *** should this be the stored version or the always updated one? + output logic Match +); + + // PageTypeRead is a key for a tera, giga, mega, or kilopage. + // PageType == 2'b00 --> kilopage + // PageType == 2'b01 --> megapage + // PageType == 2'b10 --> gigapage + // PageType == 2'b11 --> terapage + + // This entry has KEY_BITS for the key plus one valid bit. + logic Valid; + logic [KEY_BITS-1:0] Key; + logic [1:0] PageType; + + // Split up key and query into sections for each page table level. + logic [`ASID_BITS-1:0] Key_ASID; + logic [SEGMENT_BITS-1:0] Key0, Key1, Query0, Query1; + logic MatchASID, Match0, Match1; + + assign MatchASID = (SATP_ASID == Key_ASID) | PTE_G; + + if (`XLEN == 32) begin: match + + assign {Key_ASID, Key1, Key0} = Key; + assign {Query1, Query0} = VPN; + + // Calculate the actual match value based on the input vpn and the page type. + // For example, a megapage in SV32 only cares about VPN[1], so VPN[0] + // should automatically match. + assign Match0 = (Query0 == Key0) | (PageType[0]); // least signifcant section + assign Match1 = (Query1 == Key1); + + assign Match = Match0 & Match1 & MatchASID & Valid; + end else begin: match + + logic [SEGMENT_BITS-1:0] Key2, Key3, Query2, Query3; + logic Match2, Match3; + + assign {Query3, Query2, Query1, Query0} = VPN; + assign {Key_ASID, Key3, Key2, Key1, Key0} = Key; + + // Calculate the actual match value based on the input vpn and the page type. + // For example, a gigapage in SV39 only cares about VPN[2], so VPN[0] and VPN[1] + // should automatically match. + assign Match0 = (Query0 == Key0) | (PageType > 2'd0); // least signifcant section + assign Match1 = (Query1 == Key1) | (PageType > 2'd1); + assign Match2 = (Query2 == Key2) | (PageType > 2'd2); + assign Match3 = (Query3 == Key3) | SV39Mode; // this should always match in sv39 because they aren't used + + assign Match = Match0 & Match1 & Match2 & Match3 & MatchASID & Valid; + end + + // On a write, update the type of the page referred to by this line. + flopenr #(2) pagetypeflop(clk, reset, WriteEnable, PageTypeWriteVal, PageType); + assign PageTypeRead = PageType & {2{Match}}; + + // On a write, set the valid bit high and update the stored key. + // On a flush, zero the valid bit and leave the key unchanged. + // *** Might we want to update stored key right away to output match on the + // write cycle? (using a mux) + flopenr #(1) validbitflop(clk, reset, WriteEnable | TLBFlush, ~TLBFlush, Valid); + flopenr #(KEY_BITS) keyflop(clk, reset, WriteEnable, {SATP_ASID, VPN}, Key); +endmodule diff --git a/src/mmu/tlb/tlbcontrol.sv b/src/mmu/tlb/tlbcontrol.sv new file mode 100644 index 00000000..45c56f1b --- /dev/null +++ b/src/mmu/tlb/tlbcontrol.sv @@ -0,0 +1,113 @@ +/////////////////////////////////////////// +// tlbcontrol.sv +// +// Written: David_Harris@hmc.edu 5 July 2021 +// Modified: +// +// Purpose: Control signals for TLB +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbcontrol #(parameter ITLB = 0) ( + input logic [`SVMODE_BITS-1:0] SATP_MODE, + input logic [`XLEN-1:0] VAdr, + input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, + input logic [1:0] STATUS_MPP, + input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor + input logic ReadAccess, WriteAccess, + input logic DisableTranslation, + input logic TLBFlush, // Invalidate all TLB entries + input logic [7:0] PTEAccessBits, + input logic CAMHit, + input logic Misaligned, + output logic TLBMiss, + output logic TLBHit, + output logic TLBPageFault, + output logic DAPageFault, + output logic SV39Mode, + output logic Translate +); + + // Sections of the page table entry + logic [1:0] EffectivePrivilegeMode; + + logic PTE_D, PTE_A, PTE_U, PTE_X, PTE_W, PTE_R, PTE_V; // Useful PTE Control Bits + logic UpperBitsUnequal; + logic TLBAccess; + logic ImproperPrivilege; + + // Grab the sv mode from SATP and determine whether translation should occur + assign EffectivePrivilegeMode = (ITLB == 1) ? PrivilegeModeW : (STATUS_MPRV ? STATUS_MPP : PrivilegeModeW); // DTLB uses MPP mode when MPRV is 1 + assign Translate = (SATP_MODE != `NO_TRANSLATE) & (EffectivePrivilegeMode != `M_MODE) & ~DisableTranslation; + + // Determine whether TLB is being used + assign TLBAccess = ReadAccess | WriteAccess; + + // Check that upper bits are legal (all 0s or all 1s) + vm64check vm64check(.SATP_MODE, .VAdr, .SV39Mode, .UpperBitsUnequal); + + // unswizzle useful PTE bits + assign {PTE_D, PTE_A} = PTEAccessBits[7:6]; + assign {PTE_U, PTE_X, PTE_W, PTE_R, PTE_V} = PTEAccessBits[4:0]; + + // Check whether the access is allowed, page faulting if not. + if (ITLB == 1) begin:itlb // Instruction TLB fault checking + // User mode may only execute user mode pages, and supervisor mode may + // only execute non-user mode pages. + assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | + ((EffectivePrivilegeMode == `S_MODE) & PTE_U); + if(`SVADU_SUPPORTED) begin : hptwwrites + assign DAPageFault = Translate & TLBHit & ~PTE_A & ~TLBPageFault; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | UpperBitsUnequal | Misaligned | ~PTE_V)); + end else begin + // fault for software handling if access bit is off + assign DAPageFault = ~PTE_A; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | ~PTE_X | DAPageFault | UpperBitsUnequal | Misaligned | ~PTE_V)); + end + end else begin:dtlb // Data TLB fault checking + logic InvalidRead, InvalidWrite; + + // User mode may only load/store from user mode pages, and supervisor mode + // may only access user mode pages when STATUS_SUM is low. + assign ImproperPrivilege = ((EffectivePrivilegeMode == `U_MODE) & ~PTE_U) | + ((EffectivePrivilegeMode == `S_MODE) & PTE_U & ~STATUS_SUM); + // Check for read error. Reads are invalid when the page is not readable + // (and executable pages are not readable) or when the page is neither + // readable nor executable (and executable pages are readable). + assign InvalidRead = ReadAccess & ~PTE_R & (~STATUS_MXR | ~PTE_X); + // Check for write error. Writes are invalid when the page's write bit is + // low. + assign InvalidWrite = WriteAccess & ~PTE_W; + if(`SVADU_SUPPORTED) begin : hptwwrites + assign DAPageFault = Translate & TLBHit & (~PTE_A | WriteAccess & ~PTE_D) & ~TLBPageFault; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | UpperBitsUnequal | Misaligned | ~PTE_V)); + end else begin + // Fault for software handling if access bit is off or writing a page with dirty bit off + assign DAPageFault = ~PTE_A | WriteAccess & ~PTE_D; + assign TLBPageFault = (Translate & TLBHit & (ImproperPrivilege | InvalidRead | InvalidWrite | DAPageFault | UpperBitsUnequal | Misaligned | ~PTE_V)); + end + end + + assign TLBHit = CAMHit & TLBAccess; + assign TLBMiss = ~CAMHit & TLBAccess & Translate ; +endmodule diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv new file mode 100644 index 00000000..6cdb475e --- /dev/null +++ b/src/mmu/tlb/tlblru.sv @@ -0,0 +1,56 @@ +/////////////////////////////////////////// +// tlblru.sv +// +// Written: tfleming@hmc.edu & jtorrey@hmc.edu 16 February 2021 +// Modified: +// +// Purpose: Implementation of bit pseudo least-recently-used algorithm for +// cache evictions. Outputs the index of the next entry to be written. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module tlblru #(parameter TLB_ENTRIES = 8) ( + input logic clk, reset, + input logic TLBWrite, + input logic TLBFlush, + input logic [TLB_ENTRIES-1:0] Matches, + input logic CAMHit, + output logic [TLB_ENTRIES-1:0] WriteEnables +); + + logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed; + logic [TLB_ENTRIES-1:0] WriteLines; + logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed + logic AllUsed; // High if the next access causes all RU bits to be 1 + + // Find the first line not recently used + priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines)); + + // Track recently used lines, updating on a CAM Hit or TLB write + assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}}; + assign AccessLines = TLBWrite ? WriteLines : Matches; + assign RUBitsAccessed = AccessLines | RUBits; + assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none + assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; + + // enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21 + flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits); +endmodule diff --git a/src/mmu/tlb/tlbmixer.sv b/src/mmu/tlb/tlbmixer.sv new file mode 100644 index 00000000..f5555c2a --- /dev/null +++ b/src/mmu/tlb/tlbmixer.sv @@ -0,0 +1,69 @@ +/////////////////////////////////////////// +// tlbmixer.sv +// +// Written: David Harris and kmacsaigoren@hmc.edu 7 June 2021 +// Modified: +// +// +// Purpose: Takes two page numbers and replaces segments of the first page +// number with segments from the second, based on the page type. +// NOTE: this DOES NOT include the 12 bit offset, which is the same no matter the translation mode or page type. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbmixer ( + input logic [`VPN_BITS-1:0] VPN, + input logic [`PPN_BITS-1:0] PPN, + input logic [1:0] HitPageType, + input logic [11:0] Offset, + input logic TLBHit, + output logic [`PA_BITS-1:0] TLBPAdr +); + + localparam EXTRA_BITS = `PPN_BITS - `VPN_BITS; + logic [`PPN_BITS-1:0] ZeroExtendedVPN; + logic [`PPN_BITS-1:0] PageNumberMask; + logic [`PPN_BITS-1:0] PPNMixed; + + // produce PageNumberMask with 1s where virtual page number bits should be untranslaetd for superpages + if (`XLEN == 32) + // kilopage: 22 bits of PPN, 0 bits of VPN + // megapage: 12 bits of PPN, 10 bits of VPN + mux2 #(22) pnm(22'h000000, 22'h0003FF, HitPageType[0], PageNumberMask); + else + // kilopage: 44 bits of PPN, 0 bits of VPN + // megapage: 35 bits of PPN, 9 bits of VPN + // gigapage: 26 bits of PPN, 18 bits of VPN + // terapage: 17 bits of PPN, 27 bits of VPN + mux4 #(44) pnm(44'h00000000000, 44'h000000001FF, 44'h0000003FFFF, 44'h00007FFFFFF, HitPageType, PageNumberMask); + + // merge low segments of VPN with high segments of PPN decided by the pagetype. + assign ZeroExtendedVPN = {{EXTRA_BITS{1'b0}}, VPN}; // forces the VPN to be the same width as PPN. + assign PPNMixed = PPN | ZeroExtendedVPN & PageNumberMask; // + //mux2 #(1) mixmux[`PPN_BITS-1:0](ZeroExtendedVPN, PPN, PageNumberMask, PPNMixed); + //assign PPNMixed = (ZeroExtendedVPN & ~PageNumberMask) | (PPN & PageNumberMask); + // Output the hit physical address if translation is currently on. + // Provide physical address of zero if not TLBHits, to cause segmentation error if miss somehow percolated through signal + mux2 #(`PA_BITS) hitmux('0, {PPNMixed, Offset}, TLBHit, TLBPAdr); // set PA to 0 if TLB misses, to cause segementation error if this miss somehow passes through system + +endmodule diff --git a/src/mmu/tlb/tlbram.sv b/src/mmu/tlb/tlbram.sv new file mode 100644 index 00000000..febb8b6f --- /dev/null +++ b/src/mmu/tlb/tlbram.sv @@ -0,0 +1,54 @@ +/////////////////////////////////////////// +// tlbram.sv +// +// Written: jtorrey@hmc.edu & tfleming@hmc.edu 16 February 2021 +// Modified: +// +// Purpose: Stores page table entries of cached address translations. +// Outputs the physical page number and access bits of the current +// virtual address on a TLB hit. +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbram #(parameter TLB_ENTRIES = 8) ( + input logic clk, reset, + input logic [`XLEN-1:0] PTE, + input logic [TLB_ENTRIES-1:0] Matches, WriteEnables, + output logic [`PPN_BITS-1:0] PPN, + output logic [7:0] PTEAccessBits, + output logic [TLB_ENTRIES-1:0] PTE_Gs +); + + logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0]; + logic [`PPN_BITS+9:0] PageTableEntry; + + // RAM implemented with array of flops and AND/OR read logic + tlbramline #(`PPN_BITS+10) tlbramline[TLB_ENTRIES-1:0] + (.clk, .reset, .re(Matches), .we(WriteEnables), + .d(PTE[`PPN_BITS+9:0]), .q(RamRead), .PTE_G(PTE_Gs)); + or_rows #(TLB_ENTRIES, `PPN_BITS+10) PTEOr(RamRead, PageTableEntry); + + // Rename the bits read from the TLB RAM + assign PTEAccessBits = PageTableEntry[7:0]; + assign PPN = PageTableEntry[`PPN_BITS+9:10]; +endmodule diff --git a/src/mmu/tlb/tlbramline.sv b/src/mmu/tlb/tlbramline.sv new file mode 100644 index 00000000..035c58d5 --- /dev/null +++ b/src/mmu/tlb/tlbramline.sv @@ -0,0 +1,43 @@ +/////////////////////////////////////////// +// tlbramline.sv +// +// Written: David_Harris@hmc.edu 4 July 2021 +// Modified: +// +// Purpose: One line of the RAM, with enabled flip-flop and logic for reading into distributed OR +// +// Documentation: RISC-V System on Chip Design Chapter 8 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module tlbramline #(parameter WIDTH = 22) + (input logic clk, reset, + input logic re, we, + input logic [WIDTH-1:0] d, + output logic [WIDTH-1:0] q, + output logic PTE_G); + + logic [WIDTH-1:0] line; + + flopenr #(WIDTH) pteflop(clk, reset, we, d, line); + assign q = re ? line : 0; + assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching +endmodule diff --git a/src/mmu/vm64check.sv b/src/mmu/tlb/vm64check.sv similarity index 90% rename from src/mmu/vm64check.sv rename to src/mmu/tlb/vm64check.sv index a78b853e..5f12eef7 100644 --- a/src/mmu/vm64check.sv +++ b/src/mmu/tlb/vm64check.sv @@ -32,7 +32,7 @@ module vm64check ( input logic [`SVMODE_BITS-1:0] SATP_MODE, input logic [`XLEN-1:0] VAdr, output logic SV39Mode, - output logic UpperBitsUnequalPageFault + output logic UpperBitsUnequal ); if (`XLEN == 64) begin @@ -42,9 +42,9 @@ module vm64check ( logic eq_63_47, eq_46_38; assign eq_46_38 = &(VAdr[46:38]) | ~|(VAdr[46:38]); assign eq_63_47 = &(VAdr[63:47]) | ~|(VAdr[63:47]); - assign UpperBitsUnequalPageFault = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; + assign UpperBitsUnequal = SV39Mode ? ~(eq_63_47 & eq_46_38) : ~eq_63_47; end else begin assign SV39Mode = 0; - assign UpperBitsUnequalPageFault = 0; + assign UpperBitsUnequal = 0; end endmodule