From a99c0502e59461979133c36efeb2fef9d85261d0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 24 Mar 2021 15:56:55 -0500 Subject: [PATCH] Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions. --- testsBP/simple/sample.s | 19 ++- wally-pipelined/regression/wave.do | 141 ++++++++++--------- wally-pipelined/src/ieu/datapath.sv | 3 - wally-pipelined/src/privileged/csr.sv | 2 +- wally-pipelined/src/privileged/csrc.sv | 17 +-- wally-pipelined/src/privileged/csri.sv | 9 +- wally-pipelined/src/privileged/csrm.sv | 27 ++-- wally-pipelined/src/privileged/csrn.sv | 13 +- wally-pipelined/src/privileged/csrs.sv | 17 +-- wally-pipelined/src/privileged/csru.sv | 9 +- wally-pipelined/src/privileged/privileged.sv | 2 +- 11 files changed, 137 insertions(+), 122 deletions(-) diff --git a/testsBP/simple/sample.s b/testsBP/simple/sample.s index 399d3bd7..1c707cba 100644 --- a/testsBP/simple/sample.s +++ b/testsBP/simple/sample.s @@ -7,7 +7,13 @@ simple_csrbr_test: # step 1 enable the performance counters # by default the hardware enables all performance counters # however we will eventually want to manually enable incase - # some other code disables thems + # some other code disables them + + # br count is counter 5 + # br mp count is counter 4 + li t0, 0x30 + + csrrc x0, 0x320, t0 # clear bits 4 and 5 of inhibit register. # step 2 read performance counters into general purpose registers @@ -35,17 +41,20 @@ loop_done: sub t3, t5, t3 # this is the number of branch mispredictions committed. # now check if the branch count equals 100 and if the branch - bne t4, t2, fail - # *** come back to t3 - + bne t4, t2, fail + li t5, 3 + bne t3, t5, fail pass: li a0, 0 +done: + li t0, 0x30 + csrrs x0, 0x320, t0 # set bits 4 and 5 ret fail: li a0, -1 - ret + j done .data sample_data: diff --git a/wally-pipelined/regression/wave.do b/wally-pipelined/regression/wave.do index 3ab0f95c..ede2da62 100644 --- a/wally-pipelined/regression/wave.do +++ b/wally-pipelined/regression/wave.do @@ -8,36 +8,36 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM -add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/InstrStall -add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/DataStall -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM -add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallE -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallM -add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallW +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM +add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/InstrStall +add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/DataStall +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM +add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallE +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallM +add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/ifu/StallW add wave -noupdate -group Bpred -expand -group direction -color Yellow /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/GHRF add wave -noupdate -group Bpred -expand -group direction -divider Lookup add wave -noupdate -group Bpred -expand -group direction /testbench/dut/hart/ifu/bpred/Predictor/DirPredictor/LookUpPC @@ -83,10 +83,10 @@ add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrQ add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/memory add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/popPC -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE -add wave -noupdate -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE +add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNextF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCPlus2or4F @@ -96,37 +96,37 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM -add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD -add wave -noupdate -group {Decode Stage} /testbench/InstrDName -add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD -add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD -add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D -add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rf -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1 -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2 -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3 -add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3 -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW -add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags -add wave -noupdate -group alu -divider internals -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt -add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu +add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ifu/InstrD +add wave -noupdate -expand -group {Decode Stage} /testbench/InstrDName +add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD +add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD +add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D +add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D +add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf +add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 +add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 +add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 +add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1 +add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2 +add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3 +add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3 +add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW +add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW +add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW +add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW +add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags +add wave -noupdate -expand -group alu -divider internals +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt +add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu add wave -noupdate /testbench/InstrFName add wave -noupdate -group dcache /testbench/dut/hart/MemAdrM add wave -noupdate -group dcache /testbench/dut/hart/MemPAdrM @@ -173,12 +173,15 @@ add wave -noupdate -group {function radix debug} /testbench/FunctionName/Functio add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionAddr add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/ProgramAddrIndex add wave -noupdate -group {function radix debug} /testbench/FunctionName/FunctionName/FunctionName -add wave -noupdate -expand -group {performance counters} -expand /testbench/dut/hart/priv/csr/genblk1/counters/HPMCOUNTER -add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MHPMCOUNTERH add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTEN add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW +add wave -noupdate -expand -group {performance counters} /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW +add wave -noupdate /testbench/dut/hart/ieu/dp/ALUResultW +add wave -noupdate /testbench/dut/hart/ieu/dp/ResultSrcW +add wave -noupdate /testbench/dut/hart/ieu/dp/CSRReadValW +add wave -noupdate /testbench/dut/hart/priv/csr/genblk1/counters/CSRCReadValM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 7} {8084 ns} 0} +WaveRestoreCursors {{Cursor 7} {13518 ns} 0} quietly wave cursor active 1 configure wave -namecolwidth 250 configure wave -valuecolwidth 229 @@ -194,4 +197,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {6397 ns} {21325 ns} +WaveRestoreZoom {13489 ns} {13607 ns} diff --git a/wally-pipelined/src/ieu/datapath.sv b/wally-pipelined/src/ieu/datapath.sv index adcd4f6d..f94e665e 100644 --- a/wally-pipelined/src/ieu/datapath.sv +++ b/wally-pipelined/src/ieu/datapath.sv @@ -115,9 +115,6 @@ module datapath ( flopenrc #(`XLEN) ALUResultWReg(clk, reset, FlushW, ~StallW, ALUResultM, ALUResultW); flopenrc #(5) RdWEg(clk, reset, FlushW, ~StallW, RdM, RdW); - // *** something is not right here. Before the merge I found an issue with the jal instruction not writing - // the link address through the alu. - // not sure what changed. // handle Store Conditional result if atomic extension supported generate if (`A_SUPPORTED) diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv index 0c38b688..79e81303 100644 --- a/wally-pipelined/src/privileged/csr.sv +++ b/wally-pipelined/src/privileged/csr.sv @@ -28,7 +28,7 @@ module csr ( input logic clk, reset, - input logic FlushW, StallW, + input logic FlushW, StallD, StallE, StallM, StallW, input logic [31:0] InstrM, input logic [`XLEN-1:0] PCM, SrcAM, input logic CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM, diff --git a/wally-pipelined/src/privileged/csrc.sv b/wally-pipelined/src/privileged/csrc.sv index dbf21e91..ba90a48a 100644 --- a/wally-pipelined/src/privileged/csrc.sv +++ b/wally-pipelined/src/privileged/csrc.sv @@ -29,8 +29,9 @@ module csrc ( input logic clk, reset, + input logic StallD, StallE, StallM, StallW, input logic InstrValidW, LoadStallD, CSRMWriteM, BPPredWrongM, - input logic [3:0] InstrClassM, + input logic [3:0] InstrClassM, input logic [11:0] CSRAdrM, input logic [1:0] PrivilegeModeW, input logic [`XLEN-1:0] CSRWriteValM, @@ -61,10 +62,10 @@ module csrc ( logic [`COUNTERS:0] MCOUNTEN; assign MCOUNTEN[0] = 1'b1; assign MCOUNTEN[1] = 1'b0; - assign MCOUNTEN[2] = InstrValidW; - assign MCOUNTEN[3] = LoadStallD; - assign MCOUNTEN[4] = BPPredWrongM; - assign MCOUNTEN[5] = InstrClassM[0]; + assign MCOUNTEN[2] = InstrValidW & ~StallW; + assign MCOUNTEN[3] = LoadStallD & ~StallD; + assign MCOUNTEN[4] = BPPredWrongM & ~StallM; + assign MCOUNTEN[5] = InstrClassM[0] & ~StallM; assign MCOUNTEN[`COUNTERS:6] = 0; genvar j; @@ -91,7 +92,7 @@ module csrc ( // Write / update counters // Only the Machine mode versions of the counter CSRs are writable if (`XLEN==64) begin // 64-bit counters - flopr #(64) HPMCOUNTERreg_j(clk, reset, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j]); + flopenr #(64) HPMCOUNTERreg_j(clk, reset, ~StallW, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j]); end else begin // 32-bit low and high counters logic [`COUNTERS:0] WriteHPMCOUNTERHM; @@ -102,8 +103,8 @@ module csrc ( assign NextHPMCOUNTERHM[j] = WriteHPMCOUNTERHM[j] ? CSRWriteValM : HPMCOUNTERPlusM[j][63:32]; // Counter CSRs - flopr #(32) HPMCOUNTERreg_j(clk, reset, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j][31:0]); - flopr #(32) HPMCOUNTERHreg_j(clk, reset, NextHPMCOUNTERHM[j], HPMCOUNTER_REGW[j][63:32]); + flopenr #(32) HPMCOUNTERreg_j(clk, reset, ~StallW, NextHPMCOUNTERM[j], HPMCOUNTER_REGW[j][31:0]); + flopenr #(32) HPMCOUNTERHreg_j(clk, reset, ~StallW, NextHPMCOUNTERHM[j], HPMCOUNTER_REGW[j][63:32]); end end // end for diff --git a/wally-pipelined/src/privileged/csri.sv b/wally-pipelined/src/privileged/csri.sv index ee84c222..55e11b6e 100644 --- a/wally-pipelined/src/privileged/csri.sv +++ b/wally-pipelined/src/privileged/csri.sv @@ -33,6 +33,7 @@ module csri #(parameter SIE = 12'h104, SIP = 12'h144) ( input logic clk, reset, + input logic StallW, input logic CSRMWriteM, CSRSWriteM, input logic [11:0] CSRAdrM, input logic ExtIntM, TimerIntM, SwIntM, @@ -59,10 +60,10 @@ module csri #(parameter end // Interrupt Write Enables - assign WriteMIPM = CSRMWriteM && (CSRAdrM == MIP); - assign WriteMIEM = CSRMWriteM && (CSRAdrM == MIE); - assign WriteSIPM = CSRSWriteM && (CSRAdrM == SIP); - assign WriteSIEM = CSRSWriteM && (CSRAdrM == SIE); + assign WriteMIPM = CSRMWriteM && (CSRAdrM == MIP) && ~StallW; + assign WriteMIEM = CSRMWriteM && (CSRAdrM == MIE) && ~StallW; + assign WriteSIPM = CSRSWriteM && (CSRAdrM == SIP) && ~StallW; + assign WriteSIEM = CSRSWriteM && (CSRAdrM == SIE) && ~StallW; // Interrupt Pending and Enable Registers // MEIP, MTIP, MSIP are read-only diff --git a/wally-pipelined/src/privileged/csrm.sv b/wally-pipelined/src/privileged/csrm.sv index 44a840dd..dc990c2e 100644 --- a/wally-pipelined/src/privileged/csrm.sv +++ b/wally-pipelined/src/privileged/csrm.sv @@ -62,6 +62,7 @@ module csrm #(parameter DSCRATCH0 = 12'h7B2, DSCRATCH1 = 12'h7B3) ( input logic clk, reset, + input logic StallW, input logic CSRMWriteM, MTrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW, @@ -93,19 +94,19 @@ module csrm #(parameter assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISAbits}; // Write machine Mode CSRs - assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS); - assign WriteMTVECM = CSRMWriteM && (CSRAdrM == MTVEC); - assign WriteMEDELEGM = CSRMWriteM && (CSRAdrM == MEDELEG); - assign WriteMIDELEGM = CSRMWriteM && (CSRAdrM == MIDELEG); - assign WriteMSCRATCHM = CSRMWriteM && (CSRAdrM == MSCRATCH); - assign WriteMEPCM = MTrapM | (CSRMWriteM && (CSRAdrM == MEPC)); - assign WriteMCAUSEM = MTrapM | (CSRMWriteM && (CSRAdrM == MCAUSE)); - assign WriteMTVALM = MTrapM | (CSRMWriteM && (CSRAdrM == MTVAL)); - assign WritePMPCFG0M = (CSRMWriteM && (CSRAdrM == PMPCFG0)); - assign WritePMPCFG2M = (CSRMWriteM && (CSRAdrM == PMPCFG2)); - assign WritePMPADDR0M = (CSRMWriteM && (CSRAdrM == PMPADDR0)); - assign WriteMCOUNTERENM = CSRMWriteM && (CSRAdrM == MCOUNTEREN); - assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT); + assign WriteMSTATUSM = CSRMWriteM && (CSRAdrM == MSTATUS) && ~StallW; + assign WriteMTVECM = CSRMWriteM && (CSRAdrM == MTVEC) && ~StallW; + assign WriteMEDELEGM = CSRMWriteM && (CSRAdrM == MEDELEG) && ~StallW; + assign WriteMIDELEGM = CSRMWriteM && (CSRAdrM == MIDELEG) && ~StallW; + assign WriteMSCRATCHM = CSRMWriteM && (CSRAdrM == MSCRATCH) && ~StallW; + assign WriteMEPCM = MTrapM | (CSRMWriteM && (CSRAdrM == MEPC)) && ~StallW; + assign WriteMCAUSEM = MTrapM | (CSRMWriteM && (CSRAdrM == MCAUSE)) && ~StallW; + assign WriteMTVALM = MTrapM | (CSRMWriteM && (CSRAdrM == MTVAL)) && ~StallW; + assign WritePMPCFG0M = (CSRMWriteM && (CSRAdrM == PMPCFG0)) && ~StallW; + assign WritePMPCFG2M = (CSRMWriteM && (CSRAdrM == PMPCFG2)) && ~StallW; + assign WritePMPADDR0M = (CSRMWriteM && (CSRAdrM == PMPADDR0)) && ~StallW; + assign WriteMCOUNTERENM = CSRMWriteM && (CSRAdrM == MCOUNTEREN) && ~StallW; + assign WriteMCOUNTINHIBITM = CSRMWriteM && (CSRAdrM == MCOUNTINHIBIT) && ~StallW; // CSRs flopenl #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, CSRWriteValM, `XLEN'b0, MTVEC_REGW); //busybear: changed reset value to 0 diff --git a/wally-pipelined/src/privileged/csrn.sv b/wally-pipelined/src/privileged/csrn.sv index a3b3178b..2aa44bdf 100644 --- a/wally-pipelined/src/privileged/csrn.sv +++ b/wally-pipelined/src/privileged/csrn.sv @@ -36,6 +36,7 @@ module csrn #(parameter UTVAL = 12'h043, UIP = 12'h044) ( input logic clk, reset, + input logic StallW, input logic CSRNWriteM, UTrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, USTATUS_REGW, @@ -56,11 +57,11 @@ module csrn #(parameter logic [`XLEN-1:0] USCRATCH_REGW, UCAUSE_REGW, UTVAL_REGW; // Write enables - assign WriteUSTATUSM = CSRNWriteM && (CSRAdrM == USTATUS); - assign WriteUTVECM = CSRNWriteM && (CSRAdrM == UTVEC); - assign WriteUEPCM = UTrapM | (CSRNWriteM && (CSRAdrM == UEPC)); - assign WriteUCAUSEM = UTrapM | (CSRNWriteM && (CSRAdrM == UCAUSE)); - assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL)); + assign WriteUSTATUSM = CSRNWriteM && (CSRAdrM == USTATUS) && ~StallW; + assign WriteUTVECM = CSRNWriteM && (CSRAdrM == UTVEC) && ~StallW; + assign WriteUEPCM = UTrapM | (CSRNWriteM && (CSRAdrM == UEPC)) && ~StallW; + assign WriteUCAUSEM = UTrapM | (CSRNWriteM && (CSRAdrM == UCAUSE)) && ~StallW; + assign WriteUTVALM = UTrapM | (CSRNWriteM && (CSRAdrM == UTVAL)) && ~StallW; // CSRs flopenl #(`XLEN) UTVECreg(clk, reset, WriteUTVECM, CSRWriteValM, `RESET_VECTOR, UTVEC_REGW); @@ -95,4 +96,4 @@ module csrn #(parameter assign IllegalCSRNAccessM = 1; end endgenerate -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/privileged/csrs.sv b/wally-pipelined/src/privileged/csrs.sv index ede8274a..c53f98d5 100644 --- a/wally-pipelined/src/privileged/csrs.sv +++ b/wally-pipelined/src/privileged/csrs.sv @@ -41,6 +41,7 @@ module csrs #(parameter SIP= 12'h144, SATP = 12'h180) ( input logic clk, reset, + input logic StallW, input logic CSRSWriteM, STrapM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW, @@ -66,14 +67,14 @@ module csrs #(parameter logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM; logic [`XLEN-1:0] SSCRATCH_REGW, SCAUSE_REGW, STVAL_REGW; - assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS); - assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC); - assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH); - assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC)); - assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE)); - assign WriteSTVALM = STrapM | (CSRSWriteM && (CSRAdrM == STVAL)); - assign WriteSATPM = STrapM | (CSRSWriteM && (CSRAdrM == SATP)); - assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN); + assign WriteSSTATUSM = CSRSWriteM && (CSRAdrM == SSTATUS) && ~StallW; + assign WriteSTVECM = CSRSWriteM && (CSRAdrM == STVEC) && ~StallW; + assign WriteSSCRATCHM = CSRSWriteM && (CSRAdrM == SSCRATCH) && ~StallW; + assign WriteSEPCM = STrapM | (CSRSWriteM && (CSRAdrM == SEPC)) && ~StallW; + assign WriteSCAUSEM = STrapM | (CSRSWriteM && (CSRAdrM == SCAUSE)) && ~StallW; + assign WriteSTVALM = STrapM | (CSRSWriteM && (CSRAdrM == STVAL)) && ~StallW; + assign WriteSATPM = STrapM | (CSRSWriteM && (CSRAdrM == SATP)) && ~StallW; + assign WriteSCOUNTERENM = CSRSWriteM && (CSRAdrM == SCOUNTEREN) && ~StallW; // CSRs flopenl #(`XLEN) STVECreg(clk, reset, WriteSTVECM, CSRWriteValM, zero, STVEC_REGW); //busybear: change reset to 0 diff --git a/wally-pipelined/src/privileged/csru.sv b/wally-pipelined/src/privileged/csru.sv index 0fad64bf..ad309594 100644 --- a/wally-pipelined/src/privileged/csru.sv +++ b/wally-pipelined/src/privileged/csru.sv @@ -32,6 +32,7 @@ module csru #(parameter FRM = 12'h002, FCSR = 12'h003) ( input logic clk, reset, + input logic StallW, input logic CSRUWriteM, input logic [11:0] CSRAdrM, input logic [`XLEN-1:0] CSRWriteValM, @@ -50,9 +51,9 @@ module csru #(parameter logic [4:0] NextFFLAGSM; // Write enables - assign WriteFCSRM = CSRUWriteM && (CSRAdrM == FCSR); - assign WriteFFLAGSM = CSRUWriteM && (CSRAdrM == FFLAGS) | WriteFCSRM ; - assign WriteFRMM = CSRUWriteM && (CSRAdrM == FRM) | WriteFCSRM; + assign WriteFCSRM = CSRUWriteM && (CSRAdrM == FCSR) && ~StallW; + assign WriteFFLAGSM = (CSRUWriteM && (CSRAdrM == FFLAGS) | WriteFCSRM) && ~StallW; + assign WriteFRMM = (CSRUWriteM && (CSRAdrM == FRM) | WriteFCSRM) && ~StallW; // Write Values assign NextFRMM = WriteFCSRM ? CSRWriteValM[7:5] : CSRWriteValM[2:0]; @@ -81,4 +82,4 @@ module csru #(parameter assign IllegalCSRUAccessM = 1; end endgenerate -endmodule \ No newline at end of file +endmodule diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index 8a6854e9..f863b7fa 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -48,7 +48,7 @@ module privileged ( output logic [1:0] PrivilegeModeW, output logic [`XLEN-1:0] SATP_REGW, output logic [2:0] FRM_REGW, - input logic FlushD, FlushE, FlushM, StallD, StallW + input logic FlushD, FlushE, FlushM, StallD, StallE, StallM, StallW ); logic [1:0] NextPrivilegeModeM;