From a82aa233993e9f3dc3278681c6068232e5026e99 Mon Sep 17 00:00:00 2001 From: Jarred Allen Date: Tue, 16 Mar 2021 16:57:51 -0400 Subject: [PATCH] Fix icache for jumping into misaligned instructions --- wally-pipelined/src/ifu/icache.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/src/ifu/icache.sv b/wally-pipelined/src/ifu/icache.sv index c5afe784..bef90008 100644 --- a/wally-pipelined/src/ifu/icache.sv +++ b/wally-pipelined/src/ifu/icache.sv @@ -51,7 +51,7 @@ module icache( flopr #(1) flushDLastCycleFlop(clk, reset, FlushD | (FlushDLastCycle & StallF), FlushDLastCycle); flopenr #(1) delayDFlop(clk, reset, ~StallF, DelayF, DelayD); flopenr #(1) delaySideDFlop(clk, reset, ~StallF, DelaySideF, DelaySideD); - flopenr #(1) delayStateFlop(clk, reset, ~StallF, DelayF & ~DelaySideF, DelaySideF); + flopenrc#(1) delayStateFlop(clk, reset, FlushD, ~StallF, DelayF & ~DelaySideF, DelaySideF); flopenr #(16) halfInstrFlop(clk, reset, DelayF & ~StallF, MisalignedHalfInstrF, MisalignedHalfInstrD); // This flop is here to simulate pulling data out of the cache, which is edge-triggered