diff --git a/wally-pipelined/src/fpu/fsm.sv b/wally-pipelined/src/fpu/fsm.sv
index 00f95993..46b1c59a 100755
--- a/wally-pipelined/src/fpu/fsm.sv
+++ b/wally-pipelined/src/fpu/fsm.sv
@@ -41,8 +41,21 @@ module fsm (
 	  CURRENT_STATE=NEXT_STATE;
      end
 
-   always @(*)
+   always_comb
      begin
+       done = 1'b0;
+       divBusy = 1'b0;
+       load_rega = 1'b0;
+       load_regb = 1'b0;
+       load_regc = 1'b0;
+       load_regd = 1'b0;
+       load_regr = 1'b0;
+       load_regs = 1'b0;
+       sel_muxa = 3'b000;
+       sel_muxb = 3'b000;
+       sel_muxr = 1'b0;
+       NEXT_STATE = S0;
+       
  	case(CURRENT_STATE)
 	  S0:  // iteration 0
 	    begin
diff --git a/wally-pipelined/src/generic/clockgater.sv b/wally-pipelined/src/generic/clockgater.sv
index f54e1e3d..ec0990ee 100644
--- a/wally-pipelined/src/generic/clockgater.sv
+++ b/wally-pipelined/src/generic/clockgater.sv
@@ -28,7 +28,7 @@
 module clockgater
   (input logic 	E,
    input logic 	SE,
-   input logic 	CLK,
+   (* gated_clock = "yes" *) input logic 	CLK,
    output logic ECLK);
 
   // VERY IMPORTANT.
@@ -37,6 +37,7 @@ module clockgater
 
   logic 	enable_q;
   
+/* -----\/----- EXCLUDED -----\/-----
 
   always_latch begin
     if(~CLK) begin
@@ -44,5 +45,18 @@ module clockgater
     end
   end
   assign ECLK = enable_q & CLK;
+ -----/\----- EXCLUDED -----/\----- */
+  assign ECLK = CLK;
+  
+
+/* -----\/----- EXCLUDED -----\/-----
+  if (`XILINX) begin
+    BUFGCE bufgce_i0 (   
+   .I(CLK),
+   .CE(E | SE),
+   .O(ECLK)    
+   );
+  end
+ -----/\----- EXCLUDED -----/\----- */
 
 endmodule
diff --git a/wally-pipelined/src/uncore/dtim.sv b/wally-pipelined/src/uncore/dtim.sv
index c195c551..f0e123be 100644
--- a/wally-pipelined/src/uncore/dtim.sv
+++ b/wally-pipelined/src/uncore/dtim.sv
@@ -25,7 +25,7 @@
 
 `include "wally-config.vh"
 
-module dtim #(parameter BASE=0, RANGE = 65535) (
+module dtim #(parameter BASE=0, RANGE = 65535, string PRELOAD="") (
   input  logic             HCLK, HRESETn, 
   input  logic             HSELTim,
   input  logic [31:0]      HADDR,
@@ -51,6 +51,35 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
   logic        memread, memwrite;
   logic [3:0]  busycount;
 
+  initial begin
+    //$readmemh(PRELOAD, RAM);
+    RAM[0] = 64'h8c61819300002197;
+    RAM[1] = 64'h4281420141014081;
+    RAM[2] = 64'h4481440143814301;
+    RAM[3] = 64'h4681460145814501;
+    RAM[4] = 64'h4881480147814701;
+    RAM[5] = 64'h4a814a0149814901;
+    RAM[6] = 64'h4c814c014b814b01;
+    RAM[7] = 64'h4e814e014d814d01;
+    RAM[8] = 64'h0ff001134f814f01;
+    RAM[9] = 64'h00818213100121b7;
+    RAM[10] = 64'h0022a02300c18293;
+    RAM[11] = 64'h6bc14a8100222023;
+    RAM[12] = 64'h4c010b7e00100b1b;
+    RAM[13] = 64'h018ca023018b0cb3;
+    RAM[14] = 64'h4c01ff7c4be30c11;
+    RAM[15] = 64'h000caa83018b0cb3;
+    RAM[16] = 64'h49e30c11038a9063;
+    RAM[17] = 64'h0a1b014fba37ff7c;
+    RAM[18] = 64'hfe0a5fe31a7d180a;
+    RAM[19] = 64'hb7f50022a0230105;
+    RAM[20] = 64'h8e0a0a1b0010da37;
+    RAM[21] = 64'ha023fe0a5fe31a7d;
+    RAM[22] = 64'h0a1b0010da370002;
+    RAM[23] = 64'hfe0a5fe31a7d8e0a;
+    RAM[24] = 64'h0000bff10022a023;
+
+  end
 
   assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);
 
@@ -114,6 +143,9 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
   endgenerate
   /* verilator lint_on WIDTH */
 
-  assign HREADTim = HREADYTim ? HREADTim0 : `XLEN'bz;
+  //assign HREADTim = HREADYTim ? HREADTim0 : `XLEN'bz;
+  // *** Ross Thompson: removed tristate as fpga synthesis removes.
+  assign HREADTim = HREADTim0;
+  
 endmodule
 
diff --git a/wally-pipelined/src/uncore/uncore.sv b/wally-pipelined/src/uncore/uncore.sv
index e6f5d15c..3df8ee1c 100644
--- a/wally-pipelined/src/uncore/uncore.sv
+++ b/wally-pipelined/src/uncore/uncore.sv
@@ -91,7 +91,8 @@ module uncore (
     // tightly integrated memory
     //dtim #(.BASE(`TIM_BASE), .RANGE(`TIM_RANGE)) dtim (.*);
     if (`BOOTTIM_SUPPORTED) begin : bootdtim
-      dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE)) bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
+      dtim #(.BASE(`BOOTTIM_BASE), .RANGE(`BOOTTIM_RANGE), .PRELOAD("blink-led.mem"))
+      bootdtim(.HSELTim(HSELBootTim), .HREADTim(HREADBootTim), .HRESPTim(HRESPBootTim), .HREADYTim(HREADYBootTim), .*);
     end
 
     // memory-mapped I/O peripherals
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 0b1457b9..f7968f2d 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -277,4 +277,15 @@ module wallypipelinedhart
   //assign SetFflagsM = 0;
   //assign FRegWriteM = 0;
   
+  
+  // ILA probe most important signals in CPU.
+  ila_0 ila_0(.clk(clk),
+              .probe0(PCM),
+              .probe1(MemAdrM),
+              .probe2(WriteDataM),
+              .probe3(ReadDataM),
+              .probe4(TrapM),
+              .probe5(MemRWM),
+	      .probe6(InstrM));
+
 endmodule