From a7ae593a680aeb69c20b29ef5690055db3c66ae0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 18 Oct 2022 15:04:21 -0500 Subject: [PATCH] Possible fix for interrupt during a floating point divide. --- pipelined/src/hazard/hazard.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index b9a6d957..550688b4 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -69,7 +69,7 @@ module hazard( assign StallECause = (DivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?) // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap // assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE; - assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)) | FDivBusyE; + assign StallMCause = ((wfiM | FDivBusyE) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE? assign StallWCause = LSUStallM | IFUStallF; assign #1 StallF = StallFCause | StallD;