From a51257abca58ea5bc43d66e9ebefcb17a9dd8ea2 Mon Sep 17 00:00:00 2001
From: Jarred Allen <jaallen@g.hmc.edu>
Date: Wed, 24 Mar 2021 00:58:56 -0400
Subject: [PATCH] Fix compile errors from const not actually being constant
 (why does Verilog do this)

---
 wally-pipelined/src/cache/dmapped.sv | 12 ++++++------
 wally-pipelined/src/cache/line.sv    | 18 +++++++++++++-----
 2 files changed, 19 insertions(+), 11 deletions(-)

diff --git a/wally-pipelined/src/cache/dmapped.sv b/wally-pipelined/src/cache/dmapped.sv
index b57f2401..52027b39 100644
--- a/wally-pipelined/src/cache/dmapped.sv
+++ b/wally-pipelined/src/cache/dmapped.sv
@@ -43,13 +43,13 @@ module rodirectmapped #(parameter LINESIZE = 256, parameter NUMLINES = 512, para
     output logic                DataValid
 );
 
-    integer TAGWIDTH    = `XLEN-$clog2(NUMLINES)-$clog2(LINESIZE);
-    integer SETWIDTH    = $clog2(NUMLINES);
-    integer OFFSETWIDTH = $clog2(LINESIZE/8);
+    localparam integer SETWIDTH    = $clog2(NUMLINES);
+    localparam integer OFFSETWIDTH = $clog2(LINESIZE/8);
+    localparam integer TAGWIDTH    = `XLEN-SETWIDTH-OFFSETWIDTH;
 
     logic [NUMLINES-1:0][WORDSIZE-1:0]  LineOutputs;
     logic [NUMLINES-1:0]                ValidOutputs;
-    logic [NUMLINES-1:0][TAGSIZE-1:0]   TagOutputs;
+    logic [NUMLINES-1:0][TAGWIDTH-1:0]  TagOutputs;
     logic [OFFSETWIDTH-1:0]             WordSelect;
     logic [`XLEN-1:0]                   ReadPAdr;
     logic [SETWIDTH-1:0]                ReadSet, WriteSet;
@@ -70,14 +70,14 @@ module rodirectmapped #(parameter LINESIZE = 256, parameter NUMLINES = 512, para
     genvar i;
     generate
         for (i=0; i < NUMLINES; i++) begin
-            rocacheline #(LINESIZE, TAGSIZE, WORDSIZE) lines[NUMLINES](
+            rocacheline #(LINESIZE, TAGWIDTH, WORDSIZE) lines (
                 .*,
                 .WriteEnable(WriteEnable & (WriteSet == i)),
                 .WriteData(WriteLine),
                 .WriteTag(WriteTag),
                 .DataWord(LineOutputs[i]),
                 .DataTag(TagOutputs[i]),
-                .DataValid(ValidOutputs[i]),
+                .DataValid(ValidOutputs[i])
             );
         end
     endgenerate
diff --git a/wally-pipelined/src/cache/line.sv b/wally-pipelined/src/cache/line.sv
index 85d4073b..e498d073 100644
--- a/wally-pipelined/src/cache/line.sv
+++ b/wally-pipelined/src/cache/line.sv
@@ -44,17 +44,25 @@ module rocacheline #(parameter LINESIZE = 256, parameter TAGSIZE = 32, parameter
     output logic                            DataValid
 );
 
-    logic [LINESIZE-1:0] DataLine;
-    logic [$clog2(LINESIZE/8)-1:0] AlignedWordSelect;
+    localparam integer OFFSETSIZE = $clog2(LINESIZE/8);
+    localparam integer NUMWORDS = LINESIZE/WORDSIZE;
+
+    logic [NUMWORDS-1:0][WORDSIZE-1:0]  DataLinesIn, DataLinesOut;
 
     flopenr #(1)        ValidBitFlop(clk, reset, WriteEnable | flush, ~flush, DataValid);
     flopenr #(TAGSIZE)  TagFlop(clk, reset, WriteEnable, WriteTag, DataTag);
-    flopenr #(LINESIZE) LineFlop(clk, reset, WriteEnable, WriteData, DataLine);
+
+    genvar i;
+    generate
+        for (i=0; i < NUMWORDS; i++) begin
+            assign DataLinesIn[i] = WriteData[NUMWORDS*i+WORDSIZE-1:NUMWORDS*i];
+            flopenr #(LINESIZE) LineFlop(clk, reset, WriteEnable, DataLinesIn[i], DataLinesOut[i]);
+        end
+    endgenerate
 
 
     always_comb begin
-        assign AlignedWordSelect = {WordSelect[$clog2(LINESIZE/8)-1:$clog2(WORDSIZE)], {$clog2(WORDSIZE){'b0}}};
-        assign DataWord = DataLine[WORDSIZE+AlignedWordSelect-1:AlignedWordSelect];
+        assign DataWord = DataLinesOut[WordSelect[OFFSETSIZE-1:$clog2(WORDSIZE)]];
     end
 
 endmodule