From 8bf93298152a7cd4aa9bfcb7b420275ad1c3714c Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 24 Apr 2023 12:19:56 -0700 Subject: [PATCH 1/8] Added M suffix in atomic --- src/lsu/amoalu.sv | 8 ++++---- src/lsu/atomic.sv | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/lsu/amoalu.sv b/src/lsu/amoalu.sv index eda3576b..d2670449 100644 --- a/src/lsu/amoalu.sv +++ b/src/lsu/amoalu.sv @@ -34,7 +34,7 @@ module amoalu ( input logic [`XLEN-1:0] IHWriteDataM, // LSU's WriteData input logic [6:0] LSUFunct7M, // ALU Operation input logic [2:0] LSUFunct3M, // Memoy access width - output logic [`XLEN-1:0] AMOResult // ALU output + output logic [`XLEN-1:0] AMOResultM // ALU output ); logic [`XLEN-1:0] a, b, y; @@ -60,17 +60,17 @@ module amoalu ( if (`XLEN == 32) begin:sext assign a = ReadDataM; assign b = IHWriteDataM; - assign AMOResult = y; + assign AMOResultM = y; end else begin:sext // `XLEN = 64 always_comb if (LSUFunct3M[1:0] == 2'b10) begin // sign-extend word-length operations a = {{32{ReadDataM[31]}}, ReadDataM[31:0]}; b = {{32{IHWriteDataM[31]}}, IHWriteDataM[31:0]}; - AMOResult = {{32{y[31]}}, y[31:0]}; + AMOResultM = {{32{y[31]}}, y[31:0]}; end else begin a = ReadDataM; b = IHWriteDataM; - AMOResult = y; + AMOResultM = y; end end endmodule diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index fc9ede11..d33e85fe 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -38,7 +38,7 @@ module atomic ( input logic [`PA_BITS-1:0] PAdrM, // Physical memory address input logic [6:0] LSUFunct7M, // AMO alu operation gated by HPTW input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size - input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResult as the writedata output, 01: LR/SC operation + input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation output logic [`XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data @@ -46,12 +46,12 @@ module atomic ( output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC ); - logic [`XLEN-1:0] AMOResult; + logic [`XLEN-1:0] AMOResultM; logic MemReadM; - amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResult); + amoalu amoalu(.ReadDataM, .IHWriteDataM, .LSUFunct7M, .LSUFunct3M, .AMOResultM); - mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResult, LSUAtomicM[1], IMAWriteDataM); + mux2 #(`XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM); assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); From 03448aa69185c8ae0a8db9b551b0611266f3f015 Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 24 Apr 2023 12:20:33 -0700 Subject: [PATCH 2/8] Commented about Sstvecd trap vector alignment --- src/privileged/csr.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index db142de5..9f3ae89b 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -158,7 +158,7 @@ module csr #(parameter assign TVecPlusCauseM = {TVecAlignedM[`XLEN-1:6], CauseM, 2'b00}; // 64-byte alignment allows concatenation rather than addition mux2 #(`XLEN) trapvecmux(TVecAlignedM, TVecPlusCauseM, VectoredM, TrapVectorM); end else - assign TrapVectorM = TVecAlignedM; + assign TrapVectorM = TVecAlignedM; // unvectored interrupt handler can be at any word-aligned address. This is called Sstvecd // Trap Returns // A trap sets the PC to TrapVector From e519eaa33fd9df8210a80d346fd0e3d167683537 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 27 Apr 2023 14:10:46 -0700 Subject: [PATCH 3/8] Renamed byteUnit to byteop --- src/ieu/bmu/{byte.sv => byteop.sv} | 4 ++-- src/ieu/bmu/zbb.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) rename src/ieu/bmu/{byte.sv => byteop.sv} (96%) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byteop.sv similarity index 96% rename from src/ieu/bmu/byte.sv rename to src/ieu/bmu/byteop.sv index 32031059..e6099533 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byteop.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// byte.sv +// byteop.sv // // Written: Kevin Kim // Created: 1 February 2023 @@ -29,7 +29,7 @@ `include "wally-config.vh" -module byteUnit #(parameter WIDTH=32) ( +module byteop #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, // Operands input logic ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1a1b9de2..3d7bcedd 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -47,7 +47,7 @@ module zbb #(parameter WIDTH=32) ( mux2 #(1) ltmux(LT, LTU, BUnsigned , lt); cnt #(WIDTH) cnt(.A, .RevA, .B(B[1:0]), .W64, .CntResult); - byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); + byteop #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); // ZBBSelect[2] differentiates between min(u) vs max(u) instruction From e962e95e53528745f6b53ee64cb5530573ea2949 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 27 Apr 2023 14:12:57 -0700 Subject: [PATCH 4/8] CSR code cleanup --- src/privileged/csrsr.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 61a6f324..831366bb 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -177,8 +177,7 @@ module csrsr ( STATUS_MIE <= #1 STATUS_MPIE; // restore global interrupt enable STATUS_MPIE <= #1 1; // STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // set MPP to lowest supported privilege level - // STATUS_MPRV_INT <= #1 0; // changed to this by Ross to solve Linux bug; might have been s spurious disagreement with QEMU - STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // Seems to be given by page 21 of spec. + STATUS_MPRV_INT <= #1 STATUS_MPRV_INT & (STATUS_MPP == `M_MODE); // page 21 of privileged spec. end else if (sretM) begin STATUS_SIE <= #1 STATUS_SPIE; // restore global interrupt enable STATUS_SPIE <= #1 `S_SUPPORTED; From a556ea54e3c44b0cd7b23e9343217dd59bbf2e51 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 28 Apr 2023 06:20:12 -0700 Subject: [PATCH 5/8] Ignore IF_vectors --- .gitignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.gitignore b/.gitignore index 630731b2..a675f900 100644 --- a/.gitignore +++ b/.gitignore @@ -114,4 +114,5 @@ sim/vsim.log tests/coverage/*.elf *.elf.memfile sim/*Cache.log -sim/branch \ No newline at end of file +sim/branch +tests/fp/combined_IF_vectors/IF_vectors/*.tv From f6f43e826a60728130a712f9157765a8da86f6ab Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 28 Apr 2023 07:03:46 -0700 Subject: [PATCH 6/8] Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues --- src/mmu/tlb/tlblru.sv | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mmu/tlb/tlblru.sv b/src/mmu/tlb/tlblru.sv index 6cdb475e..4cabb33a 100644 --- a/src/mmu/tlb/tlblru.sv +++ b/src/mmu/tlb/tlblru.sv @@ -50,7 +50,5 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( assign RUBitsAccessed = AccessLines | RUBits; assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed; - - // enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21 - flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits); + flopenr #(TLB_ENTRIES) lrustate(clk, reset, (CAMHit | TLBWrite), RUBitsNext, RUBits); endmodule From 22e4f82a9983a17e435deafd11deee5382330ee9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 28 Apr 2023 07:52:08 -0700 Subject: [PATCH 7/8] Commenting --- src/mmu/hptw.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index f90e42ce..2cc76e8f 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -175,7 +175,7 @@ module hptw ( .SV39Mode(), .UpperBitsUnequal); assign InvalidRead = ReadAccess & ~Readable & (~STATUS_MXR | ~Executable); assign InvalidWrite = WriteAccess & ~Writable; - assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable; + assign InvalidOp = DTLBWalk ? (InvalidRead | InvalidWrite) : ~Executable; assign OtherPageFault = ImproperPrivilege | InvalidOp | UpperBitsUnequal | Misaligned | ~Valid; // hptw needs to know if there is a Dirty or Access fault occuring on this From ca5a71bbe55c74b69a3ae350f7a99148e341093c Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 28 Apr 2023 07:53:59 -0700 Subject: [PATCH 8/8] PMA Checker coverage --- sim/coverage-exclusions-rv64gc.do | 47 +++++++++++++++++-------------- src/mmu/pmachecker.sv | 8 +++--- 2 files changed, 30 insertions(+), 25 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index d1aa0ade..4d3b47c1 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -97,6 +97,9 @@ for {set i 0} {$i < $numcacheways} {incr i} { # D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY +#################### +# Unused / illegal peripheral accesses +#################### # Excluding peripherals as sources of instructions for the ifu coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/clintdec @@ -104,53 +107,61 @@ coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/gpiodec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uartdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/plicdec +# PMA Regions 8, 9, and 10 (dtim, irom, ddr4) are never used in the rv64gc configuration, so exclude coverage +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-cachable"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-idempotent"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4,6,8 +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-atomic"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +set line [GetLineNum ../src/mmu/pmachecker.sv "exclusion-tag: unused-tim"] +coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 +coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2,4 + # Excluding so far un-used instruction sources for the ifu coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/bootromdec coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker/adrdecs/uncoreramdec - #Excluding the bootrom, uncoreran, and clint as sources for the lsu coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/bootromdec - #Excluding signals in lsu: clintdec and uncoreram accept all sizes so 'SizeValid' will never be 0 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -linerange $line-$line -item e 1 -fecexprrow 5 set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5 -## Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccessF' will never be 1 -# in pmachecker.sv +#################### +# Unused access types due to sharing IFU and LSU logic +#################### + +## The lsu never executes instructions so 'ExecuteAccessF' will never be 1 set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4 set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 - -# in mmu.sv set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2 set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF \\|"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 - -# in pmpchecker.sv set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"] coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 -## Excluding ReadAccessM_1 and WriteAccessM_1 signals in the ifu pmachecker, mmu, pmpchecker because they will never be high -## and Excluding ExecuteAccessF_0 because it is always true/high in the ifu -# in pmachecker.sv +## The IFU has ReadAccess = WriteAccess = 0 and ExecuteAccess = 1 hardwired, so exclude alternatives set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4 set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3 - set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1 set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"] @@ -159,8 +170,6 @@ set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM & PMAAccessFault"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4 set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX \\| AtomicAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3 - -# in mmu.sv set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4 set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"] @@ -175,21 +184,14 @@ set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4 - -# in pmpchecker.sv set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"] coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6 - -## Executing any LoadAccess or StoreAccess signal in the ifu - depend on Read and Write Access that the ifu will never have -# in /mmu/mmu.sv set line [GetLineNum ../src/mmu/mmu.sv "PMALoadAccessFaultM \\| PMPLoadAccessFaultM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 set line [GetLineNum ../src/mmu/mmu.sv "PMAStoreAmoAccessFaultM \\| PMPStoreAmoAccessFaultM"] coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6 - -## Excluding ReadAccess_0, WriteAcess_1 in the TLB because the itlb only reads, and does not write set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"] coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4 set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"] @@ -201,3 +203,6 @@ coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $l set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"] coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2 +# TLB not recently used never has all RU bits = 1 because it will then clear all to 0 +# This is a blunt instrument; perhaps there is a more graceful exclusion +coverage exclude -srcfile priorityonehot.sv diff --git a/src/mmu/pmachecker.sv b/src/mmu/pmachecker.sv index 909cc564..ace481f7 100644 --- a/src/mmu/pmachecker.sv +++ b/src/mmu/pmachecker.sv @@ -57,14 +57,14 @@ module pmachecker ( adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions); // Only non-core RAM/ROM memory regions are cacheable - assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6]; + assign Cacheable = SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-cachable // Nonidemdempotent means access could have side effect and must not be done speculatively or redundantly // I/O is nonidempotent. - assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6]; + assign Idempotent = SelRegions[10] | SelRegions[9] | SelRegions[8] | SelRegions[7] | SelRegions[6]; // exclusion-tag: unused-idempotent // Atomic operations are only allowed on RAM - assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6]; + assign AtomicAllowed = SelRegions[10] | SelRegions[8] | SelRegions[6]; // exclusion-tag: unused-atomic // Check if tightly integrated memories are selected - assign SelTIM = SelRegions[10] | SelRegions[9]; + assign SelTIM = SelRegions[10] | SelRegions[9]; // exclusion-tag: unused-tim // Detect access faults assign PMAAccessFault = (SelRegions[0]) & AccessRWX | AtomicAccessM & ~AtomicAllowed;