From 54938c7abff7e1d99f3f145df6c71b5476f09655 Mon Sep 17 00:00:00 2001 From: cturek Date: Mon, 27 Jun 2022 21:44:06 +0000 Subject: [PATCH 1/2] Added int tests --- pipelined/srt/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile index 49b21be7..f2ed6f8c 100644 --- a/pipelined/srt/Makefile +++ b/pipelined/srt/Makefile @@ -23,5 +23,10 @@ qslc_sqrt_r4a2: qslc_sqrt_r4a2.c gcc qslc_sqrt_r4a2.c -o qslc_sqrt_r4a2 -lm ./qslc_sqrt_r4a2 > qslc_sqrt_r4a2.sv +inttestgen: inttestgen.c + gcc -lm -o inttestgen inttestgen.c + ./inttestgen + clean: rm -f testgen exptestgen qslc_r4a2 qslc_r4a2b qslc_sqrt_r4a2 + From 3a40c68549a38c091bedde6472655bf78edb19c0 Mon Sep 17 00:00:00 2001 From: cturek Date: Mon, 27 Jun 2022 23:55:21 +0000 Subject: [PATCH 2/2] Updated radix 2 divider to work with integers and floats in new structure. Integers still might not work. --- addins/riscv-arch-test | 2 +- pipelined/config/shared/wally-shared.vh | 6 +++--- pipelined/srt/exptestgen.c | 2 +- pipelined/srt/srt.sv | 19 +++++++++---------- pipelined/srt/testbench.sv | 12 ++++++------ 5 files changed, 20 insertions(+), 21 deletions(-) diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test index be67c99b..307c77b2 160000 --- a/addins/riscv-arch-test +++ b/addins/riscv-arch-test @@ -1 +1 @@ -Subproject commit be67c99bd461742aa1c100bcc0732657faae2230 +Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86 diff --git a/pipelined/config/shared/wally-shared.vh b/pipelined/config/shared/wally-shared.vh index 51c45ef0..5db8af1c 100644 --- a/pipelined/config/shared/wally-shared.vh +++ b/pipelined/config/shared/wally-shared.vh @@ -94,9 +94,9 @@ `define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS) // largest length in IEU/FPU -`define CVTLEN ((`NF<`XLEN) ? `XLEN : `NF) -`define DIVLEN ((`NF < `XLEN) ? `XLEN : `NF) -`define LLEN ((`FLEN<`XLEN) ? `XLEN : `FLEN) +`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF)) +`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF)) +`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN)) `define LOGCVTLEN $unsigned($clog2(`CVTLEN+1)) `define NORMSHIFTSZ ((`DIVLEN+`NF+3) > (3*`NF+8) ? (`DIVLEN+`NF+3) : (3*`NF+9)) `define CORRSHIFTSZ ((`DIVLEN+`NF+3) > (3*`NF+8) ? (`DIVLEN+`NF+3) : (3*`NF+6)) diff --git a/pipelined/srt/exptestgen.c b/pipelined/srt/exptestgen.c index bd51126e..61fe74aa 100644 --- a/pipelined/srt/exptestgen.c +++ b/pipelined/srt/exptestgen.c @@ -46,7 +46,7 @@ void main(void) int i, j; int bias = 1023; - if ((fptr = fopen("testvectors","w")) == NULL) { + if ((fptr = fopen("testvectors","w")) == NULL) { fprintf(stderr, "Couldn't write testvectors file\n"); exit(1); } diff --git a/pipelined/srt/srt.sv b/pipelined/srt/srt.sv index e40f2758..5adeced4 100644 --- a/pipelined/srt/srt.sv +++ b/pipelined/srt/srt.sv @@ -2,7 +2,7 @@ // srt.sv // // Written: David_Harris@hmc.edu 13 January 2022 -// Modified: +// Modified: cturek@hmc.edu June 2022 // // Purpose: Combined Divide and Square Root Floating Point and Integer Unit // @@ -29,10 +29,8 @@ //////////////////////////////////////////////////////////////////////////////////////////////// `include "wally-config.vh" - -`define DIVLEN ((`NF<(`XLEN+1)) ? (`XLEN + 1) : `NF) -`define EXTRAFRACBITS ((`NF<(`XLEN+1)) ? (`XLEN - `NF + 1) : 0) -`define EXTRAINTBITS ((`NF<(`XLEN+1)) ? 0 : (`NF - `XLEN)) +`define EXTRAFRACBITS ((`NF<(`XLEN)) ? (`XLEN - `NF) : 0) +`define EXTRAINTBITS ((`NF<(`XLEN)) ? 0 : (`NF - `XLEN)) module srt ( input logic clk, @@ -131,11 +129,11 @@ module srtpreproc ( lzc #(`XLEN) lzcA (PosA, zeroCntA); lzc #(`XLEN) lzcB (PosB, zeroCntB); - assign ExtraA = {1'b0, PosA, {`EXTRAINTBITS{1'b0}}}; - assign ExtraB = {1'b0, PosB, {`EXTRAINTBITS{1'b0}}}; + assign ExtraA = {PosA, {`EXTRAINTBITS{1'b0}}}; + assign ExtraB = {PosB, {`EXTRAINTBITS{1'b0}}}; assign PreprocA = ExtraA << zeroCntA; - assign PreprocB = ExtraB << (zeroCntB + 1); + assign PreprocB = ExtraB << zeroCntB; assign PreprocX = {SrcXFrac, {`EXTRAFRACBITS{1'b0}}}; assign PreprocY = {SrcYFrac, {`EXTRAFRACBITS{1'b0}}}; @@ -228,14 +226,15 @@ module otfc2 #(parameter N=65) ( // // QM is Q-1. It allows us to write negative bits // without using a costly CPA. - logic [N+2:0] Q, QM, QNext, QMNext; + logic [N+2:0] Q, QM, QNext, QMNext, QMMux; // QR and QMR are the shifted versions of Q and QM. // They are treated as [N-1:r] size signals, and // discard the r most significant bits of Q and QM. logic [N+1:0] QR, QMR; flopr #(N+3) Qreg(clk, Start, QNext, Q); - flopr #(N+3) QMreg(clk, Start, QMNext, QM); + mux2 #(`DIVLEN+3) QMmux(QMNext, {`DIVLEN+3{1'b1}}, Start, QMMux); + flop #(`DIVLEN+3) QMreg(clk, QMMux, QM); always_comb begin QR = Q[N+1:0]; diff --git a/pipelined/srt/testbench.sv b/pipelined/srt/testbench.sv index 93da7475..9655d7f7 100644 --- a/pipelined/srt/testbench.sv +++ b/pipelined/srt/testbench.sv @@ -1,4 +1,4 @@ -`define DIVLEN 65 +`define DIVLEN 64 ///////////// // counter // @@ -17,7 +17,7 @@ module counter(input logic clk, always @(posedge clk) begin - if (count == `DIVLEN+1) done <= #1 1; + if (count == `DIVLEN + 2) done <= #1 1; else if (done | req) done <= #1 0; if (req) count <= #1 0; else count <= #1 count+1; @@ -101,8 +101,8 @@ module testbench; b = Vec[`memb]; {bsign, bExp, bfrac} = b; nextr = Vec[`memr]; - r = Quot[`DIVLEN:`DIVLEN - 52]; - rOTFC = QuotOTFC[`DIVLEN:`DIVLEN - 52]; + r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)]; + rOTFC = QuotOTFC[(`DIVLEN - 1):(`DIVLEN - 52)]; req <= #5 1; end @@ -110,8 +110,8 @@ module testbench; always @(posedge clk) begin - r = Quot[`DIVLEN:`DIVLEN - 52]; - rOTFC = QuotOTFC[`DIVLEN:`DIVLEN - 52]; + r = Quot[(`DIVLEN - 1):(`DIVLEN - 52)]; + rOTFC = QuotOTFC[(`DIVLEN - 1):(`DIVLEN - 52)]; if (done) begin req <= #5 1;