From a26bf37be8747c4934b07ea094f58dfa59566dba Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 4 Jun 2021 11:59:14 -0400 Subject: [PATCH] Started MMU --- .../config/buildroot/wally-config.vh | 3 + .../config/busybear/wally-config.vh | 3 + .../config/coremark/wally-config.vh | 4 + .../config/coremark_bare/wally-config.vh | 3 + wally-pipelined/config/rv32ic/wally-config.vh | 3 + wally-pipelined/config/rv64BP/wally-config.vh | 3 + wally-pipelined/config/rv64ic/wally-config.vh | 3 + .../config/rv64icfd/wally-config.vh | 3 + .../config/rv64imc/wally-config.vh | 8 +- .../config/shared/wally-constants.vh | 18 +--- wally-pipelined/src/ifu/ifu.sv | 25 ++++- wally-pipelined/src/mmu/mmu.sv | 96 +++++++++++++++++++ .../src/{privileged => mmu}/pmachecker.sv | 2 +- .../src/{privileged => mmu}/pmpadrdec.sv | 0 .../src/{privileged => mmu}/pmpchecker.sv | 0 wally-pipelined/src/privileged/privileged.sv | 17 +--- 16 files changed, 151 insertions(+), 40 deletions(-) create mode 100644 wally-pipelined/src/mmu/mmu.sv rename wally-pipelined/src/{privileged => mmu}/pmachecker.sv (97%) rename wally-pipelined/src/{privileged => mmu}/pmpadrdec.sv (100%) rename wally-pipelined/src/{privileged => mmu}/pmpchecker.sv (100%) diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 57740b68..7e8a01c4 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -60,6 +60,9 @@ `define MEM_VIRTMEM 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 + // Address space `define RESET_VECTOR 64'h0000000000001000 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index a840676d..0d3cc4f0 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -60,6 +60,9 @@ `define MEM_VIRTMEM 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 + // Address space `define RESET_VECTOR 64'h0000000000001000 diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index 47e9c731..0e89b3d0 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -58,6 +58,10 @@ `define MEM_DTIM 1 `define MEM_ICACHE 0 `define MEM_VIRTMEM 0 +`define VECTORED_INTERRUPTS_SUPPORTED 1 + +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 // Address space `define RESET_VECTOR 64'h00000000000100b0 diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index b42dd678..800cdead 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -60,6 +60,9 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 + // Address space `define RESET_VECTOR 64'h0000000080000000 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index 17daa572..170b4a8c 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -59,6 +59,9 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 + // Address space `define RESET_VECTOR 32'h80000000 diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index f85e0c22..688ea865 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -61,6 +61,9 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 + // Address space `define RESET_VECTOR 64'h0000000000000000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index 12d254ba..dad3948f 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -60,6 +60,9 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 + // Address space `define RESET_VECTOR 64'h0000000080000000 diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index 4b0ce324..f5607a8c 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -60,6 +60,9 @@ `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 + // Address space `define RESET_VECTOR 64'h0000000080000000 diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh index 8c42cd81..e226b9ff 100644 --- a/wally-pipelined/config/rv64imc/wally-config.vh +++ b/wally-pipelined/config/rv64imc/wally-config.vh @@ -46,10 +46,6 @@ //`define N_SUPPORTED ((MISA >> 13) % 2 == 1) `define N_SUPPORTED 0 -`define M_MODE (2'b11) -`define S_MODE (2'b01) -`define U_MODE (2'b00) - // Microarchitectural Features `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 @@ -58,6 +54,10 @@ `define MEM_DTIM 1 `define MEM_ICACHE 0 `define MEM_VIRTMEM 0 +`define VECTORED_INTERRUPTS_SUPPORTED 1 + +`define ITLB_ENTRY_BITS 5 +`define DTLB_ENTRY_BITS 5 // Address space `define RESET_VECTOR 64'h0000000080000000 diff --git a/wally-pipelined/config/shared/wally-constants.vh b/wally-pipelined/config/shared/wally-constants.vh index ec225f8c..be0f7688 100644 --- a/wally-pipelined/config/shared/wally-constants.vh +++ b/wally-pipelined/config/shared/wally-constants.vh @@ -30,23 +30,6 @@ `include "wally-config.vh" -/* -// Virtual Memory Constants (sv48) -`define VPN_SEGMENT_BITS_RV64 9 -`define VPN_BITS_RV64 36 -`define PPN_HIGH_SEGMENT_BITS_RV64 17 -`define PPN_BITS_RV64 44 -`define PA_BITS_RV64 56 -`define SVMODE_BITS_RV64 4 -// Virtual Memory Constants (sv32) -`define VPN_SEGMENT_BITS_RV32 10 -`define VPN_BITS_RV32 20 -`define PPN_HIGH_SEGMENT_BITS_RV32 12 -`define PPN_BITS_RV32 22 -`define PA_BITS_RV32 34 -`define SVMODE_BITS_RV32 1 -*/ - // Virtual Memory Constants `define VPN_SEGMENT_BITS (`XLEN == 32 ? 10 : 9) `define VPN_BITS (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS)) @@ -61,3 +44,4 @@ `define SV32 1 `define SV39 8 `define SV48 9 + diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv index e0507b63..2aa30fc5 100644 --- a/wally-pipelined/src/ifu/ifu.sv +++ b/wally-pipelined/src/ifu/ifu.sv @@ -70,7 +70,17 @@ module ifu ( input logic [`XLEN-1:0] SATP_REGW, input logic STATUS_MXR, STATUS_SUM, input logic ITLBWriteF, ITLBFlushF, - output logic ITLBMissF, ITLBHitF + output logic ITLBMissF, ITLBHitF, + + // MMU signals. *** temporarily from AHB bus but eventually replace with internal versions pre H + input logic [31:0] HADDR, + input logic [2:0] HSIZE, HBURST, + input logic HWRITE, + input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, + output logic ICacheableF, IIdempotentF, IAtomicAllowedF, + output logic ISquashBusAccessF, + output logic [5:0] IHSELRegionsF + ); logic [`XLEN-1:0] UnalignedPCNextF, PCNextF; @@ -86,13 +96,24 @@ module ifu ( logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; - tlb #(.ENTRY_BITS(3), .ITLB(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), +/* tlb #(.ENTRY_BITS(3), .ITLB(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF), .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), + .*); */ + mmu #(.ENTRY_BITS(`ITLB_ENTRY_BITS), .IMMU(1)) itlb(.TLBAccessType(2'b10), .VirtualAddress(PCF), + .PageTableEntryWrite(PageTableEntryF), .PageTypeWrite(PageTypeF), + .TLBWrite(ITLBWriteF), .TLBFlush(ITLBFlushF), + .PhysicalAddress(PCPF), .TLBMiss(ITLBMissF), + .TLBHit(ITLBHitF), .TLBPageFault(ITLBInstrPageFaultF), + + .AtomicAccessM(1'b0), .WriteAccessM(1'b0), .ReadAccessM(1'b0), + .Cacheable(ICacheableF), .Idempotent(IIdempotentF), .AtomicAllowed(IAtomicAllowedF), + .SquashBusAccess(.ISquashBusAccssF), .HSELRegionsF(.IHSELRegionsF)), .*); + // branch predictor signals logic SelBPPredF; logic [`XLEN-1:0] BPPredPCF, PCCorrectE, PCNext0F, PCNext1F, PCNext2F, PCNext3F; diff --git a/wally-pipelined/src/mmu/mmu.sv b/wally-pipelined/src/mmu/mmu.sv new file mode 100644 index 00000000..fefce5ea --- /dev/null +++ b/wally-pipelined/src/mmu/mmu.sv @@ -0,0 +1,96 @@ +/////////////////////////////////////////// +// mmu.sv +// +// Written: david_harris@hmc.edu and kmacsaigoren@hmc.edu 4 June 2021 +// Modified: +// +// Purpose: Memory management unit, including TLB, PMA, PMP +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software +// is furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES +// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +/////////////////////////////////////////// + + +`include "wally-config.vh" + +// The TLB will have 2**ENTRY_BITS total entries + +module mmu #(parameter IMMU = 0) ( + input clk, reset, + // Current value of satp CSR (from privileged unit) + input [`XLEN-1:0] SATP_REGW, + input STATUS_MXR, STATUS_SUM, + + // Current privilege level of the processeor + input [1:0] PrivilegeModeW, + + // 00 - TLB is not being accessed + // 1x - TLB is accessed for a read (or an instruction) + // x1 - TLB is accessed for a write + // 11 - TLB is accessed for both read and write + input [1:0] TLBAccessType, + + // Virtual address input + input [`XLEN-1:0] VirtualAddress, + + // Controls for writing a new entry to the TLB + input [`XLEN-1:0] PageTableEntryWrite, + input [1:0] PageTypeWrite, + input TLBWrite, + + // Invalidate all TLB entries + input TLBFlush, + + // Physical address outputs + output [`XLEN-1:0] PhysicalAddress, + output TLBMiss, + output TLBHit, + + // Faults + output TLBPageFault, + + // PMA checker signals + input logic [31:0] HADDR, + input logic [2:0] HSIZE, HBURST, + input logic HWRITE, + input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, + output logic Cacheable, Idempotent, AtomicAllowed, + output logic SquashBusAccess, + output logic [5:0] HSELRegions + +); + + // Translation lookaside buffer + + tlb tlb #(.ENTRY_BITS(.ENTRY_BITS), .ITLB(IMMU)) itlb(.*); + + /////////////////////////////////////////// + // Check physical memory accesses + /////////////////////////////////////////// + + pmachecker pmachecker(.*); + pmpchecker pmpchecker(.*); + + *** to edit + edit PMP/PMA to use phyisical address information instead of HADDR / AHB signals [Later after it works] + *move PMA checker to MMU from privileged + *move PMP checker to MMU from privileged + *delete PMA/PMP signals from priviliged & above no longer needed + replace TLB with MMU in IFU and DMEM + adjust for two PMA/PMP outputs (IFU, DMEM) instead of just one for Bus + Move M_MODE, other constants from each config file to wally-constants, #include wally-constants as needed + +endmodule \ No newline at end of file diff --git a/wally-pipelined/src/privileged/pmachecker.sv b/wally-pipelined/src/mmu/pmachecker.sv similarity index 97% rename from wally-pipelined/src/privileged/pmachecker.sv rename to wally-pipelined/src/mmu/pmachecker.sv index 2526ec5e..db4c648b 100644 --- a/wally-pipelined/src/privileged/pmachecker.sv +++ b/wally-pipelined/src/mmu/pmachecker.sv @@ -66,7 +66,7 @@ module pmachecker ( assign ValidBootTim = '1; assign ValidTim = '1; - assign ValidCLINT = ~ExecuteAccessF && ((HSIZE == 3'b011) || (HSIZE == 3'b010)); + assign ValidCLINT = ~ExecuteAccessF && ((HSIZE == 3'b011 && `XLEN==64) || (HSIZE == 3'b010 && `XLEN==32)); assign ValidGPIO = ~ExecuteAccessF && (HSIZE == 3'b010); assign ValidUART = ~ExecuteAccessF && (HSIZE == 3'b000); assign ValidPLIC = ~ExecuteAccessF && (HSIZE == 3'b010); diff --git a/wally-pipelined/src/privileged/pmpadrdec.sv b/wally-pipelined/src/mmu/pmpadrdec.sv similarity index 100% rename from wally-pipelined/src/privileged/pmpadrdec.sv rename to wally-pipelined/src/mmu/pmpadrdec.sv diff --git a/wally-pipelined/src/privileged/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv similarity index 100% rename from wally-pipelined/src/privileged/pmpchecker.sv rename to wally-pipelined/src/mmu/pmpchecker.sv diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv index a29fb56e..95e757a8 100644 --- a/wally-pipelined/src/privileged/privileged.sv +++ b/wally-pipelined/src/privileged/privileged.sv @@ -26,6 +26,7 @@ `include "wally-config.vh" +// *** remove signals not needed by PMA/PMP now that it is moved module privileged ( input logic clk, reset, input logic FlushW, @@ -58,15 +59,6 @@ module privileged ( output logic STATUS_MXR, STATUS_SUM, output logic [2:0] FRM_REGW, input logic FlushD, FlushE, FlushM, StallD, StallW, StallE, StallM, - - // PMA checker signals - input logic [31:0] HADDR, - input logic [2:0] HSIZE, HBURST, - input logic HWRITE, - input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, - output logic Cacheable, Idempotent, AtomicAllowed, - output logic SquashBusAccess, - output logic [5:0] HSELRegions ); logic [1:0] NextPrivilegeModeM; @@ -143,13 +135,6 @@ module privileged ( csr csr(.*); - /////////////////////////////////////////// - // Check physical memory accesses - /////////////////////////////////////////// - - pmachecker pmachecker(.*); - pmpchecker pmpchecker(.*); - /////////////////////////////////////////// // Extract exceptions by name and handle them ///////////////////////////////////////////