diff --git a/wally-pipelined/config/buildroot/wally-config.vh b/wally-pipelined/config/buildroot/wally-config.vh index 8bf0b381..fb15098e 100644 --- a/wally-pipelined/config/buildroot/wally-config.vh +++ b/wally-pipelined/config/buildroot/wally-config.vh @@ -43,9 +43,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. @@ -59,6 +59,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/busybear/wally-config.vh b/wally-pipelined/config/busybear/wally-config.vh index 8ad4292b..59daaf36 100644 --- a/wally-pipelined/config/busybear/wally-config.vh +++ b/wally-pipelined/config/busybear/wally-config.vh @@ -44,9 +44,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1. @@ -60,6 +60,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/coremark-64i/wally-config.vh b/wally-pipelined/config/coremark-64i/wally-config.vh deleted file mode 100644 index ade6f3cb..00000000 --- a/wally-pipelined/config/coremark-64i/wally-config.vh +++ /dev/null @@ -1,95 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation -// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, -// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software -// is furnished to do so, subject to the following conditions: -// -// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -// -// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS -// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT -// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -/////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -//`define MISA (32'h00000104) -`define MISA (32'h00000104 | 1<<5 | 1<<18 | 1 << 20) -`define ZCSR_SUPPORTED 1 -`define ZCOUNTERS_SUPPORTED 1 - -// Microarchitectural Features -`define UARCH_PIPELINED 1 -`define UARCH_SUPERSCALR 0 -`define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 -`define MEM_DTIM 1 -`define MEM_ICACHE 0 -`define MEM_VIRTMEM 0 - -// Address space -`define RESET_VECTOR 64'h0000000000001000 - -// Bus Interface width -`define AHBW 64 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 2048 -`define DCACHE_BLOCKLENINBITS 256 -`define DCACHE_REPLBITS 3 - -// Peripheral Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -`define BOOTTIM_SUPPORTED 1'b1 -`define BOOTTIM_BASE 56'h00001000 -`define BOOTTIM_RANGE 56'h00000FFF -`define TIM_SUPPORTED 1'b1 -`define TIM_BASE 56'h80000000 -`define TIM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10012000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 0 - - -// Hardware configuration -`define UART_PRESCALE 1 - diff --git a/wally-pipelined/config/coremark/wally-config.vh b/wally-pipelined/config/coremark/wally-config.vh index b8fc305c..8fa6f8c9 100644 --- a/wally-pipelined/config/coremark/wally-config.vh +++ b/wally-pipelined/config/coremark/wally-config.vh @@ -43,9 +43,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 @@ -59,6 +59,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Address space `define RESET_VECTOR 64'h00000000000100b0 diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index 8d3fcfe7..4389423b 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -44,9 +44,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 @@ -60,6 +60,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/wally-pipelined/config/rv32ic/wally-config.vh b/wally-pipelined/config/rv32ic/wally-config.vh index d6b3327c..1355b5c9 100644 --- a/wally-pipelined/config/rv32ic/wally-config.vh +++ b/wally-pipelined/config/rv32ic/wally-config.vh @@ -42,9 +42,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 @@ -58,6 +58,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/rv32icfd/wally-config.vh b/wally-pipelined/config/rv32icfd/wally-config.vh index 2b9f9dfd..e27f40d0 100644 --- a/wally-pipelined/config/rv32icfd/wally-config.vh +++ b/wally-pipelined/config/rv32icfd/wally-config.vh @@ -42,9 +42,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 @@ -58,6 +58,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/rv64BP/wally-config.vh b/wally-pipelined/config/rv64BP/wally-config.vh index aa9b96a9..e4cef08c 100644 --- a/wally-pipelined/config/rv64BP/wally-config.vh +++ b/wally-pipelined/config/rv64BP/wally-config.vh @@ -44,9 +44,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 @@ -60,6 +60,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Address space `define RESET_VECTOR 64'h0000000000000000 diff --git a/wally-pipelined/config/rv64ic/wally-config.vh b/wally-pipelined/config/rv64ic/wally-config.vh index a46d2a0a..88d3fd03 100644 --- a/wally-pipelined/config/rv64ic/wally-config.vh +++ b/wally-pipelined/config/rv64ic/wally-config.vh @@ -43,9 +43,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 @@ -59,6 +59,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 64 diff --git a/wally-pipelined/config/rv64icfd/wally-config.vh b/wally-pipelined/config/rv64icfd/wally-config.vh index f2d0816c..ec889d64 100644 --- a/wally-pipelined/config/rv64icfd/wally-config.vh +++ b/wally-pipelined/config/rv64icfd/wally-config.vh @@ -43,9 +43,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 @@ -59,6 +59,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Legal number of PMP entries are 0, 16, or 64 `define PMP_ENTRIES 16 diff --git a/wally-pipelined/config/rv64imc/wally-config.vh b/wally-pipelined/config/rv64imc/wally-config.vh index a51a951e..12c220b6 100644 --- a/wally-pipelined/config/rv64imc/wally-config.vh +++ b/wally-pipelined/config/rv64imc/wally-config.vh @@ -42,9 +42,9 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define MEM_DCACHE 0 +`define MEM_DCACHE 1 `define MEM_DTIM 1 -`define MEM_ICACHE 0 +`define MEM_ICACHE 1 `define MEM_VIRTMEM 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 @@ -58,6 +58,9 @@ `define DCACHE_WAYSIZEINBYTES 2048 `define DCACHE_BLOCKLENINBITS 256 `define DCACHE_REPLBITS 3 +`define ICACHE_NUMWAYS 1 +`define ICACHE_WAYSIZEINBYTES 4096 +`define ICACHE_BLOCKLENINBITS 256 // Address space `define RESET_VECTOR 64'h0000000080000000 diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 3cdba4ce..3b5a649f 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -68,10 +68,14 @@ module dcache output logic [`XLEN-1:0] HWDATA // to ahb ); - localparam integer BLOCKLEN = 256; +/* localparam integer BLOCKLEN = 256; localparam integer NUMLINES = 64; localparam integer NUMWAYS = 4; - localparam integer NUMREPL_BITS = 3; + localparam integer NUMREPL_BITS = 3;*/ + localparam integer BLOCKLEN = `DCACHE_BLOCKLENINBITS; + localparam integer NUMLINES = `DCACHE_WAYSIZEINBYTES*8/BLOCKLEN; + localparam integer NUMWAYS = `DCACHE_NUMWAYS; + localparam integer NUMREPL_BITS = `DCACHE_REPLBITS; localparam integer BLOCKBYTELEN = BLOCKLEN/8; localparam integer OFFSETLEN = $clog2(BLOCKBYTELEN); diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv index 943ab1b8..99c43df5 100644 --- a/wally-pipelined/src/cache/icache.sv +++ b/wally-pipelined/src/cache/icache.sv @@ -53,9 +53,8 @@ module icache ); // Configuration parameters - // TODO Move these to a config file - localparam integer BLOCKLEN = 256; - localparam integer NUMLINES = 512; + localparam integer BLOCKLEN = `ICACHE_BLOCKLENINBITS; + localparam integer NUMLINES = `ICACHE_WAYSIZEINBYTES*8/`ICACHE_BLOCKLENINBITS; // Input signals to cache memory logic FlushMem; diff --git a/wally-pipelined/testbench/testbench-imperas.sv b/wally-pipelined/testbench/testbench-imperas.sv index e45f8233..079ac6b1 100644 --- a/wally-pipelined/testbench/testbench-imperas.sv +++ b/wally-pipelined/testbench/testbench-imperas.sv @@ -737,12 +737,26 @@ endmodule module riscvassertions(); // Legal number of PMP entries are 0, 16, or 64 initial begin - assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries"); + assert (`PMP_ENTRIES == 0 || `PMP_ENTRIES==16 || `PMP_ENTRIES==64) else $error("Illegal number of PMP entries: PMP_ENTRIES must be 0, 16, or 64"); assert (`F_SUPPORTED || ~`D_SUPPORTED) else $error("Can't support double without supporting float"); assert (`XLEN == 64 || ~`D_SUPPORTED) else $error("Wally does not yet support D extensions on RV32"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 || `MEM_DCACHE == 0 || `MEM_VIRTMEM == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_BLOCKLENINBITS >= 128 || `MEM_DCACHE == 0) else $error("DCACHE_BLOCKLENINBITS must be at least 128 when caches are enabled"); + assert (`DCACHE_BLOCKLENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_BLOCKLENINBITS must be smaller than way size"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 || `MEM_ICACHE == 0 || `MEM_VIRTMEM == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_BLOCKLENINBITS >= 32 || `MEM_ICACHE == 0) else $error("ICACHE_BLOCKLENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_BLOCKLENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_BLOCKLENINBITS must be smaller than way size"); + assert (2**$clog2(`DCACHE_BLOCKLENINBITS) == `DCACHE_BLOCKLENINBITS) else $error("DCACHE_BLOCKLENINBITS must be a power of 2"); + assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ICACHE_BLOCKLENINBITS) == `ICACHE_BLOCKLENINBITS) else $error("ICACHE_BLOCKLENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (`ICACHE_NUMWAYS == 1 || `MEM_ICACHE == 0) else $error("Multiple Instruction Cache ways not yet implemented"); + assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES) else $error("ITLB_ENTRIES must be a power of 2"); + assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES) else $error("DTLB_ENTRIES must be a power of 2"); end endmodule + /* verilator lint_on STMTDLY */ /* verilator lint_on WIDTH */