From a18f06c20b754a2bd09bfa2989f34ac6a96a55af Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 11 Mar 2022 11:03:36 -0600 Subject: [PATCH] Moved subcacheline read inside the cache. --- pipelined/src/cache/cache.sv | 20 +++++++++++++++++--- pipelined/src/ifu/ifu.sv | 13 ++++--------- pipelined/src/lsu/lsu.sv | 17 ++++------------- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index 9992650e..876470a2 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" -module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( +module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGWPL, WORDLEN, MUXINTERVAL) ( input logic clk, input logic reset, // cpu side @@ -48,7 +48,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( // to performance counters to cpu output logic CacheMiss, output logic CacheAccess, - output logic save, restore, // lsu control input logic IgnoreRequestTLB, input logic IgnoreRequestTrapM, @@ -57,9 +56,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( output logic CacheFetchLine, output logic CacheWriteLine, input logic CacheBusAck, + input logic [LOGWPL-1:0] WordCount, + input logic LSUBusWriteCrit, output logic [`PA_BITS-1:0] CacheBusAdr, input logic [LINELEN-1:0] CacheBusWriteData, - output logic [LINELEN-1:0] ReadDataLine); + output logic [WORDLEN-1:0] ReadDataWord); // Cache parameters localparam LINEBYTELEN = LINELEN/8; @@ -102,6 +103,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( logic [NUMWAYS-1:0] SelectedWay; logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; logic [1:0] CacheRW, CacheAtomic; + logic [LINELEN-1:0] ReadDataLine; + logic [`PA_BITS-1:0] WordOffsetAddr; + logic save, restore; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -139,6 +143,16 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS) ( flopenr #(NUMWAYS) wayhitsavereg(clk, save, reset, HitWay, HitWaySaved); mux2 #(NUMWAYS) saverestoremux(HitWay, HitWaySaved, restore, HitWayFinal); end else assign HitWayFinal = HitWay; + + + mux2 #(`PA_BITS) WordAdrrMux(.d0(PAdr), + .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), + .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. + + subcachelineread #(LINELEN, WORDLEN, MUXINTERVAL) subcachelineread( // *** merge into cache + .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, + .ReadDataLine, .ReadDataWord); + ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index cf380a0e..743dfbfc 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -188,7 +188,6 @@ module ifu ( logic [LINELEN-1:0] ICacheBusWriteData; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; - logic save,restore; logic [31:0] temp; logic SelUncachedAdr; @@ -212,15 +211,15 @@ module ifu ( if(CACHE_ENABLED) begin : icache cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), - .NUMWAYS(`ICACHE_NUMWAYS)) + .NUMWAYS(`ICACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(32), .MUXINTERVAL(16)) icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .IgnoreRequestTrapM('0), .CacheBusWriteData(ICacheBusWriteData), .CacheBusAck(ICacheBusAck), .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), .CacheFetchLine(ICacheFetchLine), - .CacheWriteLine(), .ReadDataLine(ReadDataLine), - .save, .restore, .Cacheable(CacheableF), + .CacheWriteLine(), .ReadDataWord(FinalInstrRawF), + .Cacheable(CacheableF), .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess), - .ByteMask('0), + .ByteMask('0), .WordCount('0), .LSUBusWriteCrit('0), .FinalWriteData('0), .RW(2'b10), .Atomic('0), .FlushCache('0), @@ -228,10 +227,6 @@ module ifu ( .PAdr(PCPF), .CacheCommitted(), .InvalidateCacheM(InvalidateICacheM)); - subcachelineread #(LINELEN, 32, 16) subcachelineread( - .clk, .reset, .PAdr(PCPF), .save, .restore, - .ReadDataLine, .ReadDataWord(FinalInstrRawF)); - end else begin : passthrough assign {ICacheFetchLine, ICacheBusAdr, ICacheStallF, FinalInstrRawF} = '0; assign ICacheAccess = CacheableF; assign ICacheMiss = CacheableF; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 004ce372..26f428f5 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -207,8 +207,6 @@ module lsu ( logic DCacheWriteLine; logic DCacheFetchLine; logic DCacheBusAck; - logic save, restore; - logic [`PA_BITS-1:0] WordOffsetAddr; logic SelBus; logic [LOGWPL-1:0] WordCount; @@ -229,24 +227,17 @@ module lsu ( if(CACHE_ENABLED) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), - .NUMWAYS(`DCACHE_NUMWAYS)) dcache( - .clk, .reset, .CPUBusy, .save, .restore, .RW(LSURWM), .Atomic(LSUAtomicM), + .NUMWAYS(`DCACHE_NUMWAYS), .LOGWPL(LOGWPL), .WORDLEN(`XLEN), .MUXINTERVAL(`XLEN)) dcache( + .clk, .reset, .CPUBusy, .LSUBusWriteCrit, .RW(LSURWM), .Atomic(LSUAtomicM), .FlushCache(FlushDCacheM), .NextAdr(LSUAdrE), .PAdr(LSUPAdrM), - .ByteMask(ByteMaskM), + .ByteMask(ByteMaskM), .WordCount, .FinalWriteData(FinalWriteDataM), .Cacheable(CacheableM), .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess), .IgnoreRequestTLB, .IgnoreRequestTrapM, .CacheCommitted(DCacheCommittedM), - .CacheBusAdr(DCacheBusAdr), .ReadDataLine(ReadDataLineM), + .CacheBusAdr(DCacheBusAdr), .ReadDataWord(ReadDataWordM), .CacheBusWriteData(DCacheBusWriteData), .CacheFetchLine(DCacheFetchLine), .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .InvalidateCacheM(1'b0)); - mux2 #(`PA_BITS) WordAdrrMux(.d0(LSUPAdrM), - .d1({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)), .s(LSUBusWriteCrit), - .y(WordOffsetAddr)); // *** can reduce width of mux. only need the offset. - - subcachelineread #(LINELEN, `XLEN, `XLEN) subcachelineread( // *** merge into cache - .clk, .reset, .PAdr(WordOffsetAddr), .save, .restore, - .ReadDataLine(ReadDataLineM), .ReadDataWord(ReadDataWordM)); end else begin : passthrough assign {ReadDataWordM, DCacheStallM, DCacheCommittedM, DCacheFetchLine, DCacheWriteLine} = '0;