From a14c71bd9597dfa4e1a41f61d974197349e14abf Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Mon, 20 Feb 2023 18:36:33 -0600 Subject: [PATCH] Renamed branch predictors and consolidated global and gshare predictors. --- config/buildroot/wally-config.vh | 2 +- config/fpga/wally-config.vh | 4 +- config/rv32e/wally-config.vh | 2 +- config/rv32gc/wally-config.vh | 2 +- config/rv32i/wally-config.vh | 2 +- config/rv32imc/wally-config.vh | 2 +- config/rv64fpquad/wally-config.vh | 2 +- config/rv64gc/wally-config.vh | 2 +- config/rv64i/wally-config.vh | 2 +- sim/wave.do | 117 ++++++++++-------- src/ifu/bpred/bpred.sv | 40 +++--- src/ifu/bpred/gshare.sv | 73 ++++++++--- .../{gshareForward.sv => gsharebasic.sv} | 69 ++++------- 13 files changed, 167 insertions(+), 152 deletions(-) rename src/ifu/bpred/{gshareForward.sv => gsharebasic.sv} (53%) diff --git a/config/buildroot/wally-config.vh b/config/buildroot/wally-config.vh index 813566a2..12c7db2d 100644 --- a/config/buildroot/wally-config.vh +++ b/config/buildroot/wally-config.vh @@ -130,7 +130,7 @@ `define PLIC_GPIO_ID 3 `define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT `define BPRED_SIZE 10 `define BTB_SIZE 10 diff --git a/config/fpga/wally-config.vh b/config/fpga/wally-config.vh index 00b84f23..a2488c06 100644 --- a/config/fpga/wally-config.vh +++ b/config/fpga/wally-config.vh @@ -139,8 +139,8 @@ `define PLIC_GPIO_ID 3 `define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 -`define BPRED_SIZE 10 +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +`define BPRED_SIZE 12 `define BTB_SIZE 10 diff --git a/config/rv32e/wally-config.vh b/config/rv32e/wally-config.vh index bda7b449..6e0de334 100644 --- a/config/rv32e/wally-config.vh +++ b/config/rv32e/wally-config.vh @@ -134,7 +134,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 0 -`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT `define BPRED_SIZE 10 `define BTB_SIZE 10 diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh index 88fc70ad..57857f3b 100644 --- a/config/rv32gc/wally-config.vh +++ b/config/rv32gc/wally-config.vh @@ -133,7 +133,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT `define BPRED_SIZE 10 `define BTB_SIZE 10 diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index 86bad6f9..efbf6e7c 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -134,7 +134,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 0 -`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT `define BPRED_SIZE 10 `define BTB_SIZE 10 diff --git a/config/rv32imc/wally-config.vh b/config/rv32imc/wally-config.vh index eb9ce652..8fb29a67 100644 --- a/config/rv32imc/wally-config.vh +++ b/config/rv32imc/wally-config.vh @@ -133,7 +133,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 0 -`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT `define BPRED_SIZE 10 `define BTB_SIZE 10 diff --git a/config/rv64fpquad/wally-config.vh b/config/rv64fpquad/wally-config.vh index ea36327d..dd8058c2 100644 --- a/config/rv64fpquad/wally-config.vh +++ b/config/rv64fpquad/wally-config.vh @@ -136,7 +136,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT `define BPRED_SIZE 10 `define BTB_SIZE 10 diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh index c323a9f0..4100f4c0 100644 --- a/config/rv64gc/wally-config.vh +++ b/config/rv64gc/wally-config.vh @@ -136,7 +136,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 1 -`define BPRED_TYPE "BP_GSHARE_FORWARD" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2 +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT `define BPRED_SIZE 10 `define BTB_SIZE 10 diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh index 7cc8d887..a3702c3f 100644 --- a/config/rv64i/wally-config.vh +++ b/config/rv64i/wally-config.vh @@ -136,7 +136,7 @@ `define PLIC_UART_ID 10 `define BPRED_SUPPORTED 0 -`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE +`define BPRED_TYPE "BP_GSHARE" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT `define BPRED_SIZE 10 `define BTB_SIZE 10 diff --git a/sim/wave.do b/sim/wave.do index 6564e654..23413957 100644 --- a/sim/wave.do +++ b/sim/wave.do @@ -37,17 +37,17 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW -add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE -add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCF -add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD -add wave -noupdate -expand -group PCS /testbench/dut/core/PCE -add wave -noupdate -expand -group PCS /testbench/dut/core/PCM -add wave -noupdate -expand -group PCS /testbench/PCW +add wave -noupdate -group {instruction pipeline} /testbench/InstrFName +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE +add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCF +add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD +add wave -noupdate -group PCS /testbench/dut/core/PCE +add wave -noupdate -group PCS /testbench/dut/core/PCM +add wave -noupdate -group PCS /testbench/PCW add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD add wave -noupdate -group {Decode Stage} /testbench/InstrDName @@ -95,15 +95,15 @@ add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/ add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/BPPredPCF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/SelBPPredF -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F -add wave -noupdate -expand -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/NextValidPCE +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/BPPredPCF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/SelBPPredF +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F +add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1 add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2 @@ -556,21 +556,21 @@ add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/c add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Key1} add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query0} add wave -noupdate -group ifu -group itlb -expand -group key19 {/testbench/dut/core/ifu/immu/immu/tlb/tlb/tlbcam/camlines[19]/Query1} -add wave -noupdate -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} -add wave -noupdate -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} -add wave -noupdate -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} -add wave -noupdate -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} -add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} -add wave -noupdate -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} -add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} -add wave -noupdate -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} +add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]} +add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]} +add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP DIRECTION WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[4]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[5]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BTA/JTA WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[6]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {JAL(R) INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[7]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]} +add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]} +add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]} +add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]} +add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]} +add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[12]} add wave -noupdate -group {ifu } -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/HREADY add wave -noupdate -group {ifu } /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/FetchBuffer @@ -602,23 +602,23 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF -add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE -add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM -add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD -add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD -add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM -add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF +add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE +add wave -noupdate -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM +add wave -noupdate -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD +add wave -noupdate -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD +add wave -noupdate -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM +add wave -noupdate -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF @@ -627,9 +627,16 @@ add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/In add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassF +add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF +add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheAccess +add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheMiss +add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/ICacheAccess +add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/DCacheMiss +add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/InstrValidNotFlushedM TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {1156601 ns} 1} {{Cursor 5} {394986 ns} 0} -quietly wave cursor active 5 +WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {391801 ns} 1} {{Cursor 4} {368581 ns} 0} {{Cursor 5} {394987 ns} 1} +quietly wave cursor active 4 configure wave -namecolwidth 250 configure wave -valuecolwidth 194 configure wave -justifyvalue left @@ -644,4 +651,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {394883 ns} {395051 ns} +WaveRestoreZoom {368125 ns} {368797 ns} diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index b0ea2683..da4070e1 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -94,36 +94,32 @@ module bpred ( // Part 1 branch direction prediction // look into the 2 port Sram model. something is wrong. - if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor + if (`BPRED_TYPE == "BP_TWOBIT") begin:Predictor twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor - globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .DirPredictionF, .DirPredictionWrongE, - .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - - end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor - speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE); - - end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor + end else if (`BPRED_TYPE == "BP_GSHARE") begin:Predictor gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, - .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - - end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor - speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .InstrClassM, .WrongPredInstrClassD, .PCSrcE); - - end else if (`BPRED_TYPE == "BP_GSHARE_FORWARD") begin:Predictor - gshareForward #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); + + end else if (`BPRED_TYPE == "BP_GLOBAL") begin:Predictor + gshare #(`BPRED_SIZE, "global") DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE, + .BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), + .PCSrcE); + + end else if (`BPRED_TYPE == "BP_GSHARE_BASIC") begin:Predictor + gsharebasic #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, + .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); + + end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor + gsharebasic #(`BPRED_SIZE, "global") DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, + .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor // *** Fix me diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 35a73fb0..bb9d25f4 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -28,7 +28,8 @@ `include "wally-config.vh" -module gshare #(parameter k = 10) ( +module gshare #(parameter k = 10, + parameter string TYPE = "gshare") ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -36,28 +37,60 @@ module gshare #(parameter k = 10) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCM, - input logic BranchInstrE, BranchInstrM, PCSrcE + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, + input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, PCSrcE ); - logic [k-1:0] IndexNextF, IndexE; - logic [1:0] DirPredictionD, DirPredictionE; + logic MatchF, MatchD, MatchE, MatchM; + logic MatchNextX, MatchXF; + + logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPrediction, ForwardDirPredictionF; logic [1:0] NewDirPredictionE, NewDirPredictionM; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; - logic [k-1:0] GHRNext; + logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM; + + logic [k-1:0] GHRF, GHRD, GHRE, GHRM; + logic [k-1:0] GHRNextM, GHRNextF; logic PCSrcM; - assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; + if(TYPE == "gshare") begin + assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; + assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; + assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]}; + assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; + assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; + end else if(TYPE == "global") begin + assign IndexNextF = {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; + assign IndexF = {PCF[k+1] ^ PCF[1], PCF[k:2]}; + assign IndexD = {PCD[k+1] ^ PCD[1], PCD[k:2]}; + assign IndexE = {PCE[k+1] ^ PCE[1], PCE[k:2]}; + assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]}; + end + + assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); + assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); + assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); + assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM); + assign MatchNextX = MatchF | MatchD | MatchE | MatchM; + + flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); + + assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} : + MatchD ? {2{DirPredictionD[1]}} : + MatchE ? {NewDirPredictionE} : + NewDirPredictionM ; + flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); + + assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; + ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), - .rd1(DirPredictionF), - .wa2(IndexE), + .rd1(TableDirPredictionF), + .wa2(IndexM), .wd2(NewDirPredictionM), - .we2(BranchInstrM & ~StallW & ~FlushW), + .we2(BranchInstrM), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -68,14 +101,14 @@ module gshare #(parameter k = 10) ( assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR; - flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR); + assign GHRNextF = BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF; + assign GHRF = BranchInstrD ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD; + assign GHRD = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE; + assign GHRE = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM; + + assign GHRNextM = {PCSrcM, GHRM[k-1:1]}; + + flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNextM, GHRM); flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); - flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); - flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); - flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); - flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); - - endmodule diff --git a/src/ifu/bpred/gshareForward.sv b/src/ifu/bpred/gsharebasic.sv similarity index 53% rename from src/ifu/bpred/gshareForward.sv rename to src/ifu/bpred/gsharebasic.sv index 57bcd4be..45438b85 100644 --- a/src/ifu/bpred/gshareForward.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -28,7 +28,8 @@ `include "wally-config.vh" -module gshareForward #(parameter k = 10) ( +module gsharebasic #(parameter k = 10, + parameter string TYPE = "global") ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -36,54 +37,33 @@ module gshareForward #(parameter k = 10) ( output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, - input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, PCSrcE + input logic [`XLEN-1:0] PCNextF, PCM, + input logic BranchInstrE, BranchInstrM, PCSrcE ); - logic MatchF, MatchD, MatchE, MatchM; - logic MatchNextX, MatchXF; - - logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE, ForwardNewDirPrediction, ForwardDirPredictionF; + logic [k-1:0] IndexNextF, IndexE; + logic [1:0] DirPredictionD, DirPredictionE; logic [1:0] NewDirPredictionE, NewDirPredictionM; - - logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM; - logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR; - logic [k-1:0] GHRNext, GHRNextF; + logic [k-1:0] GHRNext; logic PCSrcM; - assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; - - assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]}; - assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]}; - assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]}; - assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; - - assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF); - assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD); - assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE); - assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM); - assign MatchNextX = MatchF | MatchD | MatchE | MatchM; - - flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF); - - assign ForwardNewDirPrediction = MatchF ? {2{DirPredictionF[1]}} : - MatchD ? {2{DirPredictionD[1]}} : - MatchE ? {NewDirPredictionE} : - NewDirPredictionM ; + if(TYPE == "gshare") begin + assign IndexNextF = GHR ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; + assign IndexE = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]}; + end else if(TYPE == "global") begin + assign IndexNextF = {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]}; + assign IndexE = {PCM[k+1] ^ PCM[1], PCM[k:2]}; + end - flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF); - - assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF; - ram2p1r1wbe #(2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallM & ~FlushM), .ra1(IndexNextF), - .rd1(TableDirPredictionF), - .wa2(IndexM), + .rd1(DirPredictionF), + .wa2(IndexE), .wd2(NewDirPredictionM), - .we2(BranchInstrM), + .we2(BranchInstrM & ~StallW & ~FlushW), .bwe2(1'b1)); flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD); @@ -94,15 +74,14 @@ module gshareForward #(parameter k = 10) ( assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE; - assign GHRNextF = BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} : GHRF; - assign GHRF = BranchInstrD ? {DirPredictionD[1], GHRD[k-1:1]} : GHRD; - assign GHRD = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE; - assign GHRE = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM; - assign GHRNext = BranchInstrM ? {PCSrcM, GHR[k-1:1]} : GHR; - assign GHRM = GHR; - - flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchInstrM, GHRNext, GHR); + flopenr #(k) GHRReg(clk, reset, ~StallM & ~FlushM & BranchInstrM, GHRNext, GHR); flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM); + flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF); + flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD); + flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE); + flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM); + + endmodule