diff --git a/wally-pipelined/src/cache/icache.sv b/wally-pipelined/src/cache/icache.sv
index 6c27e347..7b6c4d47 100644
--- a/wally-pipelined/src/cache/icache.sv
+++ b/wally-pipelined/src/cache/icache.sv
@@ -48,7 +48,6 @@ module icache
    // High if the icache is requesting a stall
    output logic 							ICacheStallF,
    input logic 								CacheableF,
-   input logic 								ITLBMissF,
    input logic 								InvalidateICacheM,
   
    // The raw (not decompressed) instruction that was requested
@@ -159,7 +158,6 @@ module icache
 					   .CPUBusy,
 					   .ICacheMemWriteEnable,
 					   .ICacheStallF,
-					   .ITLBMissF,
 					   .IgnoreRequest,
 					   .ICacheBusAck,
 					   .ICacheFetchLine,
diff --git a/wally-pipelined/src/cache/icachefsm.sv b/wally-pipelined/src/cache/icachefsm.sv
index 476a9022..b4a41d33 100644
--- a/wally-pipelined/src/cache/icachefsm.sv
+++ b/wally-pipelined/src/cache/icachefsm.sv
@@ -31,9 +31,6 @@ module icachefsm
 
    input logic 		  CPUBusy,
 
-   // inputs from mmu
-   input logic 		  ITLBMissF,
-
    input logic 		  IgnoreRequest,
    input logic 		  CacheableF,
 
@@ -89,11 +86,6 @@ module icachefsm
 		if(IgnoreRequest) begin
 		  SelAdr = 1'b1;
 		  NextState = STATE_READY;
-		end else 
-		if(ITLBMissF) begin
-		  NextState = STATE_READY;
-		  SelAdr = 1'b1;
-		  ICacheStallF = 1'b0;
 		end
 		else if (CacheableF & hit) begin
           ICacheStallF = 1'b0;
diff --git a/wally-pipelined/src/ifu/ifu.sv b/wally-pipelined/src/ifu/ifu.sv
index 0b563b4e..f2d64ddf 100644
--- a/wally-pipelined/src/ifu/ifu.sv
+++ b/wally-pipelined/src/ifu/ifu.sv
@@ -247,7 +247,7 @@ module ifu (
   generate
 	if(`MEM_ICACHE) begin : icache
 	  icache icache(.clk, .reset, .CPUBusy, .IgnoreRequest, .ICacheMemWriteData , .ICacheBusAck,
-					.ICacheBusAdr, .ICacheStallF, .ITLBMissF, .FinalInstrRawF, 
+					.ICacheBusAdr, .ICacheStallF, .FinalInstrRawF, 
 					.ICacheFetchLine,
 					.CacheableF,
 					.PCNextF(PCNextFMux),