diff --git a/addins/embench-iot b/addins/embench-iot
index 2d2aaa7b..261a65e0 160000
--- a/addins/embench-iot
+++ b/addins/embench-iot
@@ -1 +1 @@
-Subproject commit 2d2aaa7b85c60219c591555b647dfa1785ffe1b3
+Subproject commit 261a65e0a2d3e8d62d81b1d8fe7e309a096bc6a9
diff --git a/addins/riscv-arch-test b/addins/riscv-arch-test
index effd553a..307c77b2 160000
--- a/addins/riscv-arch-test
+++ b/addins/riscv-arch-test
@@ -1 +1 @@
-Subproject commit effd553a6a91ed9b0ba251796a8a44505a45174f
+Subproject commit 307c77b26e070ae85ffea665ad9b642b40e33c86
diff --git a/addins/riscv-dv b/addins/riscv-dv
index cb4295f9..a7e27bc0 160000
--- a/addins/riscv-dv
+++ b/addins/riscv-dv
@@ -1 +1 @@
-Subproject commit cb4295f9ce5da2881d7746015a6105adb8f09071
+Subproject commit a7e27bc046405f0dbcde091be99f5a5d564e2172
diff --git a/addins/riscv-tests b/addins/riscv-tests
index 3e2bf06b..cf04274f 160000
--- a/addins/riscv-tests
+++ b/addins/riscv-tests
@@ -1 +1 @@
-Subproject commit 3e2bf06b071a77ae62c09bf07c5229d1f9397d94
+Subproject commit cf04274f50621fd9ef9147793cca6dd1657985c7
diff --git a/pipelined/src/ppa/ppa.sv b/pipelined/src/ppa/ppa.sv
index b827b669..1ce9b449 100644
--- a/pipelined/src/ppa/ppa.sv
+++ b/pipelined/src/ppa/ppa.sv
@@ -257,13 +257,14 @@ module ppa_prioriyencoder #(parameter N = 8) (
   //  Rather than linear.
 
   // create thermometer code mask
-  genvar i;
-  for (i=0; i<N; i++) begin:pri
-    if (a[i]) y= i;
-  end
+  int i;
+  always_comb
+    for (i=0; i<N; i++) begin:pri
+      if (a[i]) y= i;
+    end
 endmodule
 
-module decoder (
+module ppa_decoder (
   input  logic  [$clog2(N)-1:0] a,
   output logic  [N-1:0] y);
   always_comb begin 
@@ -272,7 +273,7 @@ module decoder (
   end
 endmodule
 
-module mux2 #(parameter WIDTH = 8) (
+module ppa_mux2 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] d0, d1, 
   input  logic             s, 
   output logic [WIDTH-1:0] y);
@@ -280,7 +281,7 @@ module mux2 #(parameter WIDTH = 8) (
   assign y = s ? d1 : d0; 
 endmodule
 
-module mux3 #(parameter WIDTH = 8) (
+module ppa_mux3 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] d0, d1, d2,
   input  logic [1:0]       s, 
   output logic [WIDTH-1:0] y);
@@ -288,7 +289,7 @@ module mux3 #(parameter WIDTH = 8) (
   assign y = s[1] ? d2 : (s[0] ? d1 : d0); 
 endmodule
 
-module mux4 #(parameter WIDTH = 8) (
+module ppa_mux4 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] d0, d1, d2, d3,
   input  logic [1:0]       s, 
   output logic [WIDTH-1:0] y);
@@ -296,7 +297,7 @@ module mux4 #(parameter WIDTH = 8) (
   assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0); 
 endmodule
 
-module mux6 #(parameter WIDTH = 8) (
+module ppa_mux6 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5,
   input  logic [2:0]       s, 
   output logic [WIDTH-1:0] y);
@@ -304,7 +305,7 @@ module mux6 #(parameter WIDTH = 8) (
   assign y = s[2] ? (s[0] ? d5 : d4) : (s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0)); 
 endmodule
 
-module mux8 #(parameter WIDTH = 8) (
+module ppa_mux8 #(parameter WIDTH = 8) (
   input  logic [WIDTH-1:0] d0, d1, d2, d3, d4, d5, d6, d7,
   input  logic [2:0]       s, 
   output logic [WIDTH-1:0] y);
@@ -314,7 +315,7 @@ endmodule
 
 // *** some way to express data-critical inputs
 
-module flop #(parameter WIDTH = 8) ( 
+module ppa_flop #(parameter WIDTH = 8) ( 
   input  logic             clk,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
@@ -323,7 +324,7 @@ module flop #(parameter WIDTH = 8) (
     q <= #1 d;
 endmodule
 
-module flopr #(parameter WIDTH = 8) ( 
+module ppa_flopr #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
@@ -333,7 +334,7 @@ module flopr #(parameter WIDTH = 8) (
     else       q <= #1 d;
 endmodule
 
-module floprasynnc #(parameter WIDTH = 8) ( 
+module ppa_floprasynnc #(parameter WIDTH = 8) ( 
   input  logic             clk, reset,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
@@ -343,7 +344,7 @@ module floprasynnc #(parameter WIDTH = 8) (
     else       q <= #1 d;
 endmodule
 
-module flopenr #(parameter WIDTH = 8) (
+module ppa_flopenr #(parameter WIDTH = 8) (
   input  logic             clk, reset, en,
   input  logic [WIDTH-1:0] d, 
   output logic [WIDTH-1:0] q);
diff --git a/synthDC/ppa.py b/synthDC/ppa.py
index e0f4982d..91b21d88 100755
--- a/synthDC/ppa.py
+++ b/synthDC/ppa.py
@@ -4,7 +4,8 @@ import subprocess
 from multiprocessing import Pool
 import csv
 import re
-# import matplotlib.pyplot as plt
+import matplotlib.pyplot as plt
+import numpy as np
 
 
 def run_command(module, width, freq):
diff --git a/synthDC/ppaData.csv b/synthDC/ppaData.csv
index 7cea16f7..0919db4c 100644
--- a/synthDC/ppaData.csv
+++ b/synthDC/ppaData.csv
@@ -35,3 +35,11 @@ mult,64,10,4.793300,46798.920227
 mult,64,4000,1.411752,93087.261425
 mult,64,5000,1.404875,94040.801492
 mult,64,6000,1.415466,89931.661403
+shifter,32,10,1.906335,1656.200032
+shifter,32,10,1.906335,1656.200032
+shifter,32,4000,0.260606,3490.760054
+shifter,32,4000,0.260606,3490.760054
+shifter,32,5000,0.238962,4985.260077
+shifter,32,5000,0.238962,4985.260077
+shifter,32,6000,0.241742,4312.000069
+shifter,32,6000,0.241742,4312.000069