From 9ffac8315b5b9ce35492e054ccb843c8cbc7e887 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 06:49:26 -0700 Subject: [PATCH] Simplified rotate source to shifter --- src/ieu/alu.sv | 8 +++----- src/ieu/bmu/bitmanipalu.sv | 10 ++-------- src/ieu/shifter.sv | 30 ++++++++++++++++-------------- 3 files changed, 21 insertions(+), 27 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index a0370f2b..71453573 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -54,7 +54,6 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic shSignA; - logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -73,7 +72,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2])); + shifter sh(.A(CondExtA), .Sign(shSignA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -106,13 +105,12 @@ module alu #(parameter WIDTH=32) ( // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu - bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .ALUSelect, .BSelect, .ZBBSelect, + bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .BSelect, .ZBBSelect, .Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult, - .CondMaskB, .CondShiftA, .rotA, .Result); + .CondMaskB, .CondShiftA, .Result); end else begin assign Result = ALUResult; assign CondMaskB = B; assign CondShiftA = A; - assign rotA = A; end endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 83638ce2..a8439b76 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -32,17 +32,15 @@ module bitmanipalu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [2:0] ALUSelect, // ALU mux select signal input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal - input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform input logic [1:0] CompFlags, // Comparator flags input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions - output logic [WIDTH-1:0] rotA, // Rotate source signal output logic [WIDTH-1:0] Result); // Result logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result @@ -68,12 +66,8 @@ module bitmanipalu #(parameter WIDTH=32) ( mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; - // shifter rotate source select mux - if (`ZBB_SUPPORTED & WIDTH == 64) begin - mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); - end else assign rotA = A; - // Pre-Shift Mux + // 0-3 bit Pre-Shift Mux if (`ZBA_SUPPORTED) begin: zbapreshift assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; assign CondShiftA = CondExtA << (PreShiftAmt); diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 594ef3dd..d0a6471c 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -30,8 +30,7 @@ `include "wally-config.vh" module shifter ( - input logic [`XLEN-1:0] shA, // shift Source - input logic [`XLEN-1:0] rotA, // rotate source + input logic [`XLEN-1:0] A, // shift Source input logic [`LOG_XLEN-1:0] Amt, // Shift amount input logic Right, Rotate, W64, Sign, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result @@ -43,32 +42,35 @@ module shifter ( if (`XLEN==32) begin // rv32 with rotates always_comb // funnel mux case({Right, Rotate}) - 2'b00: z = {shA[31:0], 31'b0}; - 2'b01: z = {rotA,rotA[31:1]}; - 2'b10: z = {{31{Sign}}, shA[31:0]}; - 2'b11: z = {rotA[30:0],rotA}; + 2'b00: z = {A[31:0], 31'b0}; + 2'b01: z = {A[31:0], A[31:1]}; + 2'b10: z = {{31{Sign}}, A[31:0]}; + 2'b11: z = {A[30:0], A}; endcase assign amttrunc = Amt; // shift amount end else begin // rv64 with rotates + // shifter rotate source select mux + logic [`XLEN-1:0] RotA; // rotate source + mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons always_comb // funnel mux case ({Right, Rotate}) - 2'b00: z = {shA[63:0],{63'b0}}; - 2'b01: z = {rotA, rotA[63:1]}; - 2'b10: z = {{63{Sign}},shA[63:0]}; - 2'b11: z = {rotA[62:0],rotA[63:0]}; + 2'b00: z = {A[63:0],{63'b0}}; + 2'b01: z = {RotA, RotA[63:1]}; + 2'b10: z = {{63{Sign}}, A[63:0]}; + 2'b11: z = {RotA[62:0], RotA}; endcase assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) z = {{31{Sign}}, shA[31:0]}; - else z = {shA[31:0], 31'b0}; + if (Right) z = {{31{Sign}}, A[31:0]}; + else z = {A[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (Right) z = {{63{Sign}},shA[63:0]}; - else z = {shA[63:0],{63'b0}}; + if (Right) z = {{63{Sign}}, A[63:0]}; + else z = {A[63:0], {63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end