From e4a9abc16c29e975c2a7b27997bc251cf7cbe7be Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 13 Jul 2021 19:11:50 -0400 Subject: [PATCH 1/4] added priority circuit to attempt to remove delay due to rippling in pmpadrdec --- wally-pipelined/src/mmu/pmpadrdec.sv | 11 ++++++----- wally-pipelined/src/mmu/pmpchecker.sv | 10 ++++++---- .../src/mmu/{tlbpriority.sv => prioritycircuit.sv} | 4 ++-- wally-pipelined/src/mmu/tlblru.sv | 2 +- 4 files changed, 15 insertions(+), 12 deletions(-) rename wally-pipelined/src/mmu/{tlbpriority.sv => prioritycircuit.sv} (96%) diff --git a/wally-pipelined/src/mmu/pmpadrdec.sv b/wally-pipelined/src/mmu/pmpadrdec.sv index 5d2174f4..b2016e5c 100644 --- a/wally-pipelined/src/mmu/pmpadrdec.sv +++ b/wally-pipelined/src/mmu/pmpadrdec.sv @@ -34,9 +34,10 @@ module pmpadrdec ( input logic [7:0] PMPCfg, input logic [`XLEN-1:0] PMPAdr, input logic PAgePMPAdrIn, - input logic NoLowerMatchIn, +// input logic NoLowerMatchIn, + input logic FirstMatch, output logic PAgePMPAdrOut, - output logic NoLowerMatchOut, +// output logic NoLowerMatchOut, output logic Match, Active, output logic L, X, W, R ); @@ -47,7 +48,7 @@ module pmpadrdec ( logic TORMatch, NAMatch; logic PAltPMPAdr; - logic FirstMatch; +// logic FirstMatch; logic [`PA_BITS-1:0] CurrentAdrFull; logic [1:0] AdrMode; @@ -87,8 +88,8 @@ module pmpadrdec ( (AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch : 0; - assign FirstMatch = NoLowerMatchIn & Match; - assign NoLowerMatchOut = NoLowerMatchIn & ~Match; +// assign FirstMatch = NoLowerMatchIn & Match; +// assign NoLowerMatchOut = NoLowerMatchIn & ~Match; assign L = PMPCfg[7] & FirstMatch; assign X = PMPCfg[2] & FirstMatch; assign W = PMPCfg[1] & FirstMatch; diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index 9c7f11da..7a2457a9 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -55,7 +55,7 @@ module pmpchecker ( // Bit i is high when the address falls in PMP region i logic EnforcePMP; logic [7:0] PMPCfg[`PMP_ENTRIES-1:0]; - logic [`PMP_ENTRIES-1:0] Match; // PMP Entry matches + logic [`PMP_ENTRIES-1:0] Match, FirstMatch; // PMP Entry matches logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set // verilator lint_off UNOPTFLAT @@ -70,9 +70,11 @@ module pmpchecker ( .PMPAdr(PMPADDR_ARRAY_REGW), .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), - .NoLowerMatchIn({NoLowerMatch[`PMP_ENTRIES-2:0], 1'b1}), - .NoLowerMatchOut(NoLowerMatch), - .Match, .Active, .L, .X, .W, .R); +// .NoLowerMatchIn({NoLowerMatch[`PMP_ENTRIES-2:0], 1'b1}), +// .NoLowerMatchOut(NoLowerMatch), + .FirstMatch, .Match, .Active, .L, .X, .W, .R); + + prioritycircuit #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit. *** seems like it won't actually help since there still needs to be a ripple of some kind with this logic. // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; diff --git a/wally-pipelined/src/mmu/tlbpriority.sv b/wally-pipelined/src/mmu/prioritycircuit.sv similarity index 96% rename from wally-pipelined/src/mmu/tlbpriority.sv rename to wally-pipelined/src/mmu/prioritycircuit.sv index 5096cae6..49599a71 100644 --- a/wally-pipelined/src/mmu/tlbpriority.sv +++ b/wally-pipelined/src/mmu/prioritycircuit.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// tlbpriority.sv +// prioritycircuit.sv // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 // Modified: Teo Ene 15 Apr 2021: @@ -30,7 +30,7 @@ `include "wally-config.vh" -module tlbpriority #(parameter ENTRIES = 8) ( +module prioritycircuit #(parameter ENTRIES = 8) ( input logic [ENTRIES-1:0] a, output logic [ENTRIES-1:0] y ); diff --git a/wally-pipelined/src/mmu/tlblru.sv b/wally-pipelined/src/mmu/tlblru.sv index 2fb0a503..f0f517aa 100644 --- a/wally-pipelined/src/mmu/tlblru.sv +++ b/wally-pipelined/src/mmu/tlblru.sv @@ -39,7 +39,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( logic AllUsed; // High if the next access causes all RU bits to be 1 // Find the first line not recently used - tlbpriority #(TLB_ENTRIES) nru(~RUBits, WriteLines); + prioritycircuit #(TLB_ENTRIES) nru(~RUBits, WriteLines); // Track recently used lines, updating on a CAM Hit or TLB write assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}}; From ab142300ef5fefa67fc2ec50f53c40d97d322b38 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 19 Jul 2021 10:46:17 -0400 Subject: [PATCH 2/4] Revert "added priority circuit to attempt to remove delay due to rippling in pmpadrdec" This reverts commit 9461fd9fbd51e17a416a7df6982379fbfa6b0974. --- wally-pipelined/src/mmu/pmpadrdec.sv | 11 +++++------ wally-pipelined/src/mmu/pmpchecker.sv | 10 ++++------ wally-pipelined/src/mmu/tlblru.sv | 2 +- .../src/mmu/{prioritycircuit.sv => tlbpriority.sv} | 4 ++-- 4 files changed, 12 insertions(+), 15 deletions(-) rename wally-pipelined/src/mmu/{prioritycircuit.sv => tlbpriority.sv} (96%) diff --git a/wally-pipelined/src/mmu/pmpadrdec.sv b/wally-pipelined/src/mmu/pmpadrdec.sv index b2016e5c..5d2174f4 100644 --- a/wally-pipelined/src/mmu/pmpadrdec.sv +++ b/wally-pipelined/src/mmu/pmpadrdec.sv @@ -34,10 +34,9 @@ module pmpadrdec ( input logic [7:0] PMPCfg, input logic [`XLEN-1:0] PMPAdr, input logic PAgePMPAdrIn, -// input logic NoLowerMatchIn, - input logic FirstMatch, + input logic NoLowerMatchIn, output logic PAgePMPAdrOut, -// output logic NoLowerMatchOut, + output logic NoLowerMatchOut, output logic Match, Active, output logic L, X, W, R ); @@ -48,7 +47,7 @@ module pmpadrdec ( logic TORMatch, NAMatch; logic PAltPMPAdr; -// logic FirstMatch; + logic FirstMatch; logic [`PA_BITS-1:0] CurrentAdrFull; logic [1:0] AdrMode; @@ -88,8 +87,8 @@ module pmpadrdec ( (AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch : 0; -// assign FirstMatch = NoLowerMatchIn & Match; -// assign NoLowerMatchOut = NoLowerMatchIn & ~Match; + assign FirstMatch = NoLowerMatchIn & Match; + assign NoLowerMatchOut = NoLowerMatchIn & ~Match; assign L = PMPCfg[7] & FirstMatch; assign X = PMPCfg[2] & FirstMatch; assign W = PMPCfg[1] & FirstMatch; diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index 7a2457a9..9c7f11da 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -55,7 +55,7 @@ module pmpchecker ( // Bit i is high when the address falls in PMP region i logic EnforcePMP; logic [7:0] PMPCfg[`PMP_ENTRIES-1:0]; - logic [`PMP_ENTRIES-1:0] Match, FirstMatch; // PMP Entry matches + logic [`PMP_ENTRIES-1:0] Match; // PMP Entry matches logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set // verilator lint_off UNOPTFLAT @@ -70,11 +70,9 @@ module pmpchecker ( .PMPAdr(PMPADDR_ARRAY_REGW), .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), -// .NoLowerMatchIn({NoLowerMatch[`PMP_ENTRIES-2:0], 1'b1}), -// .NoLowerMatchOut(NoLowerMatch), - .FirstMatch, .Match, .Active, .L, .X, .W, .R); - - prioritycircuit #(`PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit. *** seems like it won't actually help since there still needs to be a ripple of some kind with this logic. + .NoLowerMatchIn({NoLowerMatch[`PMP_ENTRIES-2:0], 1'b1}), + .NoLowerMatchOut(NoLowerMatch), + .Match, .Active, .L, .X, .W, .R); // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; diff --git a/wally-pipelined/src/mmu/tlblru.sv b/wally-pipelined/src/mmu/tlblru.sv index f0f517aa..2fb0a503 100644 --- a/wally-pipelined/src/mmu/tlblru.sv +++ b/wally-pipelined/src/mmu/tlblru.sv @@ -39,7 +39,7 @@ module tlblru #(parameter TLB_ENTRIES = 8) ( logic AllUsed; // High if the next access causes all RU bits to be 1 // Find the first line not recently used - prioritycircuit #(TLB_ENTRIES) nru(~RUBits, WriteLines); + tlbpriority #(TLB_ENTRIES) nru(~RUBits, WriteLines); // Track recently used lines, updating on a CAM Hit or TLB write assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}}; diff --git a/wally-pipelined/src/mmu/prioritycircuit.sv b/wally-pipelined/src/mmu/tlbpriority.sv similarity index 96% rename from wally-pipelined/src/mmu/prioritycircuit.sv rename to wally-pipelined/src/mmu/tlbpriority.sv index 49599a71..5096cae6 100644 --- a/wally-pipelined/src/mmu/prioritycircuit.sv +++ b/wally-pipelined/src/mmu/tlbpriority.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// prioritycircuit.sv +// tlbpriority.sv // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 // Modified: Teo Ene 15 Apr 2021: @@ -30,7 +30,7 @@ `include "wally-config.vh" -module prioritycircuit #(parameter ENTRIES = 8) ( +module tlbpriority #(parameter ENTRIES = 8) ( input logic [ENTRIES-1:0] a, output logic [ENTRIES-1:0] y ); From f31a0ded7579d9f49c41afc79d0e7a2ac1874121 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 19 Jul 2021 13:20:53 -0400 Subject: [PATCH 4/4] change buildroot expectations to match reality --- wally-pipelined/regression/regression-wally.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index b1ded5e7..234c869a 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -31,7 +31,7 @@ configs = [ TestCase( name="buildroot", cmd="vsim -do wally-buildroot-batch.do -c > {}", - grepstr="loaded 2500000 instructions" + grepstr="loaded 6000 instructions" ), TestCase( name="rv32ic",