diff --git a/wally-pipelined/src/ebu/ahblite.sv b/wally-pipelined/src/ebu/ahblite.sv
index 70f32bf7..09e5799c 100644
--- a/wally-pipelined/src/ebu/ahblite.sv
+++ b/wally-pipelined/src/ebu/ahblite.sv
@@ -53,13 +53,6 @@ module ahblite (
   input  logic [1:0]       MemSizeM,
   //output logic             DataStall,
   // Signals from MMU
-/* -----\/----- EXCLUDED -----\/-----
-  input  logic             MMUStall,
-  input  logic [`XLEN-1:0] MMUPAdr,
-  input  logic             MMUTranslate,
-  output logic [`XLEN-1:0] MMUReadPTE,
-  output logic             MMUReady,
- -----/\----- EXCLUDED -----/\----- */
   // Signals from PMA checker
   input  logic             DSquashBusAccessM, ISquashBusAccessF,
   // Signals to PMA checker (metadata of proposed access)
@@ -158,8 +151,6 @@ module ahblite (
  -----/\----- EXCLUDED -----/\----- */
   
 
-  //assign #1 InstrStall = ((NextBusState == INSTRREAD) || (NextBusState == INSTRREADC) ||
-  //                        MMUStall);
 
   //  bus outputs
   assign #1 GrantData = (ProposedNextBusState == MEMREAD) || (ProposedNextBusState == MEMWRITE) || 
diff --git a/wally-pipelined/src/mmu/pagetablewalker.sv b/wally-pipelined/src/mmu/pagetablewalker.sv
index d0d2152f..45479d4a 100644
--- a/wally-pipelined/src/mmu/pagetablewalker.sv
+++ b/wally-pipelined/src/mmu/pagetablewalker.sv
@@ -64,11 +64,6 @@ module pagetablewalker
    output logic 	    HPTWRead,
 
 
-
-
-   // Stall signal
-   output logic 	    MMUStall,
-
    // Faults
    output logic 	    WalkerInstrPageFaultF,
    output logic 	    WalkerLoadPageFaultM, 
@@ -190,7 +185,6 @@ module pagetablewalker
 	PRegEn = 1'b0;
 	TranslationPAdr = '0;
 	HPTWRead = 1'b0;
-	MMUStall = 1'b1;
         PageTableEntry = '0;
         PageType = '0;
         DTLBWriteM = '0;
@@ -209,7 +203,6 @@ module pagetablewalker
 	    end else begin
               NextWalkerState = IDLE;
 	      TranslationPAdr = '0;
-	      MMUStall = 1'b0;
 	    end
 	  end
 	  
@@ -271,14 +264,12 @@ module pagetablewalker
 	  
           LEAF: begin
             NextWalkerState = IDLE;
-            MMUStall = 1'b0;
 	  end
           FAULT: begin
             NextWalkerState = IDLE;
             WalkerInstrPageFaultF = ~DTLBMissMQ;
             WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
             WalkerStorePageFaultM = DTLBMissMQ && MemStore;
-	    MMUStall = 1'b0;
 	  end
 	  
           // Default case should never happen, but is included for linter.
@@ -293,8 +284,6 @@ module pagetablewalker
       assign VPN1 = TranslationVAdrQ[31:22];
       assign VPN0 = TranslationVAdrQ[21:12];
 
-      //assign HPTWRead = (WalkerState == IDLE && MMUTranslate) || 
-      //			WalkerState == LEVEL2 || WalkerState == LEVEL1;
       
 
       // Capture page table entry from data cache
@@ -335,7 +324,6 @@ module pagetablewalker
 	PRegEn = 1'b0;
 	TranslationPAdr = '0;
 	HPTWRead = 1'b0;
-	MMUStall = 1'b1;
         PageTableEntry = '0;
         PageType = '0;
         DTLBWriteM = '0;
@@ -358,7 +346,6 @@ module pagetablewalker
 	    end else begin
               NextWalkerState = IDLE;
 	      TranslationPAdr = '0;
-	      MMUStall = 1'b0;
 	    end
 	  end
 
@@ -499,7 +486,6 @@ module pagetablewalker
           
           LEAF: begin 
             NextWalkerState = IDLE;
-            MMUStall = 1'b0;
           end
 
           FAULT: begin
@@ -507,7 +493,6 @@ module pagetablewalker
             WalkerInstrPageFaultF = ~DTLBMissMQ;
             WalkerLoadPageFaultM = DTLBMissMQ && ~MemStore;
             WalkerStorePageFaultM = DTLBMissMQ && MemStore;
-	    MMUStall = 1'b0;
           end
 
           // Default case should never happen
diff --git a/wally-pipelined/src/wally/wallypipelinedhart.sv b/wally-pipelined/src/wally/wallypipelinedhart.sv
index 47035ec6..9a678189 100644
--- a/wally-pipelined/src/wally/wallypipelinedhart.sv
+++ b/wally-pipelined/src/wally/wallypipelinedhart.sv
@@ -129,7 +129,6 @@ module wallypipelinedhart
   logic 		    ICacheStallF;
   logic 		    DCacheStall;
   logic [`XLEN-1:0] 	    MMUPAdr, MMUReadPTE;
-  logic 		    MMUStall;
   logic 		    MMUTranslate, MMUReady;
   logic 		    HPTWRead;
   logic 		    HPTWReadyfromLSU;
@@ -199,19 +198,18 @@ module wallypipelinedhart
 				  .PageTableEntryF(PageTableEntryF),   // add to lsu port
 				  .PageTableEntryM(PageTableEntryM),   // already on lsu port convert to internal
 				  .PageTypeF(PageTypeF),               // add to lsu port connects to ifu
-				  .PageTypeM(PageTypeM),
-				  .ITLBWriteF(ITLBWriteF),
-				  .DTLBWriteM(DTLBWriteM),
-				  .MMUReadPTE(MMUReadPTE),
-				  .MMUReady(MMUReady),
-				  .HPTWStall(HPTWStall),
-				  .MMUPAdr(MMUPAdr),
-				  .MMUTranslate(MMUTranslate),
-				  .HPTWRead(HPTWRead),
-				  .MMUStall(MMUStall),
-				  .WalkerInstrPageFaultF(WalkerInstrPageFaultF),
-				  .WalkerLoadPageFaultM(WalkerLoadPageFaultM), 
-				  .WalkerStorePageFaultM(WalkerStorePageFaultM));
+				  .PageTypeM(PageTypeM),               // already on lsu port convert to internal
+				  .ITLBWriteF(ITLBWriteF),             // add to lsu port connects to ifu
+				  .DTLBWriteM(DTLBWriteM),             // already on lsu port convert to internal
+				  .MMUReadPTE(MMUReadPTE),             // from lsu arb convert to internal
+				  .MMUReady(MMUReady),                 // to lsu arb, convert to internal
+				  .HPTWStall(HPTWStall),               // from lsu arb convert to internal
+				  .MMUPAdr(MMUPAdr),                   // to lsu arb, convert to internal
+				  .MMUTranslate(MMUTranslate),         // to lsu arb, convert to internal
+				  .HPTWRead(HPTWRead),                 // to lsu arb, convert to internal
+				  .WalkerInstrPageFaultF(WalkerInstrPageFaultF), // add to lsu port
+				  .WalkerLoadPageFaultM(WalkerLoadPageFaultM),   // add to lsu port (to privilege)
+				  .WalkerStorePageFaultM(WalkerStorePageFaultM)); // add to lsu port (to privilege)