From 28c6d601505b9fd69b65870a50e8c0ca75e63c03 Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 7 Jun 2021 13:20:50 -0400 Subject: [PATCH 1/2] temporarily removing buildroot from regression until it is regenerated --- wally-pipelined/regression/regression-wally.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 56dfa4d9..5b45f9a5 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -28,11 +28,11 @@ configs = [ cmd="vsim -do wally-busybear-batch.do -c > {}", grepstr="# loaded 100000 instructions" ), - TestCase( - name="buildroot", - cmd="vsim -do wally-buildroot-batch.do -c > {}", - grepstr="# loaded 100000 instructions" - ), +# TestCase( +# name="buildroot", +# cmd="vsim -do wally-buildroot-batch.do -c > {}", +# grepstr="# loaded 100000 instructions" +# ), TestCase( name="rv32ic", cmd="vsim > {} -c < Date: Mon, 7 Jun 2021 14:22:54 -0400 Subject: [PATCH 2/2] lint is clean --- wally-pipelined/src/fpu/fma1.sv | 24 ++++++++++---------- wally-pipelined/src/fpu/fpdiv.sv | 34 +++++++++++++++------------- wally-pipelined/src/fpu/fpu.sv | 18 +++++++++++---- wally-pipelined/src/fpu/fsm.sv | 32 ++++++++++++++++++++++++-- wally-pipelined/src/hazard/hazard.sv | 2 +- wally-pipelined/src/muldiv/div.sv | 2 +- 6 files changed, 76 insertions(+), 36 deletions(-) diff --git a/wally-pipelined/src/fpu/fma1.sv b/wally-pipelined/src/fpu/fma1.sv index 0a64f0ba..83adbcd2 100644 --- a/wally-pipelined/src/fpu/fma1.sv +++ b/wally-pipelined/src/fpu/fma1.sv @@ -40,21 +40,21 @@ module fma1( // determine if an input is a special value - assign XNaNE = &FInput1E[62:52] && |FInput1E[51:0]; - assign YNaNE = &FInput2E[62:52] && |FInput2E[51:0]; - assign ZNaNE = &FInput3E2[62:52] && |FInput3E2[51:0]; + assign XNaNE = &XExp && |XMan; + assign YNaNE = &YExp && |XMan; + assign ZNaNE = &ZExp && |ZMan; - assign XDenormE = ~(|FInput1E[62:52]) && |FInput1E[51:0]; - assign YDenormE = ~(|FInput2E[62:52]) && |FInput2E[51:0]; - assign ZDenormE = ~(|FInput3E2[62:52]) && |FInput3E2[51:0]; + assign XDenormE = ~(|XExp) && |XMan; + assign YDenormE = ~(|YExp) && |YMan; + assign ZDenormE = ~(|ZExp) && |ZMan; - assign XInfE = &FInput1E[62:52] && ~(|FInput1E[51:0]); - assign YInfE = &FInput2E[62:52] && ~(|FInput2E[51:0]); - assign ZInfE = &FInput3E2[62:52] && ~(|FInput3E2[51:0]); + assign XInfE = &XExp && ~(|XMan); + assign YInfE = &YExp && ~(|YMan); + assign ZInfE = &ZExp && ~(|ZMan); - assign XZeroE = ~(|FInput1E[62:0]); - assign YZeroE = ~(|FInput2E[62:0]); - assign ZZeroE = ~(|FInput3E2[62:0]); + assign XZeroE = ~(|{XExp, XMan}); + assign YZeroE = ~(|{YExp, YMan}); + assign ZZeroE = ~(|{ZExp, ZMan}); diff --git a/wally-pipelined/src/fpu/fpdiv.sv b/wally-pipelined/src/fpu/fpdiv.sv index 96723ca7..8c305f3e 100755 --- a/wally-pipelined/src/fpu/fpdiv.sv +++ b/wally-pipelined/src/fpu/fpdiv.sv @@ -23,14 +23,14 @@ // // `timescale 1ps/1ps -module fpdiv (FDivSqrtDoneE, FDivResultE, FDivFlagsE, DivDenormE, FInput1E, FInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn, - FDivStartE, reset, clk, FDivBusyE); +module fpdiv (FDivSqrtDoneE, FDivResultM, FDivFlagsM, DivDenormM, DivInput1E, DivInput2E, FrmE, DivOpType, FmtE, DivOvEn, DivUnEn, + FDivStartE, reset, clk, FDivBusyE, HoldInputs); - input [63:0] FInput1E; // 1st input operand (A) - input [63:0] FInput2E; // 2nd input operand (B) + input [63:0] DivInput1E; // 1st input operand (A) + input [63:0] DivInput2E; // 2nd input operand (B) input [2:0] FrmE; // Rounding mode - specify values input DivOpType; // Function opcode - input FmtE; // Result Precision (0 for double, 1 for single) + input FmtE; // Result Precision (0 for double, 1 for single) //***will need to swap this input DivOvEn; // Overflow trap enabled input DivUnEn; // Underflow trap enabled @@ -38,11 +38,11 @@ module fpdiv (FDivSqrtDoneE, FDivResultE, FDivFlagsE, DivDenormE, FInput1E, FInp input reset; input clk; - output [63:0] FDivResultE; // Result of operation - output [4:0] FDivFlagsE; // IEEE exception flags - output DivDenormE; // DivDenormE on input or output + output [63:0] FDivResultM; // Result of operation + output [4:0] FDivFlagsM; // IEEE exception flags + output DivDenormM; // DivDenormM on input or output output FDivSqrtDoneE; - output FDivBusyE; + output FDivBusyE, HoldInputs; supply1 vdd; supply0 vss; @@ -93,17 +93,19 @@ module fpdiv (FDivSqrtDoneE, FDivResultE, FDivFlagsE, DivDenormE, FInput1E, FInp wire load_regrv, load_regsv; logic exp_cout1, exp_cout2, exp_odd, open; + + // Convert the input operands to their appropriate forms based on // the orignal operands, the DivOpType , and their precision FmtE. // Single precision inputs are converted to double precision // and the sign of the first operand is set appropratiately based on // if the operation is absolute value or negation. - convert_inputs_div divconv1 (Float1, Float2, FInput1E, FInput2E, DivOpType, FmtE); + convert_inputs_div divconv1 (Float1, Float2, DivInput1E, DivInput2E, DivOpType, FmtE); // Test for exceptions and return the "Invalid Operation" and - // "Denormalized" Input FDivFlagsE. The "sel_inv" is used in + // "Denormalized" Input FDivFlagsM. The "sel_inv" is used in // the third pipeline stage to select the result. Also, op1_Norm - // and op2_Norm are one if FInput1E and FInput2E are not zero or denormalized. + // and op2_Norm are one if DivInput1E and DivInput2E are not zero or denormalized. // sub is one if the effective operation is subtaction. exception_div divexc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, Float1, Float2, DivOpType); @@ -140,7 +142,7 @@ module fpdiv (FDivSqrtDoneE, FDivResultE, FDivFlagsE, DivDenormE, FInput1E, FInp // FSM : control divider fsm control (FDivSqrtDoneE, load_rega, load_regb, load_regc, load_regd, load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, - clk, reset, FDivStartE, DivOpType, FDivBusyE); + clk, reset, FDivStartE, DivOpType, FDivBusyE, HoldInputs); // Round the mantissa to a 52-bit value, with the leading one // removed. The rounding units also handles special cases and @@ -152,9 +154,9 @@ module fpdiv (FDivSqrtDoneE, FDivResultE, FDivFlagsE, DivDenormE, FInput1E, FInp q1, qm1, qp1, q0, qm0, qp0, regr_out); // Store the final result and the exception flags in registers. - flopenr #(64) rega (clk, reset, FDivSqrtDoneE, Result, FDivResultE); - flopenr #(1) regb (clk, reset, FDivSqrtDoneE, DenormIO, DivDenormE); - flopenr #(5) regc (clk, reset, FDivSqrtDoneE, FlagsIn, FDivFlagsE); + flopenr #(64) rega (clk, reset, FDivSqrtDoneE, Result, FDivResultM); + flopenr #(1) regb (clk, reset, FDivSqrtDoneE, DenormIO, DivDenormM); + flopenr #(5) regc (clk, reset, FDivSqrtDoneE, FlagsIn, FDivFlagsM); endmodule // fpadd diff --git a/wally-pipelined/src/fpu/fpu.sv b/wally-pipelined/src/fpu/fpu.sv index 10632467..59a6c1e0 100755 --- a/wally-pipelined/src/fpu/fpu.sv +++ b/wally-pipelined/src/fpu/fpu.sv @@ -78,6 +78,8 @@ module fpu ( logic [63:0] FDivResultE, FDivResultM, FDivResultW; logic [4:0] FDivFlagsE, FDivFlagsM, FDivFlagsW; logic FDivSqrtDoneE, FDivSqrtDoneM; + logic [63:0] DivInput1E, DivInput2E; + logic HoldInputs; // FMA signals logic [105:0] ProdManE, ProdManM; @@ -224,7 +226,15 @@ module fpu ( .CLK(clk), .ECLK(fpdivClk)); - fpdiv fpdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .*); + // capture the inputs for div/sqrt + flopenrc #(64) reg_input1 (.d(FInput1E), .q(DivInput1E), + .en(~HoldInputs), .clear(FDivSqrtDoneE), + .reset(reset), .clk(clk)); + flopenrc #(64) reg_input2 (.d(FInput2E), .q(DivInput2E), + .en(~HoldInputs), .clear(FDivSqrtDoneE), + .reset(reset), .clk(clk)); + + fpdiv fpdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .*); // first of two-stage instance of floating-point add/cvt unit fpuaddcvt1 fpadd1 (.*); @@ -266,9 +276,9 @@ module fpu ( //***************** // fpdiv E/M pipe registers //***************** - flopenrc #(64) EMRegDiv1(clk, reset, PipeClearEM, PipeEnableEM, FDivResultE, FDivResultM); - flopenrc #(5) EMRegDiv2(clk, reset, PipeClearEM, PipeEnableEM, FDivFlagsE, FDivFlagsM); - flopenrc #(1) EMRegDiv3(clk, reset, PipeClearEM, PipeEnableEM, DivDenormE, DivDenormM); + // flopenrc #(64) EMRegDiv1(clk, reset, PipeClearEM, PipeEnableEM, FDivResultE, FDivResultM); + // flopenrc #(5) EMRegDiv2(clk, reset, PipeClearEM, PipeEnableEM, FDivFlagsE, FDivFlagsM); + // flopenrc #(1) EMRegDiv3(clk, reset, PipeClearEM, PipeEnableEM, DivDenormE, DivDenormM); //***************** // fpadd E/M pipe registers diff --git a/wally-pipelined/src/fpu/fsm.sv b/wally-pipelined/src/fpu/fsm.sv index a03980db..7500eeaa 100755 --- a/wally-pipelined/src/fpu/fsm.sv +++ b/wally-pipelined/src/fpu/fsm.sv @@ -1,7 +1,7 @@ module fsm (done, load_rega, load_regb, load_regc, load_regd, load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr, - clk, reset, start, op_type, divBusy); + clk, reset, start, op_type, divBusy, holdInputs); input clk; input reset; @@ -20,7 +20,7 @@ module fsm (done, load_rega, load_regb, load_regc, output [2:0] sel_muxa; output [2:0] sel_muxb; output sel_muxr; - output logic divBusy; + output logic divBusy,holdInputs; reg done; // End of cycles reg load_rega; // enable for regA @@ -65,6 +65,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b0; + holdInputs = 1'b0; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -80,6 +81,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b0; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -95,6 +97,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b0; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -111,6 +114,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b1; load_regb = 1'b0; load_regc = 1'b1; @@ -126,6 +130,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -141,6 +146,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b1; load_regb = 1'b0; load_regc = 1'b1; @@ -156,6 +162,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -171,6 +178,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b1; load_regb = 1'b0; load_regc = 1'b1; @@ -186,6 +194,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -201,6 +210,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b1; load_regb = 1'b0; load_regc = 1'b1; @@ -216,6 +226,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -231,6 +242,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -246,6 +258,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b1; divBusy = 1'b0; + holdInputs = 1'b0; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -261,6 +274,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -276,6 +290,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b1; load_regb = 1'b0; load_regc = 1'b1; @@ -291,6 +306,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -306,6 +322,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -321,6 +338,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b1; load_regb = 1'b0; load_regc = 1'b1; @@ -336,6 +354,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -351,6 +370,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -366,6 +386,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b1; load_regb = 1'b0; load_regc = 1'b1; @@ -381,6 +402,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b1; load_regc = 1'b0; @@ -396,6 +418,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -411,6 +434,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b1; load_regb = 1'b0; load_regc = 1'b1; @@ -426,6 +450,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -441,6 +466,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b1; + holdInputs = 1'b1; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -456,6 +482,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b1; divBusy = 1'b0; + holdInputs = 1'b0; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; @@ -471,6 +498,7 @@ module fsm (done, load_rega, load_regb, load_regc, begin done = 1'b0; divBusy = 1'b0; + holdInputs = 1'b0; load_rega = 1'b0; load_regb = 1'b0; load_regc = 1'b0; diff --git a/wally-pipelined/src/hazard/hazard.sv b/wally-pipelined/src/hazard/hazard.sv index 47b9cba4..016d8e1a 100644 --- a/wally-pipelined/src/hazard/hazard.sv +++ b/wally-pipelined/src/hazard/hazard.sv @@ -57,7 +57,7 @@ module hazard( assign StallFCause = CSRWritePendingDEM && ~(TrapM || RetM || BPPredWrongE); assign StallDCause = (LoadStallD || MulDivStallD || CSRRdStallD || FPUStallD) && ~(TrapM || RetM || BPPredWrongE); // stall in decode if instruction is a load/mul/csr dependent on previous - assign StallECause = DivBusyE | FDivBusyE; + assign StallECause = DivBusyE || FDivBusyE; assign StallMCause = 0; assign StallWCause = DataStall || ICacheStallF; diff --git a/wally-pipelined/src/muldiv/div.sv b/wally-pipelined/src/muldiv/div.sv index 10af5eee..3bea0e47 100755 --- a/wally-pipelined/src/muldiv/div.sv +++ b/wally-pipelined/src/muldiv/div.sv @@ -304,7 +304,7 @@ module csa #(parameter WIDTH=8) (input logic [WIDTH-1:0] a, b, c, fa fa_inst (a[i], b[i], c[i], sum[i], carry_temp[i+1]); end endgenerate - assign carry = {1'b0, carry_temp[WIDTH-1:1], 1'b0}; + assign carry = {carry_temp[WIDTH-1:1], 1'b0}; endmodule // csa