From 9dfbfd57728ece878224604abbe455c52a95dfd3 Mon Sep 17 00:00:00 2001
From: ushakya22 <ushakya@hmc.edu>
Date: Thu, 29 Apr 2021 15:21:08 -0400
Subject: [PATCH] fix to pcm bug

---
 wally-pipelined/src/privileged/csr.sv        | 12 ++++++++++--
 wally-pipelined/src/privileged/privileged.sv |  3 ++-
 wally-pipelined/src/privileged/trap.sv       |  3 ++-
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/wally-pipelined/src/privileged/csr.sv b/wally-pipelined/src/privileged/csr.sv
index b457f7d3..9e7f26cb 100644
--- a/wally-pipelined/src/privileged/csr.sv
+++ b/wally-pipelined/src/privileged/csr.sv
@@ -36,6 +36,7 @@ module csr #(parameter
   input  logic             FlushW, StallD, StallE, StallM, StallW,
   input  logic [31:0]      InstrM, 
   input  logic [`XLEN-1:0] PCM, SrcAM,
+  input  logic             InterruptM,
   input  logic             CSRReadM, CSRWriteM, TrapM, MTrapM, STrapM, UTrapM, mretM, sretM, uretM,
   input  logic             TimerIntM, ExtIntM, SwIntM,
   input  logic             InstrValidW, FloatRegWriteW, LoadStallD,
@@ -69,7 +70,14 @@ module csr #(parameter
   logic            WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM;
   logic            CSRMWriteM, CSRSWriteM, CSRUWriteM;
 
-  logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, NextCauseM, NextMtvalM;
+  logic [`XLEN-1:0] UnalignedNextEPCM, NextEPCM, preservedPCM, readPCM, NextCauseM, NextMtvalM;
+
+  always_ff @(posedge clk) begin
+      preservedPCM <= PCM;
+  end
+
+  mux2 #(`XLEN) pcmux(PCM, preservedPCM, InterruptM, readPCM);
+  //flop #(`XLEN) CSRReadPCMreg(clk, reset, PCM, readPCM);
 
   logic [11:0] CSRAdrM;
   logic [11:0] SIP_REGW, SIE_REGW;
@@ -98,7 +106,7 @@ module csr #(parameter
 
       // write CSRs
       assign CSRAdrM = InstrM[31:20];
-      assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
+      assign UnalignedNextEPCM = TrapM ? readPCM : CSRWriteValM;
       assign NextEPCM = `C_SUPPORTED ? {UnalignedNextEPCM[`XLEN-1:1], 1'b0} : {UnalignedNextEPCM[`XLEN-1:2], 2'b00}; // 3.1.15 alignment
       assign NextCauseM = TrapM ? CauseM : CSRWriteValM;
       assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
diff --git a/wally-pipelined/src/privileged/privileged.sv b/wally-pipelined/src/privileged/privileged.sv
index ef312c7b..feeeac19 100644
--- a/wally-pipelined/src/privileged/privileged.sv
+++ b/wally-pipelined/src/privileged/privileged.sv
@@ -85,7 +85,8 @@ module privileged (
   logic IllegalInstrFaultM;
 
   logic BreakpointFaultM, EcallFaultM;
-  logic MTrapM, STrapM, UTrapM; 
+  logic MTrapM, STrapM, UTrapM;
+  logic InterruptM; 
 
   logic [1:0] STATUS_MPP;
   logic       STATUS_SPP, STATUS_TSR;
diff --git a/wally-pipelined/src/privileged/trap.sv b/wally-pipelined/src/privileged/trap.sv
index 2c0506e1..552ce9a4 100644
--- a/wally-pipelined/src/privileged/trap.sv
+++ b/wally-pipelined/src/privileged/trap.sv
@@ -41,13 +41,14 @@ module trap (
   input  logic [`XLEN-1:0] InstrMisalignedAdrM, MemAdrM, 
   input  logic [31:0]      InstrM,
   output logic             TrapM, MTrapM, STrapM, UTrapM, RetM,
+  output logic             InterruptM,
   output logic [`XLEN-1:0] PrivilegedNextPCM, CauseM, NextFaultMtvalM
 //  output logic [11:0]     MIP_REGW, SIP_REGW, UIP_REGW, MIE_REGW, SIE_REGW, UIE_REGW,
 //  input  logic            WriteMIPM, WriteSIPM, WriteUIPM, WriteMIEM, WriteSIEM, WriteUIEM
 );
 
   logic [11:0] MIntGlobalEnM, SIntGlobalEnM, PendingIntsM; 
-  logic InterruptM;
+  //logic InterruptM;
   logic [`XLEN-1:0] PrivilegedTrapVector, PrivilegedVectoredTrapVector;
 
   // Determine pending enabled interrupts